soclayout.git
14 hours ago Luke Kenneth... argh, found the blackbox problem: yosys is "doing the... master
14 hours ago Luke Kenneth... try renaming spblock without the underscore
14 hours ago Luke Kenneth... try changing layout of blackbox spblock_512w64b8w
16 hours ago Luke Kenneth... experimenting with blackboxes
16 hours ago Luke Kenneth... rename spblock_512w64b8w, and vco_test_ana for pll
17 hours ago Luke Kenneth... rename blackboxes to lowercase, spblock_512w64b8w, pll
17 hours ago Luke Kenneth... update ls180 sram4k
23 hours ago Luke Kenneth... add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst...
23 hours ago Luke Kenneth... must use VST_FLAGS uniquify uppercase
23 hours ago Luke Kenneth... sort out adding SPBlock_512 SRAM verilog to ls180
26 hours ago Luke Kenneth... update tsmc_018 4k build script
26 hours ago Luke Kenneth... use correct arguments to litex build to create 4k srams...
27 hours ago Luke Kenneth... rename ls180sram4k to ls180
27 hours ago Luke Kenneth... add full core variant including 4k sram of ls180
27 hours ago Luke Kenneth... update libresoc.v, c4m-jtag fsm was renamed
27 hours ago Luke Kenneth... update libresoc.v, c4m-jtag fsm was renamed
4 days ago Luke Kenneth... add an SRAM and wishbone to add test (makes it bigger)
5 days ago Luke Kenneth... connect up boundary scan to inputs/outputs
5 days ago Luke Kenneth... submodule update
5 days ago Luke Kenneth... use METAL10 for topRoutingLayer
5 days ago Luke Kenneth... whoops forgot settings.py
6 days ago Luke Kenneth... submodule update
6 days ago Luke Kenneth... set routingGauge manually
6 days ago Luke Kenneth... enable HFNS in adder
6 days ago Luke Kenneth... include (but do not use) FreePDK45 in experiments10
6 days ago Luke Kenneth... different FreePDK45 experiments10 chip size
6 days ago Luke Kenneth... experimentation to get experiment10_verilog work with...
6 days ago Luke Kenneth... add FreePDK45 experiments10_verilog doDesign.py
6 days ago Luke Kenneth... add FreePDK45 variant of experiments10_verilog
6 days ago Luke Kenneth... update PLL signal output names
7 days ago Staf VerhaegendoDesign.py: Disable SRAM placement
7 days ago Staf VerhaegenReduce core size.
7 days ago Luke Kenneth... rename sys_clk in adder test experiments10_verilog...
7 days ago Luke Kenneth... rename JTAG port in adder test experiments10_verilog...
7 days ago Luke Kenneth... back to "working" verilog add
7 days ago Luke Kenneth... another attempt to get 100% completed route
7 days ago Staf VerhaegenRight branch of c4m-pdk-freedpk45.
7 days ago Luke Kenneth... good grief, increasing ls180 core size to 70,000, 100...
7 days ago Luke Kenneth... increase core size to see if global routing can be...
7 days ago Luke Kenneth... whitespace cleanup
7 days ago Luke Kenneth... use auto-generated pinmux ioPadsSpecs
7 days ago Luke Kenneth... submodule conflict (update again)
7 days ago Luke Kenneth... use verilog version of ls180 in FreePDK_c4m45
7 days ago Staf VerhaegenUpdate c4m-pdk-freepdk45 submodule.
7 days ago Luke Kenneth... crank up the numbers (again)
7 days ago Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45.
7 days ago Staf Verhaegenexperiments9: Ignore pinmux generated files.
7 days ago Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit
7 days ago Staf VerhaegenSubmodule for C4M FreePDK45 PDK release files.
8 days ago Luke Kenneth... crank up the numbers to see if routing completion can...
8 days ago Luke Kenneth... increase katana tracks reserved
8 days ago Luke Kenneth... use verilog for ls180 instead of ilang
9 days ago Luke Kenneth... make VST names unique, for GHDL to cope
9 days ago Luke Kenneth... sigh, broken experiment10_verilog
9 days ago Luke Kenneth... whitespace
9 days ago Luke Kenneth... whitespace cleanup
9 days ago Luke Kenneth... pad name starts with p_
10 days ago Luke Kenneth... rename design of experiments10 to match ls180 chip...
2021-04-02 Luke Kenneth... experiment with nmigen verilog generation
2021-04-01 Luke Kenneth... update / refresh full core DFF
2021-04-01 Luke Kenneth... update / refresh full core DFF
2021-04-01 Luke Kenneth... run doChipFloorplan in experiments10
2021-04-01 Luke Kenneth... increase experiment10 JTAG tap width to 4
2021-04-01 Luke Kenneth... update submodule
2021-03-30 Luke Kenneth... update 4k SRAM ls180.il
2021-03-30 Luke Kenneth... add yosys version number
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-29 Jean-Paul ChaputAdd a placeholder for the PLL in the doDesign.py for...
2021-03-29 Luke Kenneth... Revert "enable high fanout in ls180 experiment9 doDesig...
2021-03-29 Luke Kenneth... enable high fanout in ls180 experiment9 doDesign.py
2021-03-29 Luke Kenneth... aaagh found bug in litex setup, 64 bit WB bus was truncated
2021-03-28 Luke Kenneth... reduce SPR regfile size considerably
2021-03-28 Luke Kenneth... reduce INT and FAST regfile sizes by sharing ports
2021-03-27 Luke Kenneth... add missing floorplan function call
2021-03-27 Luke Kenneth... hooray, corrected pinouts
2021-03-27 Luke Kenneth... really weird error "unsupported direction for eint...
2021-03-23 Jean-Paul ChaputUodated doDesign for the latest ls180 (sram variant).
2021-03-22 Luke Kenneth... increase DFF RAM size slightly
2021-03-22 Luke Kenneth... add very small DFF srams variant
2021-03-22 Luke Kenneth... create small dff with 4x 4k SRAMs
2021-03-22 Luke Kenneth... ls180.il update
2021-03-22 Luke Kenneth... argh pinmux generating bi-directional SDR DM when it...
2021-03-18 Luke Kenneth... update ls180.il
2021-03-16 Luke Kenneth... update submodule
2021-03-16 Luke Kenneth... update ls180.il 4ksram with correct sdram connections
2021-03-16 Jean-Paul ChaputAdd experiment9/symbolic to test the multiple drivers...
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-14 Jean-Paul ChaputAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
2021-03-11 Luke Kenneth... try alternative pad/core connection
2021-03-09 Jean-Paul ChaputForgot the Makefile, stupid!
2021-03-09 Jean-Paul ChaputFirst working version of the Flexlib + P&R flow for...
2021-03-06 Luke Kenneth... add blackbox SPBlock 4k SRAM module
2021-03-05 Luke Kenneth... remove sram 4k wb bte/cti
2021-03-05 Luke Kenneth... litex expects wishbone "err" signals, added to sram 4k
2021-03-05 Luke Kenneth... rename sram_4k wishbone interface to actually like...
2021-03-05 Jean-Paul ChaputAdded support files for ls180+SRAM on TSMC 180nm.
2021-03-03 Luke Kenneth... add blackbox attribute manually to SPBlock_512W64B8W
2021-03-02 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-02 Jean-Paul ChaputFirst working power plane in experiment12.
2021-02-20 Luke Kenneth... add 4k sram build
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