soclayout.git
6 weeks agoAdjust katana settings for LS180/TSMC after Coriolis bugfix #f58212e. master
Jean-Paul Chaput [Tue, 19 Oct 2021 12:50:54 +0000 (14:50 +0200)]
Adjust katana settings for LS180/TSMC after Coriolis bugfix #f58212e.

8 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 6 Oct 2021 23:01:49 +0000 (01:01 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

8 weeks agoMore accurate abstract models for SRAM & PLL.
Jean-Paul Chaput [Wed, 6 Oct 2021 22:58:03 +0000 (00:58 +0200)]
More accurate abstract models for SRAM & PLL.

With Coriolis layer assignment correction and configuration tuning,
the P&R stage should now take less than one hour. It do not complete,
still. More adjustments are to be done.

2 months agouse main soclayout mksym.sh and symlink in experiments9
Luke Kenneth Casson Leighton [Sun, 19 Sep 2021 10:18:19 +0000 (10:18 +0000)]
use main soclayout mksym.sh and symlink in experiments9

2 months agoadd $USER to mksym.sh
Luke Kenneth Casson Leighton [Sun, 19 Sep 2021 10:16:49 +0000 (10:16 +0000)]
add $USER to mksym.sh

5 months agoEnable the heavy leaf load on the main clock. LS180_RC7_FINAL
Jean-Paul Chaput [Thu, 1 Jul 2021 12:03:34 +0000 (14:03 +0200)]
Enable the heavy leaf load on the main clock.

5 months agoAdd the filler setting in doDesign.py. LS180_RC6
Jean-Paul Chaput [Tue, 29 Jun 2021 13:26:12 +0000 (15:26 +0200)]
Add the filler setting in doDesign.py.

5 months agoReadjust the position of the SRAM after their blockage changes.
Jean-Paul Chaput [Sat, 26 Jun 2021 12:41:17 +0000 (14:41 +0200)]
Readjust the position of the SRAM after their blockage changes.

5 months agoKeep track of the latest debugged nets (antenna & DRC). LS180_RC3
Jean-Paul Chaput [Fri, 18 Jun 2021 17:22:04 +0000 (19:22 +0200)]
Keep track of the latest debugged nets (antenna & DRC).

5 months agoAdd logos in the bottom left corner and supress iovss terminal.
Jean-Paul Chaput [Fri, 18 Jun 2021 17:21:17 +0000 (19:21 +0200)]
Add logos in the bottom left corner and supress iovss terminal.

5 months agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 15 Jun 2021 23:18:16 +0000 (01:18 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

5 months agoadd wget of libresoc gds logo
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 12:38:01 +0000 (12:38 +0000)]
add wget of libresoc gds logo

5 months agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 15 Jun 2021 09:06:01 +0000 (11:06 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

5 months agoAdjust router track reservations for convergence.
Jean-Paul Chaput [Tue, 15 Jun 2021 09:05:25 +0000 (11:05 +0200)]
Adjust router track reservations for convergence.

5 months agoadd sorbonne logo to wget
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 16:18:28 +0000 (16:18 +0000)]
add sorbonne logo to wget

5 months agohmm set spacemargin back to 0.05
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 11:49:26 +0000 (11:49 +0000)]
hmm set spacemargin back to 0.05

5 months agoexperiment with same settings as benchs/6502
Luke Kenneth Casson Leighton [Sun, 13 Jun 2021 11:29:32 +0000 (11:29 +0000)]
experiment with same settings as benchs/6502

5 months agoattempt to put together a GDSII loader file. errr...
Luke Kenneth Casson Leighton [Sat, 12 Jun 2021 16:41:12 +0000 (16:41 +0000)]
attempt to put together a GDSII loader file. errr...

5 months agoadd fetch of GDS-II files
Luke Kenneth Casson Leighton [Sat, 12 Jun 2021 16:04:18 +0000 (16:04 +0000)]
add fetch of GDS-II files

5 months agoadd fetch of GDS-II files
Luke Kenneth Casson Leighton [Sat, 12 Jun 2021 16:02:55 +0000 (16:02 +0000)]
add fetch of GDS-II files

5 months agoreverse pingroup SDRAM address to get it closer to bottom right
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:29:51 +0000 (21:29 +0000)]
reverse pingroup SDRAM address to get it closer to bottom right

5 months agoredo pinmux, mirror image some pins
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:18:28 +0000 (21:18 +0000)]
redo pinmux, mirror image some pins

5 months agosubmodule update
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:12:03 +0000 (21:12 +0000)]
submodule update

5 months agoadd spimaster to peripheral system, all names changed. wtf?? sigh
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 15:51:10 +0000 (15:51 +0000)]
add spimaster to peripheral system, all names changed. wtf?? sigh

5 months agoupdated non_generated pinmap json file
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 12:01:41 +0000 (12:01 +0000)]
updated non_generated pinmap json file

5 months agoupdated non_generated pinmap json file
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:55:00 +0000 (11:55 +0000)]
updated non_generated pinmap json file

5 months agoupdate submodule
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:54:14 +0000 (11:54 +0000)]
update submodule

5 months agoargh, nsxlib does not have analog. have to cheat
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:50:02 +0000 (11:50 +0000)]
argh, nsxlib does not have analog.  have to cheat

5 months agosubmodule update
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:13:54 +0000 (11:13 +0000)]
submodule update

5 months agoRebame root clock signal from "core.por_clk" into "core.pll_clk".
Jean-Paul Chaput [Thu, 10 Jun 2021 09:17:20 +0000 (11:17 +0200)]
Rebame root clock signal from "core.por_clk" into "core.pll_clk".

5 months agosys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:29:25 +0000 (19:29 +0000)]
sys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
pinouts in json format

5 months agoadd litex pinpads JSON file to nongenerated
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:10:35 +0000 (19:10 +0000)]
add litex pinpads JSON file to nongenerated

5 months agodoh, should have reduced NC by 16
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:09:20 +0000 (19:09 +0000)]
doh, should have reduced NC by 16

5 months agopll24_i renamed to clk_24_i
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:43:34 +0000 (15:43 +0000)]
pll24_i renamed to clk_24_i

5 months agopllclk_o is renamed to pllclk_clk
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:41:47 +0000 (15:41 +0000)]
pllclk_o is renamed to pllclk_clk

5 months agouse sys_pllclk_from_pad not sys_clk_from_pad
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:23:34 +0000 (15:23 +0000)]
use sys_pllclk_from_pad not sys_clk_from_pad
rename module ls180

5 months agosys_clk renamed to sys_pllclk
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:20:36 +0000 (15:20 +0000)]
sys_clk renamed to sys_pllclk

5 months agoreorg of PLL, routed out into peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:19:50 +0000 (15:19 +0000)]
reorg of PLL, routed out into peripheral interconnect
then manually connected up
needed a rename of sys_clk to sys_pllclk to not conflict

5 months agoI/O pads reorganisation, 32 per side (except for NORTH).
Jean-Paul Chaput [Wed, 9 Jun 2021 09:50:37 +0000 (11:50 +0200)]
I/O pads reorganisation, 32 per side (except for NORTH).

5 months agoP&R tweaks for routing convergence.
Jean-Paul Chaput [Wed, 9 Jun 2021 09:14:33 +0000 (11:14 +0200)]
P&R tweaks for routing convergence.

5 months agoAdd a case in the build script to fit my environment (jpc).
Jean-Paul Chaput [Wed, 9 Jun 2021 09:13:27 +0000 (11:13 +0200)]
Add a case in the build script to fit my environment (jpc).

5 months agoRemove files that are now copied from other locations.
Jean-Paul Chaput [Wed, 9 Jun 2021 09:02:51 +0000 (11:02 +0200)]
Remove files that are now copied from other locations.

5 months agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 8 Jun 2021 11:15:46 +0000 (13:15 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

5 months agoAdpapt e9/TSMC doDesign to the new size of the SRAMs (jumpers).
Jean-Paul Chaput [Tue, 8 Jun 2021 11:14:32 +0000 (13:14 +0200)]
Adpapt e9/TSMC doDesign to the new size of the SRAMs (jumpers).

5 months agoargh, nsxlib cannot cope with 3 clocks!
Luke Kenneth Casson Leighton [Sun, 6 Jun 2021 14:01:16 +0000 (14:01 +0000)]
argh, nsxlib cannot cope with 3 clocks!

5 months agoadd vss/vdd as pins, gets the net into the VST
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:45:00 +0000 (17:45 +0000)]
add vss/vdd as pins, gets the net into the VST

5 months agoset power type in fake pll vdd/vss
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:38:04 +0000 (17:38 +0000)]
set power type in fake pll vdd/vss

5 months agowhoops, fake pll/mem need vss/vdd
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:34:32 +0000 (17:34 +0000)]
whoops, fake pll/mem need vss/vdd

5 months agowhoops naming pads different from nets is important
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:09:01 +0000 (17:09 +0000)]
whoops naming pads different from nets is important

5 months agosigh trying to find the right clock line
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:08:44 +0000 (17:08 +0000)]
sigh trying to find the right clock line

5 months agomore comments
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:53:26 +0000 (12:53 +0000)]
more comments

5 months agocomment about por_clk
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:20:00 +0000 (12:20 +0000)]
comment about por_clk

5 months agocorrect clock name for H-Tree in ls180
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:19:02 +0000 (12:19 +0000)]
correct clock name for H-Tree in ls180
use por_clk not core.por_clk
this is the output from the PLL

5 months agosort out clock names in experiments10_verilog
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:30:42 +0000 (11:30 +0000)]
sort out clock names in experiments10_verilog

5 months agoadd coresync_clk to list of HTree
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:09:54 +0000 (11:09 +0000)]
add coresync_clk to list of HTree

5 months agoadd dummy pll to experiments10_verilog
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:04:27 +0000 (11:04 +0000)]
add dummy pll to experiments10_verilog

5 months agoset various clocks to use H-Tree
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 10:23:39 +0000 (10:23 +0000)]
set various clocks to use H-Tree

5 months agoadd dummy (fake) PLL to experiments10_verilog for testing
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 10:15:23 +0000 (10:15 +0000)]
add dummy (fake) PLL to experiments10_verilog for testing

5 months agoUpdated experiments12 for the latest Coriolis.
Jean-Paul Chaput [Fri, 4 Jun 2021 19:12:29 +0000 (21:12 +0200)]
Updated experiments12 for the latest Coriolis.

* To serve as a test bench for the reamining diode insertion
  problems.

5 months agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Fri, 4 Jun 2021 16:15:38 +0000 (18:15 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

5 months agoUpdated configuration suited for experiment9/tsmc_c018.
Jean-Paul Chaput [Fri, 4 Jun 2021 16:09:32 +0000 (18:09 +0200)]
Updated configuration suited for experiment9/tsmc_c018.

* Typo in coriolis2/settings.py (extra 'e' in blackboxNames parameter).
* Disable blackboxes generation in TSMC, they are directly supplied by
  the FlexLib DK.
* Strip the Makefile from unusable targets in real mode.
* Update doDesign.py for the latest Coriolis (H-Tree).

6 months agoadd 4ksram recon script in tsmc_c018 as well
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 22:29:03 +0000 (22:29 +0000)]
add 4ksram recon script in tsmc_c018 as well

6 months agoadd build_full_4ksram_recon.sh to copy over Staf re-connected PLL
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 21:56:54 +0000 (21:56 +0000)]
add build_full_4ksram_recon.sh to copy over Staf re-connected PLL

6 months agorename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 21:52:45 +0000 (21:52 +0000)]
rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
this restores ls180 module to minimise changes

6 months agoReroute clk so PLL output clock is used as sys_clk.
Staf Verhaegen [Thu, 3 Jun 2021 19:59:56 +0000 (21:59 +0200)]
Reroute clk so PLL output clock is used as sys_clk.

6 months agoDuplicate file before patching for clock rerouting.
Staf Verhaegen [Thu, 3 Jun 2021 19:55:55 +0000 (21:55 +0200)]
Duplicate file before patching for clock rerouting.

6 months agorename ref in fake-pll to ref_v
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:14:33 +0000 (15:14 +0000)]
rename ref in fake-pll to ref_v

6 months agoupdate libresoc.v to use sys_clk for main core
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:07:27 +0000 (15:07 +0000)]
update libresoc.v to use sys_clk for main core

6 months agochange ref to ref_v in PLL (keyword)
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:07:03 +0000 (15:07 +0000)]
change ref to ref_v in PLL (keyword)

6 months agoset other nets to input in fake 4k SRAM cell
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:59:36 +0000 (13:59 +0000)]
set other nets to input in fake 4k SRAM cell

6 months agoadd TODO into tsmc_c018 coriolis2 settings.py
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:53:17 +0000 (13:53 +0000)]
add TODO into tsmc_c018 coriolis2 settings.py

6 months agoupdate libresoc.v
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:52:56 +0000 (13:52 +0000)]
update libresoc.v

6 months agoset fake-mem LibreSOCMem output q as a Net Output
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:52:36 +0000 (13:52 +0000)]
set fake-mem LibreSOCMem output q as a Net Output

6 months agoset fake PLL Master Cell directions explicitly
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:50:12 +0000 (13:50 +0000)]
set fake PLL Master Cell directions explicitly

6 months agoclk_sel_i in TestIssuer was one bit not 2
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:13:00 +0000 (15:13 +0000)]
clk_sel_i in TestIssuer was one bit not 2

6 months agoremove sram4k wb err (unused anyway)
Luke Kenneth Casson Leighton [Wed, 26 May 2021 14:07:13 +0000 (14:07 +0000)]
remove sram4k wb err (unused anyway)

6 months agoappears to be missing libresoc from NETLISTS in Makefile
Luke Kenneth Casson Leighton [Wed, 26 May 2021 13:46:01 +0000 (13:46 +0000)]
appears to be missing libresoc from NETLISTS in Makefile

6 months agoattempt better grid alignment for fake cells
Luke Kenneth Casson Leighton [Tue, 25 May 2021 15:01:46 +0000 (15:01 +0000)]
attempt better grid alignment for fake cells

6 months agochange cell sizes to grid layout (?)
Luke Kenneth Casson Leighton [Tue, 25 May 2021 12:01:44 +0000 (12:01 +0000)]
change cell sizes to grid layout (?)

6 months agoincrease not-connected pads by one
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:45:59 +0000 (11:45 +0000)]
increase not-connected pads by one

6 months agoadd fake pll symlink
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:39:00 +0000 (11:39 +0000)]
add fake pll symlink

6 months agorename pll out signal to out_v in "fake" pll cell
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:37:47 +0000 (11:37 +0000)]
rename pll out signal to out_v in "fake" pll cell

6 months agorename PLL out to out_v in test_issuer
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:32:58 +0000 (11:32 +0000)]
rename PLL out to out_v in test_issuer

6 months agorename pll blackbox out to out_v
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:30:07 +0000 (11:30 +0000)]
rename pll blackbox out to out_v

6 months agodisappearing signal from pll, attempt to get it back
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:45:12 +0000 (17:45 +0000)]
disappearing signal from pll, attempt to get it back

6 months agoremove "*" net from fake-pll cell, it ends up in the vst file
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:35:37 +0000 (17:35 +0000)]
remove "*" net from fake-pll cell, it ends up in the vst file

6 months agoround to 0.135 cell grid?
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:27:40 +0000 (17:27 +0000)]
round to 0.135 cell grid?

6 months agorename cell to "real_pll" to avoid conflict with cell also named "pll"
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:25:35 +0000 (17:25 +0000)]
rename cell to "real_pll" to avoid conflict with cell also named "pll"

6 months agoadd dummy/fake/ghost PLL blackbox cell
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:00:20 +0000 (17:00 +0000)]
add dummy/fake/ghost PLL blackbox cell
to nsxlib experiments9.  based on the dummy/fake/ghost/symbolic
LibreSOCMem previously created
the cell is completely empty, the only important thing is the *existence*
of the cell and its I/O connections

6 months agorename PLL pad names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 12:06:24 +0000 (12:06 +0000)]
rename PLL pad names

6 months agocorrect PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:59:32 +0000 (11:59 +0000)]
correct PLL names

6 months agore-add 4k sram
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:44:49 +0000 (11:44 +0000)]
re-add 4k sram

6 months agoannoying rename of pll analog pin
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:36:16 +0000 (11:36 +0000)]
annoying rename of pll analog pin

6 months agomanually rename ls180sram4k module to ls180
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:15:36 +0000 (11:15 +0000)]
manually rename ls180sram4k module to ls180

6 months agosubmodule update
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:03:08 +0000 (11:03 +0000)]
submodule update

6 months agoupdate PLL to use submodule Instance
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:02:59 +0000 (11:02 +0000)]
update PLL to use submodule Instance

7 months agodo an SRAM search by looking for matching along the path
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:47:47 +0000 (17:47 +0000)]
do an SRAM search by looking for matching along the path
goodbye explicit yosys ids!

7 months ago4k sram build
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:17:54 +0000 (17:17 +0000)]
4k sram build

7 months agouse "make view" not "make vst"
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:05:18 +0000 (17:05 +0000)]
use "make view" not "make vst"

7 months agoadd fake LibreSOCMem library to freepdk_c4m45
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 12:40:09 +0000 (12:40 +0000)]
add fake LibreSOCMem library to freepdk_c4m45