soclayout.git
12 hours agoargh, found the blackbox problem: yosys is "doing the right thing" and master
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 23:30:08 +0000 (23:30 +0000)]
argh, found the blackbox problem: yosys is "doing the right thing" and
identifying spblock as a cell (there are 4 used, therefore it gets identified
as a cell).
also because the blackbox is empty, yosys is optimising it out.
therefore, solution: put something (q = d) into the blackbox, and make
4 each with different names.
yes, it is awful, but it works

13 hours agotry renaming spblock without the underscore
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:37:50 +0000 (22:37 +0000)]
try renaming spblock without the underscore

13 hours agotry changing layout of blackbox spblock_512w64b8w
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:34:07 +0000 (22:34 +0000)]
try changing layout of blackbox spblock_512w64b8w

15 hours agoexperimenting with blackboxes
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:51:26 +0000 (20:51 +0000)]
experimenting with blackboxes

15 hours agorename spblock_512w64b8w, and vco_test_ana for pll
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:43:31 +0000 (20:43 +0000)]
rename spblock_512w64b8w, and vco_test_ana for pll

15 hours agorename blackboxes to lowercase, spblock_512w64b8w, pll
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:20:50 +0000 (20:20 +0000)]
rename blackboxes to lowercase, spblock_512w64b8w, pll

15 hours agoupdate ls180 sram4k
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:19:48 +0000 (20:19 +0000)]
update ls180 sram4k

22 hours agoadd yosys BLACKBOX SPBlock_512W64B8W - still blif2vst.py complains
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:51:46 +0000 (13:51 +0000)]
add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst.py complains

22 hours agomust use VST_FLAGS uniquify uppercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:39:42 +0000 (13:39 +0000)]
must use VST_FLAGS uniquify uppercase

22 hours agosort out adding SPBlock_512 SRAM verilog to ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:34:22 +0000 (13:34 +0000)]
sort out adding SPBlock_512 SRAM verilog to ls180

25 hours agoupdate tsmc_018 4k build script
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:55:53 +0000 (10:55 +0000)]
update tsmc_018 4k build script

25 hours agouse correct arguments to litex build to create 4k srams sigh
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:53:42 +0000 (10:53 +0000)]
use correct arguments to litex build to create 4k srams sigh

25 hours agorename ls180sram4k to ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:30:01 +0000 (10:30 +0000)]
rename ls180sram4k to ls180

25 hours agoadd full core variant including 4k sram of ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:28:19 +0000 (10:28 +0000)]
add full core variant including 4k sram of ls180

25 hours agoupdate libresoc.v, c4m-jtag fsm was renamed
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:27:10 +0000 (10:27 +0000)]
update libresoc.v, c4m-jtag fsm was renamed

25 hours agoupdate libresoc.v, c4m-jtag fsm was renamed
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:26:57 +0000 (10:26 +0000)]
update libresoc.v, c4m-jtag fsm was renamed

4 days agoadd an SRAM and wishbone to add test (makes it bigger)
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:29:22 +0000 (19:29 +0000)]
add an SRAM and wishbone to add test (makes it bigger)
also enable HFNS.  this to test cocotb-ghdl

5 days agoconnect up boundary scan to inputs/outputs
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 10:04:31 +0000 (10:04 +0000)]
connect up boundary scan to inputs/outputs

5 days agosubmodule update
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 18:52:49 +0000 (18:52 +0000)]
submodule update

5 days agouse METAL10 for topRoutingLayer
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 18:52:42 +0000 (18:52 +0000)]
use METAL10 for topRoutingLayer

5 days agowhoops forgot settings.py
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 13:50:45 +0000 (13:50 +0000)]
whoops forgot settings.py

6 days agosubmodule update
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 22:34:52 +0000 (22:34 +0000)]
submodule update

6 days agoset routingGauge manually
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 22:34:37 +0000 (22:34 +0000)]
set routingGauge manually

6 days agoenable HFNS in adder
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 18:27:51 +0000 (18:27 +0000)]
enable HFNS in adder

6 days agoinclude (but do not use) FreePDK45 in experiments10
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 18:00:29 +0000 (18:00 +0000)]
include (but do not use) FreePDK45 in experiments10

6 days agodifferent FreePDK45 experiments10 chip size
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:58:07 +0000 (16:58 +0000)]
different FreePDK45 experiments10 chip size

6 days agoexperimentation to get experiment10_verilog work with FreePDK
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:44:51 +0000 (16:44 +0000)]
experimentation to get experiment10_verilog work with FreePDK

6 days agoadd FreePDK45 experiments10_verilog doDesign.py
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:33:21 +0000 (16:33 +0000)]
add FreePDK45 experiments10_verilog doDesign.py

6 days agoadd FreePDK45 variant of experiments10_verilog
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:15:38 +0000 (16:15 +0000)]
add FreePDK45 variant of experiments10_verilog

6 days agoupdate PLL signal output names
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 14:06:53 +0000 (14:06 +0000)]
update PLL signal output names

7 days agodoDesign.py: Disable SRAM placement
Staf Verhaegen [Mon, 12 Apr 2021 11:24:54 +0000 (13:24 +0200)]
doDesign.py: Disable SRAM placement

7 days agoReduce core size.
Staf Verhaegen [Mon, 12 Apr 2021 11:24:28 +0000 (13:24 +0200)]
Reduce core size.

Using 45nm cells makes the design Pad limited.

7 days agorename sys_clk in adder test experiments10_verilog (success compile)
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:56:53 +0000 (10:56 +0000)]
rename sys_clk in adder test experiments10_verilog (success compile)

7 days agorename JTAG port in adder test experiments10_verilog (success compile)
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:54:57 +0000 (10:54 +0000)]
rename JTAG port in adder test experiments10_verilog (success compile)

7 days agoback to "working" verilog add
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:48:42 +0000 (10:48 +0000)]
back to "working" verilog add

7 days agoanother attempt to get 100% completed route
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:06:44 +0000 (10:06 +0000)]
another attempt to get 100% completed route

7 days agoRight branch of c4m-pdk-freedpk45.
Staf Verhaegen [Mon, 12 Apr 2021 08:02:47 +0000 (10:02 +0200)]
Right branch of c4m-pdk-freedpk45.

7 days agogood grief, increasing ls180 core size to 70,000, 100% route attempt
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 21:49:46 +0000 (21:49 +0000)]
good grief, increasing ls180 core size to 70,000, 100% route attempt

7 days agoincrease core size to see if global routing can be achieved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 20:09:38 +0000 (20:09 +0000)]
increase core size to see if global routing can be achieved

7 days agowhitespace cleanup
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 20:03:15 +0000 (20:03 +0000)]
whitespace cleanup

7 days agouse auto-generated pinmux ioPadsSpecs
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:38:19 +0000 (17:38 +0000)]
use auto-generated pinmux ioPadsSpecs

7 days agosubmodule conflict (update again)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:23:18 +0000 (17:23 +0000)]
submodule conflict (update again)

7 days agouse verilog version of ls180 in FreePDK_c4m45
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:21:32 +0000 (17:21 +0000)]
use verilog version of ls180 in FreePDK_c4m45

7 days agoUpdate c4m-pdk-freepdk45 submodule.
Staf Verhaegen [Sun, 11 Apr 2021 16:14:07 +0000 (18:14 +0200)]
Update c4m-pdk-freepdk45 submodule.

7 days agocrank up the numbers (again)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 16:07:19 +0000 (16:07 +0000)]
crank up the numbers (again)

7 days agoWip of P&R of ls180 with C4M FreePDK45.
Staf Verhaegen [Sun, 11 Apr 2021 15:38:45 +0000 (17:38 +0200)]
Wip of P&R of ls180 with C4M FreePDK45.

build_full.sh can run til after `make vst`,
`make lvx` fails.

7 days agoexperiments9: Ignore pinmux generated files.
Staf Verhaegen [Sun, 11 Apr 2021 15:14:13 +0000 (17:14 +0200)]
experiments9: Ignore pinmux generated files.

7 days agomksym.sh: Check exitence of alliance-check-toolkit
Staf Verhaegen [Sun, 11 Apr 2021 15:13:47 +0000 (17:13 +0200)]
mksym.sh: Check exitence of alliance-check-toolkit

7 days agoSubmodule for C4M FreePDK45 PDK release files.
Staf Verhaegen [Sun, 11 Apr 2021 15:03:50 +0000 (17:03 +0200)]
Submodule for C4M FreePDK45 PDK release files.

Use released-libresoc branch.

8 days agocrank up the numbers to see if routing completion can be achieved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 11:32:15 +0000 (11:32 +0000)]
crank up the numbers to see if routing completion can be achieved

8 days agoincrease katana tracks reserved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 10:43:20 +0000 (10:43 +0000)]
increase katana tracks reserved

8 days agouse verilog for ls180 instead of ilang
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 19:57:45 +0000 (19:57 +0000)]
use verilog for ls180 instead of ilang

9 days agomake VST names unique, for GHDL to cope
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 11:23:38 +0000 (11:23 +0000)]
make VST names unique, for GHDL to cope

9 days agosigh, broken experiment10_verilog
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 16:16:15 +0000 (16:16 +0000)]
sigh, broken experiment10_verilog

9 days agowhitespace
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:58:58 +0000 (15:58 +0000)]
whitespace

9 days agowhitespace cleanup
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:38 +0000 (15:55 +0000)]
whitespace cleanup

9 days agopad name starts with p_
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:29 +0000 (15:55 +0000)]
pad name starts with p_

9 days agorename design of experiments10 to match ls180 chip pads
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 12:05:11 +0000 (12:05 +0000)]
rename design of experiments10 to match ls180 chip pads

2 weeks agoexperiment with nmigen verilog generation
Luke Kenneth Casson Leighton [Fri, 2 Apr 2021 12:37:38 +0000 (12:37 +0000)]
experiment with nmigen verilog generation

2 weeks agoupdate / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:07 +0000 (22:41 +0000)]
update / refresh full core DFF

2 weeks agoupdate / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:29:06 +0000 (22:29 +0000)]
update / refresh full core DFF

2 weeks agorun doChipFloorplan in experiments10
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:35:18 +0000 (16:35 +0000)]
run doChipFloorplan in experiments10

2 weeks agoincrease experiment10 JTAG tap width to 4
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:30:45 +0000 (16:30 +0000)]
increase experiment10 JTAG tap width to 4

2 weeks agoupdate submodule
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:04:37 +0000 (16:04 +0000)]
update submodule

2 weeks agoupdate 4k SRAM ls180.il
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:55:43 +0000 (10:55 +0000)]
update 4k SRAM ls180.il

2 weeks agoadd yosys version number
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 09:45:45 +0000 (09:45 +0000)]
add yosys version number

2 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Mon, 29 Mar 2021 18:54:32 +0000 (20:54 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

2 weeks agoAdd a placeholder for the PLL in the doDesign.py for ls180.
Jean-Paul Chaput [Mon, 29 Mar 2021 18:53:40 +0000 (20:53 +0200)]
Add a placeholder for the PLL in the doDesign.py for ls180.

2 weeks agoRevert "enable high fanout in ls180 experiment9 doDesign.py"
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:30:57 +0000 (18:30 +0000)]
Revert "enable high fanout in ls180 experiment9 doDesign.py"

This reverts commit 309301fd58ed12bec149292a40bf1a3c1507d36d.

2 weeks agoenable high fanout in ls180 experiment9 doDesign.py
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:19:23 +0000 (17:19 +0000)]
enable high fanout in ls180 experiment9 doDesign.py

3 weeks agoaaagh found bug in litex setup, 64 bit WB bus was truncated
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 07:18:29 +0000 (07:18 +0000)]
aaagh found bug in litex setup, 64 bit WB bus was truncated

3 weeks agoreduce SPR regfile size considerably
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 17:07:22 +0000 (17:07 +0000)]
reduce SPR regfile size considerably

3 weeks agoreduce INT and FAST regfile sizes by sharing ports
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 14:41:40 +0000 (14:41 +0000)]
reduce INT and FAST regfile sizes by sharing ports

3 weeks agoadd missing floorplan function call
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:47 +0000 (20:27 +0000)]
add missing floorplan function call

3 weeks agohooray, corrected pinouts
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:34 +0000 (20:27 +0000)]
hooray, corrected pinouts

3 weeks agoreally weird error "unsupported direction for eint" which makes no sense
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 17:38:26 +0000 (17:38 +0000)]
really weird error "unsupported direction for eint" which makes no sense

3 weeks agoUodated doDesign for the latest ls180 (sram variant).
Jean-Paul Chaput [Tue, 23 Mar 2021 19:25:33 +0000 (20:25 +0100)]
Uodated doDesign for the latest ls180 (sram variant).

3 weeks agoincrease DFF RAM size slightly
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:20:45 +0000 (17:20 +0000)]
increase DFF RAM size slightly

3 weeks agoadd very small DFF srams variant
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:15:00 +0000 (17:15 +0000)]
add very small DFF srams variant

3 weeks agocreate small dff with 4x 4k SRAMs
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:08:46 +0000 (17:08 +0000)]
create small dff with 4x 4k SRAMs

3 weeks agols180.il update
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:57:00 +0000 (12:57 +0000)]
ls180.il update

3 weeks agoargh pinmux generating bi-directional SDR DM when it should be output
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:43:36 +0000 (12:43 +0000)]
argh pinmux generating bi-directional SDR DM when it should be output

4 weeks agoupdate ls180.il
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:51:21 +0000 (12:51 +0000)]
update ls180.il

4 weeks agoupdate submodule
Luke Kenneth Casson Leighton [Tue, 16 Mar 2021 17:40:41 +0000 (17:40 +0000)]
update submodule

4 weeks agoupdate ls180.il 4ksram with correct sdram connections
Luke Kenneth Casson Leighton [Tue, 16 Mar 2021 17:39:59 +0000 (17:39 +0000)]
update ls180.il 4ksram with correct sdram connections

4 weeks agoAdd experiment9/symbolic to test the multiple drivers problem.
Jean-Paul Chaput [Tue, 16 Mar 2021 11:41:34 +0000 (12:41 +0100)]
Add experiment9/symbolic to test the multiple drivers problem.

5 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Sun, 14 Mar 2021 16:04:58 +0000 (17:04 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

5 weeks agoAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
Jean-Paul Chaput [Sun, 14 Mar 2021 15:37:19 +0000 (16:37 +0100)]
Adjusted doDesign.py scripts to use Chip.doChipFloorplan().

5 weeks agotry alternative pad/core connection
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 11:31:22 +0000 (11:31 +0000)]
try alternative pad/core connection

5 weeks agoForgot the Makefile, stupid!
Jean-Paul Chaput [Tue, 9 Mar 2021 10:24:50 +0000 (11:24 +0100)]
Forgot the Makefile, stupid!

5 weeks agoFirst working version of the Flexlib + P&R flow for the ls180+SRAM.
Jean-Paul Chaput [Tue, 9 Mar 2021 10:01:04 +0000 (11:01 +0100)]
First working version of the Flexlib + P&R flow for the ls180+SRAM.

Note: It is working in the sense that the flow complete, but is stills
      contains various errors that needs fixing.
        We discoupled from pinmux as core2chip have problems associating
      the pad instances names with the relevant core signals.
        We guessed a pad placement from pinmux, but it seems a bit odd
      to me...

6 weeks agoadd blackbox SPBlock 4k SRAM module
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:30:42 +0000 (00:30 +0000)]
add blackbox SPBlock 4k SRAM module

6 weeks agoremove sram 4k wb bte/cti
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 23:10:35 +0000 (23:10 +0000)]
remove sram 4k wb bte/cti

6 weeks agolitex expects wishbone "err" signals, added to sram 4k
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:09:25 +0000 (21:09 +0000)]
litex expects wishbone "err" signals, added to sram 4k

6 weeks agorename sram_4k wishbone interface to actually like include "wishbone"?
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:19:18 +0000 (19:19 +0000)]
rename sram_4k wishbone interface to actually like include "wishbone"?

6 weeks agoAdded support files for ls180+SRAM on TSMC 180nm.
Jean-Paul Chaput [Fri, 5 Mar 2021 10:14:02 +0000 (11:14 +0100)]
Added support files for ls180+SRAM on TSMC 180nm.

6 weeks agoadd blackbox attribute manually to SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 22:03:40 +0000 (22:03 +0000)]
add blackbox attribute manually to SPBlock_512W64B8W

6 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 2 Mar 2021 12:02:14 +0000 (13:02 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

6 weeks agoFirst working power plane in experiment12.
Jean-Paul Chaput [Tue, 2 Mar 2021 11:23:36 +0000 (12:23 +0100)]
First working power plane in experiment12.

8 weeks agoadd 4k sram build
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:25:29 +0000 (15:25 +0000)]
add 4k sram build