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[soc.git]
/
src
/
soc
/
clock
/
2021-06-03
Luke Kenneth Casso...
rename ref to ref_v in PLL due to ref being a verilog...
tree
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commitdiff
2021-05-27
Luke Kenneth Casso...
adjust PLL connections looking for coriolis2 issue
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commitdiff
2021-05-26
Luke Kenneth Casso...
rename PLL signals
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commitdiff
2021-05-24
Luke Kenneth Casso...
change name of submodule to real_pll
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commitdiff
2021-05-24
Luke Kenneth Casso...
match up PLL names
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commitdiff
2021-05-22
Luke Kenneth Casso...
update PLL to use Instance
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commitdiff
2021-04-18
Luke Kenneth Casso...
create signal on test_issuer which gives PLL clk_sel_i...
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commitdiff
2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
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commitdiff
2020-11-13
Luke Kenneth Casso...
reduce clkcsel ls180 width (2 pins), rename pll_18...
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commitdiff
2020-11-13
Luke Kenneth Casso...
rename and add pll lock signal to ls180
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commitdiff
2020-11-10
Luke Kenneth Casso...
remove ClockSelect module, use DummyPLL
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commitdiff
2020-11-10
Luke Kenneth Casso...
add separate DummyPLL module, according to API discussed at
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commitdiff
2020-10-07
Luke Kenneth Casso...
reorder / reorganise reset signals slightly
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commitdiff
2020-10-06
Luke Kenneth Casso...
add ports function to DummyPLL
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commitdiff
2020-10-01
Luke Kenneth Casso...
create dummy PLL block, connect up to core and clock...
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commitdiff
2020-09-27
Luke Kenneth Casso...
rename sys_clk_i to clk_24_i
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commitdiff
2020-09-27
Luke Kenneth Casso...
add clock selection mechanism
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commitdiff