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nope - need it to be zero if not identified as svp64
[soc.git]
/
src
/
soc
/
consts.py
2020-10-06
Luke Kenneth Casso...
add SRR1 setting for LDST memory exception trap
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2020-10-06
Luke Kenneth Casso...
add LDSTException decode/handling in PowerDecoder2
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2020-09-06
Luke Kenneth Casso...
add DEC SPR to CoreState and PowerDecoder, activate...
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2020-09-04
Luke Kenneth Casso...
adding option to include XICS external interrupts.
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2020-07-24
Samuel A. Falvo II
WIP: addressing code review, restoring proofs, etc.
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2020-07-24
Luke Kenneth Casso...
add better comments on field_slice
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2020-07-24
Luke Kenneth Casso...
returned field_slice to original, and added comments
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2020-07-24
Luke Kenneth Casso...
made it clear what is meant by the slice numbering...
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2020-07-24
Samuel A. Falvo II
Refactorin of common code
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2020-07-22
Luke Kenneth Casso...
sigh, auto-create some little/big-endian classes for...
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2020-07-22
Luke Kenneth Casso...
add TT.size and use it in PowerDecoder and trap input...
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2020-07-22
Luke Kenneth Casso...
note that traptype MUST increase in bitwidth correspond...
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2020-07-22
Samuel A. Falvo II
Complete FV properties for OP_TRAP instructions.
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2020-07-21
Samuel A. Falvo II
Refine properties to comply with spec
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2020-07-21
Samuel A. Falvo II
Merge in recent updates to TRAP FV properties.
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2020-07-15
Luke Kenneth Casso...
move traptype to soc.consts
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
cater for illegal instruction (generates a trap)
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2020-07-04
Luke Kenneth Casso...
use new consts module
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