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make argv handling more flexible
[soc.git]
/
src
/
soc
/
consts.py
2021-04-23
Luke Kenneth Casso...
removing more as moved over to openpower-isa
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2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
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2021-03-20
Luke Kenneth Casso...
sort out predicate zeroing in ISACaller
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2021-03-19
Luke Kenneth Casso...
decode predicate src/dest zeroing in SVP64RMModeDecode
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2021-03-17
Luke Kenneth Casso...
add SVP64 INT-style predication to ISACaller
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2021-03-16
Cesar Strauss
Add subfield and bit definitions for the SVP64 RM mode...
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2021-02-28
Luke Kenneth Casso...
start on SVP64 RM Mode decoder
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2021-02-21
Cesar Strauss
The field selection function was moved to nmutil.util
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2021-02-21
Luke Kenneth Casso...
create SVP64CROffs consts for when SVP64 Vector-of...
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2021-02-20
Cesar Strauss
Actually forward the field width to field_slice()
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2021-02-20
Cesar Strauss
Replace more hardcoded constants with symbolic field...
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2021-02-17
Luke Kenneth Casso...
declare blank classes SPEC and EXTRA2 to add MSB-to...
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2021-02-17
Cesar Strauss
Use subfield bit selection to extract the RM SVP64...
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2021-02-17
Cesar Strauss
Replace MSB-i by symbolic subfield indices and selectors
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2021-02-17
Cesar Strauss
Add a function to select bits from a signal into a...
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2021-02-16
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-02-16
Luke Kenneth Casso...
adapt botchify so it can be used for 31- or 15- etc...
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2020-10-06
Luke Kenneth Casso...
add SRR1 setting for LDST memory exception trap
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2020-10-06
Luke Kenneth Casso...
add LDSTException decode/handling in PowerDecoder2
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2020-09-06
Luke Kenneth Casso...
add DEC SPR to CoreState and PowerDecoder, activate...
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2020-09-04
Luke Kenneth Casso...
adding option to include XICS external interrupts.
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2020-07-24
Samuel A. Falvo II
WIP: addressing code review, restoring proofs, etc.
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2020-07-24
Luke Kenneth Casso...
add better comments on field_slice
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2020-07-24
Luke Kenneth Casso...
returned field_slice to original, and added comments
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2020-07-24
Luke Kenneth Casso...
made it clear what is meant by the slice numbering...
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2020-07-24
Samuel A. Falvo II
Refactorin of common code
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2020-07-22
Luke Kenneth Casso...
sigh, auto-create some little/big-endian classes for...
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2020-07-22
Luke Kenneth Casso...
add TT.size and use it in PowerDecoder and trap input...
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2020-07-22
Luke Kenneth Casso...
note that traptype MUST increase in bitwidth correspond...
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2020-07-22
Samuel A. Falvo II
Complete FV properties for OP_TRAP instructions.
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2020-07-21
Samuel A. Falvo II
Refine properties to comply with spec
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2020-07-21
Samuel A. Falvo II
Merge in recent updates to TRAP FV properties.
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2020-07-15
Luke Kenneth Casso...
move traptype to soc.consts
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
cater for illegal instruction (generates a trap)
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2020-07-04
Luke Kenneth Casso...
use new consts module
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