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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / experiment /
2023-11-05 Cesar StraussAllow the formal engine to perform a same-cycle result... master tree | commitdiff
2023-09-11 Jacob Lifshaymark src/soc/experiment/test/test_compldst_multi.py... tree | commitdiff
2023-01-01 Cesar StraussHandle newer nMigen adding a "bench" hierarchy root... tree | commitdiff
2022-11-15 Cesar StraussKeep the valid signal from the formal engine ALU stable... tree | commitdiff
2022-10-28 Cesar StraussCheck that exactly one ALU write is made, per instruction tree | commitdiff
2022-10-28 Cesar StraussCheck cover and bmc in separate sub-tests tree | commitdiff
2022-10-26 Cesar StraussReset req_l latch on system reset tree | commitdiff
2022-10-26 Cesar StraussReset src_l latch on issue_i tree | commitdiff
2022-10-24 Luke Kenneth Casso... only NLnet sponsor tree | commitdiff
2022-10-16 Cesar StraussMove test to expose bug in MultiCompUnit tree | commitdiff
2022-10-12 Cesar StraussCheck invariant for instruction operands tree | commitdiff
2022-10-12 Cesar StraussIf the ALU is idle, do not assert valid tree | commitdiff
2022-10-09 Cesar StraussCount zero_a and imm_data.ok as masked read transactions tree | commitdiff
2022-10-09 Cesar StraussDon't issue while busy tree | commitdiff
2022-10-08 Cesar StraussAdd count of masked reads tree | commitdiff
2022-10-08 Cesar StraussAdd ALU read transaction counter tree | commitdiff
2022-10-08 Cesar StraussAdd ALU write transaction counter tree | commitdiff
2022-10-08 Cesar StraussAdd write transaction counter tree | commitdiff
2022-10-05 Cesar StraussFix duplicate line (copy & paste error) tree | commitdiff
2022-10-01 Cesar StraussAdd counter for operand reads tree | commitdiff
2022-10-01 Cesar StraussAvoid toggling go_i when rel_o is low tree | commitdiff
2022-10-01 Cesar StraussLeave shadow / die proof for last tree | commitdiff
2022-10-01 Cesar StraussStart of formal proof of MultiCompUnit tree | commitdiff
2022-07-06 Luke Kenneth Casso... add fabric compatibility mode tree | commitdiff
2022-06-26 Luke Kenneth Casso... reduce icache/dcache TLB sizes tree | commitdiff
2022-04-29 Luke Kenneth Casso... add option to set small cache sizes in tree | commitdiff
2022-04-16 Luke Kenneth Casso... reduce dcache/icache number of ways, to fit into ECP5... tree | commitdiff
2022-03-26 Luke Kenneth Casso... rename PLRU modules to avoid conflict in microwatt tree | commitdiff
2022-03-18 Luke Kenneth Casso... turn CompALU/CompLDST latches synchronous tree | commitdiff
2022-03-12 Luke Kenneth Casso... Revert "read last row from r.wb.adr not r.req_adr in... tree | commitdiff
2022-03-12 Luke Kenneth Casso... read last row from r.wb.adr not r.req_adr in icache tree | commitdiff
2022-03-08 Luke Kenneth Casso... remove stbs_done in icache.py tree | commitdiff
2022-03-08 Luke Kenneth Casso... remove ld_stbs_done from dcache: not needed tree | commitdiff
2022-02-27 Luke Kenneth Casso... for lulz make I-Cache possible to set to 32-bit (XLEN=32) tree | commitdiff
2022-02-23 Luke Kenneth Casso... forgot to pass cix (cache-inhibited) through to LD... tree | commitdiff
2022-02-20 Luke Kenneth Casso... add syn_ramstyle "block_ram" attributes and reduce... tree | commitdiff
2022-02-18 Luke Kenneth Casso... use block_ram attribute for FPGA synthesis tree | commitdiff
2022-02-18 Luke Kenneth Casso... reduce number of d-cache lines in microwatt fpga mode tree | commitdiff
2022-02-18 Luke Kenneth Casso... couple of adjustments to reduce gate count in i/d-cache tree | commitdiff
2022-02-18 Luke Kenneth Casso... reduce TLB set size from 64 to 16 to get FPGA resource... tree | commitdiff
2022-02-18 Luke Kenneth Casso... drastically reduce I-Cache size in microwatt-compat... tree | commitdiff
2022-02-18 Luke Kenneth Casso... parameterise I-Cache similar to D-Cache. lots of "self." tree | commitdiff
2022-02-17 Luke Kenneth Casso... add opencores SDRAM verilog wrapper tree | commitdiff
2022-02-16 Luke Kenneth Casso... oof. big update to DCache to accept config parameters tree | commitdiff
2022-01-31 Luke Kenneth Casso... fix bug in itlb_valid SRLatch set/reset, a bit weird... tree | commitdiff
2022-01-31 Luke Kenneth Casso... whoops tlb_valids in ICache is a combinatorial-get/set tree | commitdiff
2022-01-31 Luke Kenneth Casso... convert TLBValidArray in ICache to SRLatch tree | commitdiff
2022-01-31 Luke Kenneth Casso... use an SRLatch for cache_valids, at least it reduces... tree | commitdiff
2022-01-31 Luke Kenneth Casso... use Memory for cache tags in dcache tree | commitdiff
2022-01-31 Luke Kenneth Casso... use Memory for cache_tags in icache tree | commitdiff
2022-01-31 Luke Kenneth Casso... remove combinatorial loop from MultiCompUnit tree | commitdiff
2022-01-30 Luke Kenneth Casso... break out cache_tags and cache_valids (again) this... tree | commitdiff
2022-01-30 Luke Kenneth Casso... remove CacheTagArray in icache.py tree | commitdiff
2022-01-30 Luke Kenneth Casso... create Memory for Cache Tags in I-Cache tree | commitdiff
2022-01-30 Luke Kenneth Casso... remove unneeded parameter tree | commitdiff
2022-01-30 Luke Kenneth Casso... add Array of CacheValids back in, so as to reduce LUT4... tree | commitdiff
2022-01-30 Luke Kenneth Casso... tagset is a local Signal in ICache tree | commitdiff
2022-01-30 Luke Kenneth Casso... identify combinatorial loop signals in MultiCompUnit... tree | commitdiff
2022-01-30 Luke Kenneth Casso... use nmigen Memory in I-Cache for TLB Lookups tree | commitdiff
2022-01-30 Luke Kenneth Casso... put itlb_valid back, ready for conversion to Memory... tree | commitdiff
2022-01-30 Luke Kenneth Casso... convert CacheRAM to Memory, acts much faster now tree | commitdiff
2022-01-29 Luke Kenneth Casso... explanatory comment when page hit is the same for stores tree | commitdiff
2022-01-29 Luke Kenneth Casso... use right offset in dcache wb address tree | commitdiff
2022-01-29 Luke Kenneth Casso... re-examining dcache.vhdl, still did not get the store... tree | commitdiff
2022-01-29 Luke Kenneth Casso... bug in dcache.py where when two stores occur in the... tree | commitdiff
2022-01-28 Luke Kenneth Casso... sort out misaligned store in LoadStore1 tree | commitdiff
2022-01-25 Luke Kenneth Casso... add license and copyright header to dcache.py, tree | commitdiff
2022-01-24 Luke Kenneth Casso... comments tree | commitdiff
2022-01-24 Luke Kenneth Casso... hmm there seems to have been an error in DTLB Read, tree | commitdiff
2022-01-23 Luke Kenneth Casso... looked in soc.vhdl in microwatt and the parameters... tree | commitdiff
2022-01-23 Luke Kenneth Casso... add debug output of whether stall occurs on dcache tree | commitdiff
2022-01-22 Luke Kenneth Casso... missed setting of r0_full to zero in dcache. not encoun... tree | commitdiff
2022-01-16 Luke Kenneth Casso... pass over store_done correctly from dcache over PortInt... tree | commitdiff
2022-01-16 Luke Kenneth Casso... add CR0 to LDSTCompUnit, for reporting if LR/SC store... tree | commitdiff
2022-01-16 Luke Kenneth Casso... remove PortInterface mmu_done signal, tree | commitdiff
2022-01-15 Luke Kenneth Casso... forgot name on dcache Reservation tree | commitdiff
2022-01-15 Luke Kenneth Casso... pass over atomic signals to dcache from loadstore. tree | commitdiff
2022-01-15 Luke Kenneth Casso... try using req.op in RELOAD_WAIT_ACK to detect whether... tree | commitdiff
2022-01-15 Luke Kenneth Casso... add atomic LR/SC signal to LDSTCompUnit tree | commitdiff
2022-01-15 Luke Kenneth Casso... add reserve (atomic) signal to LDST data structures... tree | commitdiff
2022-01-15 Luke Kenneth Casso... tidyup PortInterface tree | commitdiff
2022-01-15 Luke Kenneth Casso... workaround for bug in dcache where the r1.req waiting... ldst_misalign tree | commitdiff
2022-01-14 Luke Kenneth Casso... split out CacheTag Record to separate structure tree | commitdiff
2022-01-14 Luke Kenneth Casso... update how d_valid is handled tree | commitdiff
2022-01-14 Luke Kenneth Casso... missed setting r1.store_way and r1.store_row in STORE_W... tree | commitdiff
2022-01-14 Luke Kenneth Casso... Revert "dcache 2nd stage (r1) should only indicate... tree | commitdiff
2022-01-12 Luke Kenneth Casso... dcache 2nd stage (r1) should only indicate not-busy tree | commitdiff
2022-01-12 Luke Kenneth Casso... fix issue with d_valid in dcache, was not being set... tree | commitdiff
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error: tree | commitdiff
2022-01-08 Luke Kenneth Casso... fix MMU lookup after 2nd request (misaligned) by also... tree | commitdiff
2022-01-08 Luke Kenneth Casso... add microwatt mmu.bin test5 to show page-fault on misal... tree | commitdiff
2022-01-08 Luke Kenneth Casso... enable microwatt mmu test2 tree | commitdiff
2022-01-08 Luke Kenneth Casso... whitespace and use exc is None not exc == None tree | commitdiff
2022-01-08 Luke Kenneth Casso... add a second LD request to dcache which is merged with... tree | commitdiff
2022-01-08 Luke Kenneth Casso... start adding in mis-aligned LD/ST support into LoadStore1 tree | commitdiff
2022-01-08 Tobias Platenadd function test_pi_ld_misalign tree | commitdiff
2022-01-07 Tobias Platenbegin testcase for misalign tree | commitdiff
2022-01-07 Luke Kenneth Casso... whitespace tree | commitdiff
2022-01-07 Luke Kenneth Casso... add missing MSRSpec import tree | commitdiff
2022-01-06 Luke Kenneth Casso... double the number of lines in the L1 D/I-Cache to match... tree | commitdiff
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