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finish converting mul tests to use common code
[soc.git]
/
src
/
soc
/
fu
/
trap
/
pipe_data.py
2020-08-11
Luke Kenneth Casso...
reduce regfile ports by creating separate STATE regfile
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2020-07-21
Luke Kenneth Casso...
move cia and msr to trap input record
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2020-07-15
Luke Kenneth Casso...
remove unneeded comment in trap pipe_data
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
rename spr1 to fast1 in trap data
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2020-07-01
Luke Kenneth Casso...
debugging trap pipeline
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2020-07-01
Luke Kenneth Casso...
start running trap unit test, fixing errors
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2020-06-06
Luke Kenneth Casso...
remove unneeded imports
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2020-06-06
Luke Kenneth Casso...
noticed the regular pattern in all pipe_data.py (regspecs).
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2020-06-02
Luke Kenneth Casso...
rename regspecs to give a consistent naming scheme
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2020-05-27
Luke Kenneth Casso...
add SRR0 to TrapInputData
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2020-05-24
Luke Kenneth Casso...
spelling mistake in variable
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2020-05-24
Luke Kenneth Casso...
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
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2020-05-21
Luke Kenneth Casso...
move FU IntegerData to directory below
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2020-05-21
Luke Kenneth Casso...
add dedicated TrapPipeSpec
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2020-05-20
Luke Kenneth Casso...
add register specs to pipeline in/out so that they...
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2020-05-19
Luke Kenneth Casso...
hmmm, branch sets nia to Data as well and sets nia...
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2020-05-19
Luke Kenneth Casso...
whitespace
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2020-05-19
Luke Kenneth Casso...
use Data on SPRs in Trap InputData just like in BranchO...
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2020-05-19
Luke Kenneth Casso...
update comments
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2020-05-19
Michael Nolan
Add should_trap signal to trap output data
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2020-05-19
Michael Nolan
Begin adding trap FU
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