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whoops, ICS in litex sim needs to be 0x1000 size region
[soc.git] / src / soc / litex / florent / libresoc /
2020-09-05 Luke Kenneth Casso... increase wishbone address width to 29 for xics and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-04 Luke Kenneth Casso... add XICS memory regions, shrink litex CSR memmap size... tree | commitdiff
2020-09-04 Luke Kenneth Casso... adding XICS wb slave devices to litex sim tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Luke Kenneth Casso... add way to capture CR from DMI in litex sim tree | commitdiff
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus tree | commitdiff
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-08-05 Luke Kenneth Casso... rename ibus/dbus (shorten) tree | commitdiff
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... more remove wildcard imports tree | commitdiff
2020-08-04 Luke Kenneth Casso... adding litex sim experimentation. tree | commitdiff