projects
/
soc.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅
next
Complete the formal proof of the pseudo dual port SRAM
[soc.git]
/
src
/
soc
/
regfile
/
2022-04-03
Cesar Strauss
Complete the formal proof of the pseudo dual port SRAM
tree
|
commitdiff
2022-04-03
Cesar Strauss
Implement a debug port on the pseudo 1W/1R SRAM
tree
|
commitdiff
2022-04-03
Cesar Strauss
Formal proof of the phased write dual port memory wrapper
tree
|
commitdiff
2022-04-02
Cesar Strauss
Implement transparent read ports on the phased write...
tree
|
commitdiff
2022-04-02
Cesar Strauss
Implement and test a "phased write port" memory
tree
|
commitdiff
2022-03-27
Cesar Strauss
Finish the SRAM formal proof by implementing induction
tree
|
commitdiff
2022-03-26
Cesar Strauss
Add formal verification of the single port memory block
tree
|
commitdiff
2022-03-13
Cesar Strauss
Simulate some read/write/modify operations on the SRAM...
tree
|
commitdiff
2022-03-13
Cesar Strauss
Add a Single R/W Port SRAM model
tree
|
commitdiff
2022-02-27
Luke Kenneth Casso...
add XLEN option to regfiles via pspec
tree
|
commitdiff
2022-02-20
Luke Kenneth Casso...
add syn_ramstyle "block_ram" attributes and reduce...
tree
|
commitdiff
2022-02-18
Luke Kenneth Casso...
add blockram style to regfile Memory
tree
|
commitdiff
2022-01-19
Luke Kenneth Casso...
move DEC and TB into StateRegs, to make room in FastRegs
tree
|
commitdiff
2022-01-18
Luke Kenneth Casso...
add support for DMI debug read of FAST Regfile SPRs
tree
|
commitdiff
2022-01-04
Luke Kenneth Casso...
fix DriverConflict over MSR write in Issuer/Core by...
tree
|
commitdiff
2021-12-23
Luke Kenneth Casso...
allow MSR reset to default to a value set by issuer_ver...
tree
|
commitdiff
2021-12-23
Luke Kenneth Casso...
add ability to set the reset values of RegFileArray
tree
|
commitdiff
2021-11-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2021-11-29
Luke Kenneth Casso...
always set fwd_bus_mode=False on regfiles
tree
|
commitdiff
2021-11-24
Luke Kenneth Casso...
convert hazard bitvectors to Reset-Priority SRLatch...
tree
|
commitdiff
2021-11-24
Luke Kenneth Casso...
add 2nd hazard bitvector port for write-after-write
tree
|
commitdiff
2021-11-21
Luke Kenneth Casso...
fixed issue with hazard dependencies, read will nott
tree
|
commitdiff
2021-11-17
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2021-11-17
Luke Kenneth Casso...
core hazard bitvector regfiles need to be readable
tree
|
commitdiff
2021-11-16
Luke Kenneth Casso...
use a virtual regfile port for the hazard bitvectors
tree
|
commitdiff
2021-11-16
Luke Kenneth Casso...
create set/get ports for bitvectors
tree
|
commitdiff
2021-11-16
Luke Kenneth Casso...
rename regports for bitvectors so that
tree
|
commitdiff
2021-11-16
Luke Kenneth Casso...
whoops, hazard vectors were depth 1 width N
tree
|
commitdiff
2021-11-11
Luke Kenneth Casso...
fix regfile port names for "fast" port access (regreduc...
tree
|
commitdiff
2021-11-11
Luke Kenneth Casso...
add exact same number - and name - bitvector ports...
tree
|
commitdiff
2021-11-11
Luke Kenneth Casso...
code-morph regfile port specs to a dictionary format...
tree
|
commitdiff
2021-11-10
Luke Kenneth Casso...
morph regfiles to add hazard vector make_vecs function
tree
|
commitdiff
2021-11-07
Luke Kenneth Casso...
add hazard vectors to Regfiles
tree
|
commitdiff
2021-11-07
Luke Kenneth Casso...
add quick test of regfiles to output rtlil
tree
|
commitdiff
2021-08-24
Luke Kenneth Casso...
replace data_o with o_data and data_i with i_data as...
tree
|
commitdiff
2021-05-04
Luke Kenneth Casso...
add SVSTATE (SVSRR0) to TRAP pipeline
tree
|
commitdiff
2021-05-04
Luke Kenneth Casso...
missed that soc.regfile.util has moved to openpower...
tree
|
commitdiff
2021-05-04
Luke Kenneth Casso...
add SVSRR0 to FastRegsEnum
tree
|
commitdiff
2021-04-27
Luke Kenneth Casso...
add option to disable bus forwarding on SPRs and FAST...
tree
|
commitdiff
2021-04-27
Luke Kenneth Casso...
add option to enable/disable bus forwarding mode on...
tree
|
commitdiff
2021-04-23
Luke Kenneth Casso...
move to import from openpower-isa for reg enums
tree
|
commitdiff
2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
tree
|
commitdiff
2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
tree
|
commitdiff
2021-03-30
Luke Kenneth Casso...
use port name for INT regfile to match up with test_run...
tree
|
commitdiff
2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
tree
|
commitdiff
2021-03-28
Luke Kenneth Casso...
add option to reduce number of regfile ports (get DFFs...
tree
|
commitdiff
2021-03-28
Luke Kenneth Casso...
reduce regfile port usage on non-svp64
tree
|
commitdiff
2021-03-17
Luke Kenneth Casso...
add predication read ports (CR and INT)
tree
|
commitdiff
2021-03-02
Luke Kenneth Casso...
sort out SPR setting in MMU
tree
|
commitdiff
2021-02-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2021-02-14
Luke Kenneth Casso...
add Regfiles comments
tree
|
commitdiff
2021-01-28
Luke Kenneth Casso...
add SVSTATE to StateRegs
tree
|
commitdiff
2020-09-06
Luke Kenneth Casso...
add reset option to Register
tree
|
commitdiff
2020-09-06
Luke Kenneth Casso...
add unit test for slow SPRs (SPRG0/1)
tree
|
commitdiff
2020-09-06
Luke Kenneth Casso...
minor code-munge on SPR-to-FAST mapping
tree
|
commitdiff
2020-09-06
Luke Kenneth Casso...
move DEC and TB from StateRegs to FastRegs for several...
tree
|
commitdiff
2020-09-06
Luke Kenneth Casso...
add DEC and TB to State regfile
tree
|
commitdiff
2020-08-31
Luke Kenneth Casso...
add XER to fastregs and "construct" it in mfspr/mtspr
tree
|
commitdiff
2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
|
commitdiff
2020-08-25
Luke Kenneth Casso...
add CR read to DMI interface
tree
|
commitdiff
2020-08-15
Luke Kenneth Casso...
rather big change to interaction between regfile and...
tree
|
commitdiff
2020-08-14
Luke Kenneth Casso...
put multi-ports back (for read) on int and fast regfiles
tree
|
commitdiff
2020-08-13
Luke Kenneth Casso...
add forwarding-bus mode to Regfile Memory (and disable it)
tree
|
commitdiff
2020-08-13
Luke Kenneth Casso...
sigh. convert Fast regfile to binary
tree
|
commitdiff
2020-08-13
Luke Kenneth Casso...
sigh. convert INT regfile to binary addressing
tree
|
commitdiff
2020-08-13
Luke Kenneth Casso...
create a RegFileMem class that uses Memory
tree
|
commitdiff
2020-08-11
Luke Kenneth Casso...
sigh, remove yet another int regfile read port
tree
|
commitdiff
2020-08-11
Luke Kenneth Casso...
reduce regfile port usage for INT and FAST
tree
|
commitdiff
2020-08-11
Luke Kenneth Casso...
reduce regfile ports by creating separate STATE regfile
tree
|
commitdiff
2020-08-11
Luke Kenneth Casso...
reducing regfile port usage by sharing read ports
tree
|
commitdiff
2020-08-03
Luke Kenneth Casso...
add extra port for debug read of int regs via DMI
tree
|
commitdiff
2020-07-29
Jacob Lifshay
add __init__.py to all source directories
tree
|
commitdiff
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
tree
|
commitdiff
2020-07-22
Jacob Lifshay
format code
tree
|
commitdiff
2020-07-22
Luke Kenneth Casso...
reduce number of FastRegs read ports
tree
|
commitdiff
2020-07-14
Luke Kenneth Casso...
add MSR reading to issue FSM
tree
|
commitdiff
2020-07-08
Luke Kenneth Casso...
adding in ALU test back in, debugging SPR setup
tree
|
commitdiff
2020-07-08
Luke Kenneth Casso...
sorting out setting of XER
tree
|
commitdiff
2020-07-08
Luke Kenneth Casso...
add spr to fast reg converter
tree
|
commitdiff
2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2020-07-05
Luke Kenneth Casso...
add slow spr regfile regspec support
tree
|
commitdiff
2020-07-04
Luke Kenneth Casso...
more rename spr1/spr2 to fast1/fast2
tree
|
commitdiff
2020-07-04
Luke Kenneth Casso...
add gitignores
tree
|
commitdiff
2020-07-04
Luke Kenneth Casso...
debugging decoding of SPRs (fast)
tree
|
commitdiff
2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2020-06-18
Luke Kenneth Casso...
slightly hacky way to keep an eye on the PC
tree
|
commitdiff
2020-06-16
Luke Kenneth Casso...
add test instruction memory SRAM
tree
|
commitdiff
2020-06-05
Luke Kenneth Casso...
name regfile ports by name not numerical position
tree
|
commitdiff
2020-06-05
Luke Kenneth Casso...
whoops connecting up CR in wrong order. fixing with...
tree
|
commitdiff
2020-06-05
Luke Kenneth Casso...
fix syntax errors and use correct FastRegs (SRR0/1...
tree
|
commitdiff
2020-06-04
Luke Kenneth Casso...
initialise XER from simulation
tree
|
commitdiff
2020-06-04
Luke Kenneth Casso...
add extra argument (not used) to regfile.py
tree
|
commitdiff
2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
tree
|
commitdiff
2020-06-04
Luke Kenneth Casso...
missing a fastregs write-port
tree
|
commitdiff
2020-06-03
Luke Kenneth Casso...
connect read-enable and src_i to regfile ports
tree
|
commitdiff
2020-06-03
Luke Kenneth Casso...
start putting a non-production core together,
tree
|
commitdiff
2020-06-03
Luke Kenneth Casso...
decide to elaborate Refiles *into* another class, rathe...
tree
|
commitdiff
2020-06-03
Luke Kenneth Casso...
turn RegFiles into module, add all regfiles to it
tree
|
commitdiff
2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
|
commitdiff
2020-06-03
Luke Kenneth Casso...
add class containing all regfiles
tree
|
commitdiff
next