2021-11-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-29 |
Luke Kenneth Casso... | always set fwd_bus_mode=False on regfiles |
tree | commitdiff |
2021-11-24 |
Luke Kenneth Casso... | convert hazard bitvectors to Reset-Priority SRLatch... |
tree | commitdiff |
2021-11-24 |
Luke Kenneth Casso... | add 2nd hazard bitvector port for write-after-write |
tree | commitdiff |
2021-11-21 |
Luke Kenneth Casso... | fixed issue with hazard dependencies, read will nott |
tree | commitdiff |
2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-17 |
Luke Kenneth Casso... | core hazard bitvector regfiles need to be readable |
tree | commitdiff |
2021-11-16 |
Luke Kenneth Casso... | use a virtual regfile port for the hazard bitvectors |
tree | commitdiff |
2021-11-16 |
Luke Kenneth Casso... | create set/get ports for bitvectors |
tree | commitdiff |
2021-11-16 |
Luke Kenneth Casso... | rename regports for bitvectors so that |
tree | commitdiff |
2021-11-16 |
Luke Kenneth Casso... | whoops, hazard vectors were depth 1 width N |
tree | commitdiff |
2021-11-11 |
Luke Kenneth Casso... | fix regfile port names for "fast" port access (regreduc... |
tree | commitdiff |
2021-11-11 |
Luke Kenneth Casso... | add exact same number - and name - bitvector ports... |
tree | commitdiff |
2021-11-11 |
Luke Kenneth Casso... | code-morph regfile port specs to a dictionary format... |
tree | commitdiff |
2021-11-10 |
Luke Kenneth Casso... | morph regfiles to add hazard vector make_vecs function |
tree | commitdiff |
2021-11-07 |
Luke Kenneth Casso... | add hazard vectors to Regfiles |
tree | commitdiff |
2021-11-07 |
Luke Kenneth Casso... | add quick test of regfiles to output rtlil |
tree | commitdiff |
2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add SVSTATE (SVSRR0) to TRAP pipeline |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | missed that soc.regfile.util has moved to openpower... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add SVSRR0 to FastRegsEnum |
tree | commitdiff |
2021-04-27 |
Luke Kenneth Casso... | add option to disable bus forwarding on SPRs and FAST... |
tree | commitdiff |
2021-04-27 |
Luke Kenneth Casso... | add option to enable/disable bus forwarding mode on... |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move to import from openpower-isa for reg enums |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
tree | commitdiff |
2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2021-03-30 |
Luke Kenneth Casso... | use port name for INT regfile to match up with test_run... |
tree | commitdiff |
2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
tree | commitdiff |
2021-03-28 |
Luke Kenneth Casso... | add option to reduce number of regfile ports (get DFFs... |
tree | commitdiff |
2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
tree | commitdiff |
2021-03-17 |
Luke Kenneth Casso... | add predication read ports (CR and INT) |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
tree | commitdiff |
2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add Regfiles comments |
tree | commitdiff |
2021-01-28 |
Luke Kenneth Casso... | add SVSTATE to StateRegs |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | add reset option to Register |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | add unit test for slow SPRs (SPRG0/1) |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | minor code-munge on SPR-to-FAST mapping |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | move DEC and TB from StateRegs to FastRegs for several... |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | add DEC and TB to State regfile |
tree | commitdiff |
2020-08-31 |
Luke Kenneth Casso... | add XER to fastregs and "construct" it in mfspr/mtspr |
tree | commitdiff |
2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
tree | commitdiff |
2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | put multi-ports back (for read) on int and fast regfiles |
tree | commitdiff |
2020-08-13 |
Luke Kenneth Casso... | add forwarding-bus mode to Regfile Memory (and disable it) |
tree | commitdiff |
2020-08-13 |
Luke Kenneth Casso... | sigh. convert Fast regfile to binary |
tree | commitdiff |
2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
tree | commitdiff |
2020-08-13 |
Luke Kenneth Casso... | create a RegFileMem class that uses Memory |
tree | commitdiff |
2020-08-11 |
Luke Kenneth Casso... | sigh, remove yet another int regfile read port |
tree | commitdiff |
2020-08-11 |
Luke Kenneth Casso... | reduce regfile port usage for INT and FAST |
tree | commitdiff |
2020-08-11 |
Luke Kenneth Casso... | reduce regfile ports by creating separate STATE regfile |
tree | commitdiff |
2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
tree | commitdiff |
2020-08-03 |
Luke Kenneth Casso... | add extra port for debug read of int regs via DMI |
tree | commitdiff |
2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | format code |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | reduce number of FastRegs read ports |
tree | commitdiff |
2020-07-14 |
Luke Kenneth Casso... | add MSR reading to issue FSM |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | adding in ALU test back in, debugging SPR setup |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | sorting out setting of XER |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | add spr to fast reg converter |
tree | commitdiff |
2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | add slow spr regfile regspec support |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | more rename spr1/spr2 to fast1/fast2 |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | add gitignores |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | debugging decoding of SPRs (fast) |
tree | commitdiff |
2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-18 |
Luke Kenneth Casso... | slightly hacky way to keep an eye on the PC |
tree | commitdiff |
2020-06-16 |
Luke Kenneth Casso... | add test instruction memory SRAM |
tree | commitdiff |
2020-06-05 |
Luke Kenneth Casso... | name regfile ports by name not numerical position |
tree | commitdiff |
2020-06-05 |
Luke Kenneth Casso... | whoops connecting up CR in wrong order. fixing with... |
tree | commitdiff |
2020-06-05 |
Luke Kenneth Casso... | fix syntax errors and use correct FastRegs (SRR0/1... |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | initialise XER from simulation |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | add extra argument (not used) to regfile.py |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | missing a fastregs write-port |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | connect read-enable and src_i to regfile ports |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | start putting a non-production core together, |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | decide to elaborate Refiles *into* another class, rathe... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | turn RegFiles into module, add all regfiles to it |
tree | commitdiff |
2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | add class containing all regfiles |
tree | commitdiff |
2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-02 |
Luke Kenneth Casso... | decode fast spr for OP_BCREG CTR, TAR and LR |
tree | commitdiff |
2020-06-02 |
Luke Kenneth Casso... | whoops cut/paste error, creating write_ports not read_ports |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Add proof for RegFile |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Add proof for RegFileArray |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Have regfile use AnySeq instead of AnyConst |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Enable k-induction for register file proof |
tree | commitdiff |
2020-06-01 |
Michael Nolan | That was weird. For some reason it wasn't generating... |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Full BMC proof of Register |
tree | commitdiff |
2020-06-01 |
Michael Nolan | Begin rewrite of proof_regfile.py |
tree | commitdiff |
2020-05-29 |
Luke Kenneth Casso... | interesting. use of Settle() works, showing that Regfi... |
tree | commitdiff |
2020-05-28 |
Luke Kenneth Casso... | messing about with proof_regfile.py |
tree | commitdiff |
2020-05-28 |
colepoirier | Added Initial() synchronous check with draft truth |
tree | commitdiff |
2020-05-28 |
Luke Kenneth Casso... | hmm.... |
tree | commitdiff |
2020-05-28 |
colepoirier | Add sync Assert for _wrports 'wen' signal in proof_regf... |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | do not use range(0, x) - just range(x) |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | remove write-block on register zero |
tree | commitdiff |
next |