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finished remaining hdl items
[soc.git] / src / soc / simple / test /
2021-09-09 klehmanfinished remaining hdl items tree | commitdiff
2021-09-09 klehmanHDL int reg added tree | commitdiff
2021-09-09 klehmanmore sim class registers add tree | commitdiff
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in... tree | commitdiff
2021-09-08 klehmaninitial commit of sim state class tree | commitdiff
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2 tree | commitdiff
2021-09-07 Luke Kenneth Casso... fun fixing of get_core_hdl_regs, "yield from" tree | commitdiff
2021-09-07 Luke Kenneth Casso... move functions to above where they are called tree | commitdiff
2021-09-07 klehmanbreakout of register collection and compare tree | commitdiff
2021-09-07 Cesar StraussFix typo. tree | commitdiff
2021-09-07 Luke Kenneth Casso... add TODO code-comments tree | commitdiff
2021-09-07 Luke Kenneth Casso... whitespace, add bug ref number to test API tree | commitdiff
2021-08-29 Luke Kenneth Casso... unnecessary signal rename ivalid_i to ii_valid (reverting) tree | commitdiff
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as... tree | commitdiff
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea... tree | commitdiff
2021-08-17 Cesar StraussEnable LD/ST exception test case tree | commitdiff
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option tree | commitdiff
2021-08-16 Tobias Platenadd WIP DCBZTestCase tree | commitdiff
2021-08-01 Jonathan Neuschäferimport setup_i_memory from soc.simple.test.test_runner tree | commitdiff
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid... tree | commitdiff
2021-07-24 Tobias Platenadd test_issuer_dcache.py tree | commitdiff
2021-07-15 Luke Kenneth Casso... update TestRunner, SVSTATE is now a class that inherits... tree | commitdiff
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy) tree | commitdiff
2021-07-12 Luke Kenneth Casso... use standard create_pdecode in TestRunner tree | commitdiff
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-07-10 Cesar StraussShow some usage of PortInterface in action tree | commitdiff
2021-05-22 Cesar StraussMove the reset code outside of the sub-test tree | commitdiff
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational. tree | commitdiff
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU tree | commitdiff
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that... tree | commitdiff
2021-05-06 Luke Kenneth Casso... whoops disabled tests agaaaaain tree | commitdiff
2021-05-06 Luke Kenneth Casso... add in predicate mask bit detection when zeroing is... tree | commitdiff
2021-05-06 Luke Kenneth Casso... moved exts* SVP64 unit tests to a different location tree | commitdiff
2021-05-04 Luke Kenneth Casso... whoops disabled some test_issuer group tests tree | commitdiff
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit tree | commitdiff
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test. tree | commitdiff
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER... tree | commitdiff
2021-05-01 Luke Kenneth Casso... add LD/ST cases to MMU, which should all still work tree | commitdiff
2021-05-01 Luke Kenneth Casso... add MMUTestCaseROM tree | commitdiff
2021-05-01 Luke Kenneth Casso... use new AllFunctionUnits.get_fu function tree | commitdiff
2021-05-01 Luke Kenneth Casso... use SPRreduced to match PowerDecoder2 tree | commitdiff
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able... tree | commitdiff
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py tree | commitdiff
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte... tree | commitdiff
2021-04-30 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=635 tree | commitdiff
2021-04-30 Luke Kenneth Casso... better reporting on gpr comparisons tree | commitdiff
2021-04-23 Luke Kenneth Casso... add comments on TestIssuer TestRunner tree | commitdiff
2021-04-23 Luke Kenneth Casso... comment tests back in tree | commitdiff
2021-04-23 Luke Kenneth Casso... error in setting fast regs test values tree | commitdiff
2021-04-23 Luke Kenneth Casso... import from openpower.tests tree | commitdiff
2021-04-23 Luke Kenneth Casso... use openpower.test.common tree | commitdiff
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... move over to from openpower imports tree | commitdiff
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu tree | commitdiff
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling... tree | commitdiff
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2021-03-30 Luke Kenneth Casso... use port name for INT regfile to match up with test_run... tree | commitdiff
2021-03-30 Cesar StraussMemory port seems to have been renamed tree | commitdiff
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size tree | commitdiff
2021-03-28 Luke Kenneth Casso... reduce number of regfile ports tree | commitdiff
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding tree | commitdiff
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document tree | commitdiff
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on tree | commitdiff
2021-03-08 Luke Kenneth Casso... actually make it possible to disable svp64 on commandli... tree | commitdiff
2021-03-08 Luke Kenneth Casso... add option in TestRunner to disable svp64 via commandli... tree | commitdiff
2021-03-03 Luke Kenneth Casso... set SVSTATE in TestRunner using new TestIssuer.svstate_i tree | commitdiff
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i tree | commitdiff
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU tree | commitdiff
2021-02-27 Cesar StraussAdd traces for the new FSM tree | commitdiff
2021-02-24 Tobias Platentest_runner.py: add needed imports tree | commitdiff
2021-02-23 Tobias Platendeduplicate tree | commitdiff
2021-02-22 Luke Kenneth Casso... whoops tree | commitdiff
2021-02-22 Luke Kenneth Casso... moving PC-setting (NIA) out of execute_fsm in TestIssuer tree | commitdiff
2021-02-21 Cesar StraussHide the register augmentation traces by default tree | commitdiff
2021-02-21 Luke Kenneth Casso... move fetch_fsm to separate function in TestIssuer tree | commitdiff
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs tree | commitdiff
2021-02-20 Luke Kenneth Casso... whoops set ROM to none by mistake tree | commitdiff
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self... tree | commitdiff
2021-02-20 Tobias Platenadd rom debugger tree | commitdiff
2021-02-20 Tobias Platenadd mmu rom testcase tree | commitdiff
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output tree | commitdiff
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging... tree | commitdiff
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding... tree | commitdiff
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the... tree | commitdiff
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues tree | commitdiff
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start tree | commitdiff
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL tree | commitdiff
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file tree | commitdiff
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-02-14 Cesar StraussShow traces for the register numbers of the current... tree | commitdiff
2021-02-14 Luke Kenneth Casso... add TestRunner comments tree | commitdiff
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction tree | commitdiff
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test tree | commitdiff
2021-02-13 Luke Kenneth Casso... split out TestRunner into separate module tree | commitdiff
2021-02-12 Luke Kenneth Casso... add SVSTATE to TestCase infrastructure for use in TestI... tree | commitdiff
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