remove bitmanip fu cuz ternlogi (the only instruction implemented so far) is in shift...
[soc.git] / src / soc / simple /
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth Casso... FunctionUnitBaseMulti which derives from ReservationSta...
2021-12-01 Luke Kenneth Casso... better name for read latch in core.py
2021-12-01 Luke Kenneth Casso... remove redundant / mis-named variable in core
2021-12-01 Luke Kenneth Casso... code-comments
2021-12-01 Luke Kenneth Casso... remove unneeded data structure in core
2021-12-01 Luke Kenneth Casso... whoops treereduce on write-vector set/clr error
2021-12-01 Luke Kenneth Casso... more code-cleanup
2021-12-01 Luke Kenneth Casso... use new regspec_decode and fu.get_iospec functions
2021-12-01 Luke Kenneth Casso... core tidyup
2021-11-30 Luke Kenneth Casso... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth Casso... add LogicalTestCases back in to test_core.py (pass)
2021-11-30 Luke Kenneth Casso... let PowerDecode2 decide which operand class to use...
2021-11-30 Luke Kenneth Casso... use latched readflag (recspec_decode_read "ok") instead...
2021-11-30 Luke Kenneth Casso... tidyup on read-flag latches
2021-11-30 Luke Kenneth Casso... fix read-decode information by latching not just the...
2021-11-30 Luke Kenneth Casso... fix write-after-write hazard checking
2021-11-30 Luke Kenneth Casso... allow busy to settle before checking state in test_core.py
2021-11-30 Luke Kenneth Casso... only check regs right at the end in test_core.py overla...
2021-11-30 Luke Kenneth Casso... move sim call before core run in test_core.py
2021-11-30 Luke Kenneth Casso... getting formerly unused test_core.py operational
2021-11-29 Luke Kenneth Casso... whoops missed make_hazard_vec test
2021-11-29 Luke Kenneth Casso... whoops do the set/get of the write-vector at a single...
2021-11-29 Luke Kenneth Casso... add MMU and SPR to list of FUs that must report "busy...
2021-11-29 Luke Kenneth Casso... disallow overlap in core on LDST, Branch, and Trap.
2021-11-29 Luke Kenneth Casso... use dict style not setattr on submodules
2021-11-27 Luke Kenneth Casso... code-comments
2021-11-27 Luke Kenneth Casso... fix instructions of the type "read-reg-is-same-as-write"
2021-11-24 Luke Kenneth Casso... convert hazard bitvectors to Reset-Priority SRLatch...
2021-11-24 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-24 Luke Kenneth Casso... fix write-after-write hazard detection
2021-11-24 Luke Kenneth Casso... when allow_overlap enabled do a manual wait until all...
2021-11-24 Luke Kenneth Casso... code-comments
2021-11-24 Luke Kenneth Casso... add write-after-write hazard detection
2021-11-24 Luke Kenneth Casso... whoops merged the two write-ports for RT and RA-with...
2021-11-24 Luke Kenneth Casso... disable hazard vectors when overlap is not requested...
2021-11-23 Luke Kenneth Casso... more comments
2021-11-23 Luke Kenneth Casso... add FU write-after-write hazard detection Signal (dummy...
2021-11-23 Luke Kenneth Casso... add code-comments, link to in-order core
2021-11-23 Luke Kenneth Casso... more use of namedtuples in core.py for clarity
2021-11-23 Luke Kenneth Casso... start some use of namedtuples in core.py
2021-11-23 Luke Kenneth Casso... use some namedtuples to make things clearer in core.py
2021-11-23 Luke Kenneth Casso... use fascinating trick of defaultdict-of-defaultdicts
2021-11-22 Luke Kenneth Casso... make FetchFSM take PC as an input in its ispec
2021-11-22 Luke Kenneth Casso... local variable rename in FetchFSM
2021-11-22 Luke Kenneth Casso... split out FetchFSM into separate module
2021-11-22 Luke Kenneth Casso... whoops accidentally committed commented-out test for...
2021-11-21 Luke Kenneth Casso... reset execute back to ISSUE_START if at INSN_WAIT and
2021-11-21 Luke Kenneth Casso... restrict (refine) hazard selection to the one being...
2021-11-21 Luke Kenneth Casso... block picker hazard on input to PriorityPicker rather...
2021-11-21 Luke Kenneth Casso... parse test_issuer args allow option "allow-overlap...
2021-11-21 Luke Kenneth Casso... complex. TestRunner now does not work properly unless...
2021-11-21 Luke Kenneth Casso... fixed issue with hazard dependencies, read will nott
2021-11-19 Luke Kenneth Casso... add both bitdict and selected args to connect_rd/wrport
2021-11-19 Luke Kenneth Casso... sorting out issue hazard conflicts in core.
2021-11-19 Luke Kenneth Casso... debug and cleanup
2021-11-19 Luke Kenneth Casso... rename instruction_active to instr_active in core
2021-11-19 Luke Kenneth Casso... read latch on regfile ports was fine, the combinatorial...
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth Casso... latch copy of read register numbers, not in use due...
2021-11-19 Luke Kenneth Casso... use read spec in connect_rdport rather than list of...
2021-11-19 Luke Kenneth Casso... capture write regfile numbers into write latches in...
2021-11-19 Luke Kenneth Casso... code tidyup / comments, and use defaultdict
2021-11-19 Luke Kenneth Casso... create lists of latches in each FU, to record the read...
2021-11-18 Luke Kenneth Casso... remove combinatorial loop in core instruction conflict...
2021-11-18 Luke Kenneth Casso... experimenting with overlapping instructions, bit of...
2021-11-18 Luke Kenneth Casso... set up core processing FSM, which captures data if...
2021-11-18 Luke Kenneth Casso... set up a temporary copy of CoreInput
2021-11-18 Luke Kenneth Casso... experiment allowing overlap (activated with --allow...
2021-11-18 Luke Kenneth Casso... remove unneeded import
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Luke Kenneth Casso... reading of regfile bitvector added, which activates...
2021-11-17 Luke Kenneth Casso... add option to test_issuer.py to allow for overlapping...
2021-11-17 Luke Kenneth Casso... add ability to run hazard instruction for test purposes
2021-11-17 Luke Kenneth Casso... detect the case in Core bitvector when the Function...
2021-11-17 Luke Kenneth Casso... missing optional check on make_hazard_vecs
2021-11-17 Luke Kenneth Casso... move core hazard set/clear to separate function, for...
2021-11-17 Luke Kenneth Casso... whoops context-indentation by mistake (no harm done...
2021-11-17 Luke Kenneth Casso... add a FetchOutput pipeline data structure
2021-11-16 Luke Kenneth Casso... print out regfile unary status, bit of name-cleanup
2021-11-16 Luke Kenneth Casso... use a virtual regfile port for the hazard bitvectors
2021-11-16 Luke Kenneth Casso... create set/get ports for bitvectors
2021-11-16 Luke Kenneth Casso... capture write port (wrflag) in byregfiles_spec for...
2021-11-16 Luke Kenneth Casso... rename regports for bitvectors so that
2021-11-16 Luke Kenneth Casso... starting to get write-clear of hazard vectors operating
2021-11-13 Luke Kenneth Casso... start adding hazard vector setting in core (unfinished)
2021-11-11 Luke Kenneth Casso... debug prints
2021-11-11 Luke Kenneth Casso... fix regfile port names for "fast" port access (regreduc...
2021-11-11 Luke Kenneth Casso... code-comments
2021-11-11 Luke Kenneth Casso... split out core input/output into separate file core_data.py
2021-11-11 Luke Kenneth Casso... enable hazard vecs in core
2021-11-11 Luke Kenneth Casso... invert numbering on CR HDLState.get_crregs
2021-11-10 Luke Kenneth Casso... update store data reg 10 to 0xfe in virtmode mmu test
2021-11-10 Luke Kenneth Casso... allow MSR to be set in StateRegs in test_core.py
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Tobias Platentest testcase for exception
2021-11-10 Luke Kenneth Casso... make core busy_o part of the CoreOutput data structure
2021-11-10 Luke Kenneth Casso... add a "fu_found" signal to core, which allows for an...
2021-11-09 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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