2021-11-30 |
Luke Kenneth Casso... | getting formerly unused test_core.py operational |
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2021-11-29 |
Luke Kenneth Casso... | whoops missed make_hazard_vec test |
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2021-11-29 |
Luke Kenneth Casso... | whoops do the set/get of the write-vector at a single... |
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2021-11-29 |
Luke Kenneth Casso... | add MMU and SPR to list of FUs that must report "busy... |
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2021-11-29 |
Luke Kenneth Casso... | disallow overlap in core on LDST, Branch, and Trap. |
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2021-11-29 |
Luke Kenneth Casso... | use dict style not setattr on submodules |
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2021-11-27 |
Luke Kenneth Casso... | code-comments |
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2021-11-27 |
Luke Kenneth Casso... | fix instructions of the type "read-reg-is-same-as-write" |
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2021-11-24 |
Luke Kenneth Casso... | convert hazard bitvectors to Reset-Priority SRLatch... |
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2021-11-24 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-24 |
Luke Kenneth Casso... | fix write-after-write hazard detection |
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2021-11-24 |
Luke Kenneth Casso... | when allow_overlap enabled do a manual wait until all... |
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2021-11-24 |
Luke Kenneth Casso... | code-comments |
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2021-11-24 |
Luke Kenneth Casso... | add write-after-write hazard detection |
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2021-11-24 |
Luke Kenneth Casso... | whoops merged the two write-ports for RT and RA-with... |
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2021-11-24 |
Luke Kenneth Casso... | disable hazard vectors when overlap is not requested... |
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2021-11-23 |
Luke Kenneth Casso... | more comments |
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2021-11-23 |
Luke Kenneth Casso... | add FU write-after-write hazard detection Signal (dummy... |
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2021-11-23 |
Luke Kenneth Casso... | add code-comments, link to in-order core |
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2021-11-23 |
Luke Kenneth Casso... | more use of namedtuples in core.py for clarity |
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2021-11-23 |
Luke Kenneth Casso... | start some use of namedtuples in core.py |
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2021-11-23 |
Luke Kenneth Casso... | use some namedtuples to make things clearer in core.py |
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2021-11-23 |
Luke Kenneth Casso... | use fascinating trick of defaultdict-of-defaultdicts |
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2021-11-22 |
Luke Kenneth Casso... | make FetchFSM take PC as an input in its ispec |
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2021-11-22 |
Luke Kenneth Casso... | local variable rename in FetchFSM |
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2021-11-22 |
Luke Kenneth Casso... | split out FetchFSM into separate module |
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2021-11-22 |
Luke Kenneth Casso... | whoops accidentally committed commented-out test for... |
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2021-11-21 |
Luke Kenneth Casso... | reset execute back to ISSUE_START if at INSN_WAIT and |
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2021-11-21 |
Luke Kenneth Casso... | restrict (refine) hazard selection to the one being... |
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2021-11-21 |
Luke Kenneth Casso... | block picker hazard on input to PriorityPicker rather... |
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2021-11-21 |
Luke Kenneth Casso... | parse test_issuer args allow option "allow-overlap... |
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2021-11-21 |
Luke Kenneth Casso... | complex. TestRunner now does not work properly unless... |
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2021-11-21 |
Luke Kenneth Casso... | fixed issue with hazard dependencies, read will nott |
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2021-11-19 |
Luke Kenneth Casso... | add both bitdict and selected args to connect_rd/wrport |
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2021-11-19 |
Luke Kenneth Casso... | sorting out issue hazard conflicts in core. |
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2021-11-19 |
Luke Kenneth Casso... | debug and cleanup |
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2021-11-19 |
Luke Kenneth Casso... | rename instruction_active to instr_active in core |
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2021-11-19 |
Luke Kenneth Casso... | read latch on regfile ports was fine, the combinatorial... |
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2021-11-19 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-19 |
Luke Kenneth Casso... | latch copy of read register numbers, not in use due... |
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2021-11-19 |
Luke Kenneth Casso... | use read spec in connect_rdport rather than list of... |
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2021-11-19 |
Luke Kenneth Casso... | capture write regfile numbers into write latches in... |
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2021-11-19 |
Luke Kenneth Casso... | code tidyup / comments, and use defaultdict |
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2021-11-19 |
Luke Kenneth Casso... | create lists of latches in each FU, to record the read... |
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2021-11-18 |
Luke Kenneth Casso... | remove combinatorial loop in core instruction conflict... |
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2021-11-18 |
Luke Kenneth Casso... | experimenting with overlapping instructions, bit of... |
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2021-11-18 |
Luke Kenneth Casso... | set up core processing FSM, which captures data if... |
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2021-11-18 |
Luke Kenneth Casso... | set up a temporary copy of CoreInput |
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2021-11-18 |
Luke Kenneth Casso... | experiment allowing overlap (activated with --allow... |
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2021-11-18 |
Luke Kenneth Casso... | remove unneeded import |
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2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-17 |
Luke Kenneth Casso... | reading of regfile bitvector added, which activates... |
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2021-11-17 |
Luke Kenneth Casso... | add option to test_issuer.py to allow for overlapping... |
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2021-11-17 |
Luke Kenneth Casso... | add ability to run hazard instruction for test purposes |
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2021-11-17 |
Luke Kenneth Casso... | detect the case in Core bitvector when the Function... |
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2021-11-17 |
Luke Kenneth Casso... | missing optional check on make_hazard_vecs |
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2021-11-17 |
Luke Kenneth Casso... | move core hazard set/clear to separate function, for... |
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2021-11-17 |
Luke Kenneth Casso... | whoops context-indentation by mistake (no harm done... |
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2021-11-17 |
Luke Kenneth Casso... | add a FetchOutput pipeline data structure |
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2021-11-16 |
Luke Kenneth Casso... | print out regfile unary status, bit of name-cleanup |
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2021-11-16 |
Luke Kenneth Casso... | use a virtual regfile port for the hazard bitvectors |
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2021-11-16 |
Luke Kenneth Casso... | create set/get ports for bitvectors |
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2021-11-16 |
Luke Kenneth Casso... | capture write port (wrflag) in byregfiles_spec for... |
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2021-11-16 |
Luke Kenneth Casso... | rename regports for bitvectors so that |
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2021-11-16 |
Luke Kenneth Casso... | starting to get write-clear of hazard vectors operating |
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2021-11-13 |
Luke Kenneth Casso... | start adding hazard vector setting in core (unfinished) |
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2021-11-11 |
Luke Kenneth Casso... | debug prints |
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2021-11-11 |
Luke Kenneth Casso... | fix regfile port names for "fast" port access (regreduc... |
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2021-11-11 |
Luke Kenneth Casso... | code-comments |
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2021-11-11 |
Luke Kenneth Casso... | split out core input/output into separate file core_data.py |
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2021-11-11 |
Luke Kenneth Casso... | enable hazard vecs in core |
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2021-11-11 |
Luke Kenneth Casso... | invert numbering on CR HDLState.get_crregs |
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2021-11-10 |
Luke Kenneth Casso... | update store data reg 10 to 0xfe in virtmode mmu test |
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2021-11-10 |
Luke Kenneth Casso... | allow MSR to be set in StateRegs in test_core.py |
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2021-11-10 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-10 |
Tobias Platen | test testcase for exception |
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2021-11-10 |
Luke Kenneth Casso... | make core busy_o part of the CoreOutput data structure |
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2021-11-10 |
Luke Kenneth Casso... | add a "fu_found" signal to core, which allows for an... |
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2021-11-09 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-09 |
Tobias Platen | test_issuer_mmu.py: add case_5_allsprs |
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2021-11-09 |
Luke Kenneth Casso... | add core instruction-issue PriorityPickers |
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2021-11-09 |
Luke Kenneth Casso... | comments |
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2021-11-09 |
Luke Kenneth Casso... | core.py: create a dictionary of lists of Function Units... |
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2021-11-09 |
Luke Kenneth Casso... | create function core conect_satellite_decoders |
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2021-11-08 |
Luke Kenneth Casso... | shorter way of getting FU busy signals |
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2021-11-08 |
Luke Kenneth Casso... | MultiCompUnit fixed to not need rdmask to be sustained... |
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2021-11-08 |
Tobias Platen | mmu unit test working again |
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2021-11-08 |
Luke Kenneth Casso... | remove unused variable |
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2021-11-08 |
Luke Kenneth Casso... | code comments |
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2021-11-08 |
Luke Kenneth Casso... | comments |
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2021-11-08 |
Luke Kenneth Casso... | remove issue_i from core, use i_valid instead to decide... |
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2021-11-08 |
Luke Kenneth Casso... | move "exception happened" detection from TestIssuer... |
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2021-11-08 |
Luke Kenneth Casso... | use p.i_valid in core instead of explicit signal ivalid_i |
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2021-11-08 |
Luke Kenneth Casso... | use Pipeline API o_ready instead of explicit core busy_... |
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2021-11-08 |
Luke Kenneth Casso... | convert core.py to Pipeline API, deriving from ControlBase |
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2021-11-08 |
Luke Kenneth Casso... | move simple core input and output data to in/out data... |
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2021-11-07 |
Luke Kenneth Casso... | for some reason mul test cases had not been added to... |
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2021-11-06 |
Tobias Platen | update test_issuer_mmu.py testcase, add needed debug... |
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2021-11-05 |
Tobias Platen | tlbie, mtspr and mfspr test cases |
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2021-11-05 |
Tobias Platen | add mmu/dcache unit test |
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