2020-08-27 |
Luke Kenneth Casso... | need to read SO if Rc=1 |
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2020-08-27 |
Luke Kenneth Casso... | reorg of SO handling related to CR0 |
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2020-08-26 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-26 |
Cole Poirier | dcache.py replace subtypes/types/constant aliases with... |
tree | commitdiff |
2020-08-26 |
Luke Kenneth Casso... | use sub-test in logical test_pipe_caller |
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2020-08-26 |
Luke Kenneth Casso... | investigating div fsm and simulator bug |
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2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-25 |
Cole Poirier | dcache.py rearrange, transform classes into functions... |
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2020-08-25 |
Jacob Lifshay | fix broken remainder for div FSM |
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2020-08-25 |
Jacob Lifshay | clean up formatting |
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2020-08-25 |
Luke Kenneth Casso... | although shift-rot does not alter XER.so it still needs... |
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2020-08-25 |
Luke Kenneth Casso... | add way to capture CR from DMI in litex sim |
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2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
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2020-08-25 |
Luke Kenneth Casso... | shorten using temp vars |
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2020-08-25 |
Luke Kenneth Casso... | add CR DMI interface |
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2020-08-25 |
Luke Kenneth Casso... | add crxor unit test to qemu |
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2020-08-25 |
Cole Poirier | dcache.py fix whitespace, fomatting, syntax |
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2020-08-25 |
Cole Poirier | dcache.py fix formatting |
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2020-08-25 |
Cole Poirier | dcache.py move Reservation RecordObject to top of file |
tree | commitdiff |
2020-08-25 |
Cole Poirier | dcache.py move RegStage1 RecordObject to top of file |
tree | commitdiff |
2020-08-25 |
Cole Poirier | dcache.py move MemAccessRequest RecordObject to top... |
tree | commitdiff |
2020-08-25 |
Cole Poirier | dcache.py move Stage0 RecordObject to top of file |
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2020-08-24 |
Luke Kenneth Casso... | argh, reading regfile over DMI was overlapped and corru... |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | add isel CR tests to run on qemu (confirmed working) |
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2020-08-24 |
Tobias Platen | TestCachedMemoryPortInterface cleanup |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | make it easier to select FSM/Pipe DIV unit |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | fix *another* ld-update-related timing / FSM issue |
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2020-08-24 |
Luke Kenneth Casso... | tidyup / shuffle after review |
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2020-08-24 |
Luke Kenneth Casso... | remove default parameter |
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2020-08-24 |
Luke Kenneth Casso... | "WAY" does not exist - range(NUM_WAYS) was intended |
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2020-08-24 |
Luke Kenneth Casso... | use WAY_BITS in appropriate locations |
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2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-24 |
Cole Poirier | dcache.py commit first full tranlation pass, about... |
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2020-08-23 |
Luke Kenneth Casso... | update copyright notices to include additional primary... |
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2020-08-23 |
Luke Kenneth Casso... | add load algebraic immediate unit test |
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2020-08-23 |
Luke Kenneth Casso... | add algebraic ld tests lwax, lwaux |
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2020-08-23 |
Michael Nolan | Add copyright to files I primarily authored in simulator/ |
tree | commitdiff |
2020-08-23 |
Michael Nolan | Add copyright to files in fu/ that I was the primary... |
tree | commitdiff |
2020-08-23 |
Michael Nolan | Add copyright statement to power_decoder.py |
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2020-08-23 |
Luke Kenneth Casso... | bring "core stopped" signal out through DMI interface |
tree | commitdiff |
2020-08-23 |
Luke Kenneth Casso... | add in DMI "stat" loop which monitors core "stopping" |
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2020-08-23 |
Cesar Strauss | Allow an empty style, and passing default styles as... |
tree | commitdiff |
2020-08-23 |
Cesar Strauss | Add comment node type |
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2020-08-23 |
Cesar Strauss | Add base and display styles |
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2020-08-23 |
Cesar Strauss | Apply style from node own name |
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2020-08-23 |
Cesar Strauss | Add color style |
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2020-08-23 |
Cesar Strauss | Collect styles from the tuple |
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2020-08-23 |
Cesar Strauss | Propagate the root style to all signals |
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2020-08-23 |
Luke Kenneth Casso... | comment why litex sim mem map is altered |
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2020-08-23 |
Luke Kenneth Casso... | multiply does not have invert_in, zero_a or invert_out |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | rename invert_a to invert_in because logical inverts RB |
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2020-08-22 |
Luke Kenneth Casso... | load bios not 1.bin unit test |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add extra div regression tests |
tree | commitdiff |
2020-08-22 |
Cesar Strauss | Move comments to the docstring |
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2020-08-22 |
Cesar Strauss | Walk the DOM and emit the trace names |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add eqv to logical unit test |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add nor and nand to unit test |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | moved to div pipe temporarily in compunits |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | bug in andc and orc, complement was taking place on... |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | extend addis test |
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2020-08-22 |
Luke Kenneth Casso... | add andc and orc tests, failing because RB needs invers... |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi... |
tree | commitdiff |
2020-08-22 |
Cesar Strauss | First draft of a mini-language to describe GTKWave... |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add regression test for nonzero addis |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add means to run microwatt test binaries |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | r0 zero tests on addis, fails |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | investigating litex sdrinit function |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add pseudo-op conversion |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add start of litex bios counter loop |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | remove extraneous comments |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | testing 64-bit wishbone bus after 32-bit *still* fails... |
tree | commitdiff |
2020-08-21 |
Tobias Platen | typo fix in test_l0_cache_buffer2.py |
tree | commitdiff |
2020-08-21 |
Cole Poirier | dcache.py fix asserts, use backslash and two strings... |
tree | commitdiff |
2020-08-21 |
Cole Poirier | dcache.py replace functions that return signals with... |
tree | commitdiff |
2020-08-21 |
Cole Poirier | wb_types fix typo |
tree | commitdiff |
2020-08-21 |
Tobias Platen | connect TestCachedMemoryPortInterface to LDSTSplitter |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | get litex sim enabled with 32-bit wishbone bus |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | ld/st bus reduction test operational |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | first test of down-converted load/store from 64 to... |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | first test of down-converted load/store from 64 to... |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | add in WishboneDownConvert into LoadStoreUnitInterface |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | comment formatting |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | remove default values |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | just range(the_constant) |
tree | commitdiff |
2020-08-21 |
Samuel A. Falvo II | MUL pipeline WIP: mullw and mullwu covered. |
tree | commitdiff |
2020-08-21 |
Samuel A. Falvo II | MUL pipeline: account for overflow flags. WIP |
tree | commitdiff |
2020-08-21 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-21 |
Cole Poirier | dcache.py commit today and yesterday's progress (sorry... |
tree | commitdiff |
2020-08-21 |
Samuel A. Falvo II | MUL pipeline proofs: mulli / mullw WIP. |
tree | commitdiff |
2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: muldw(u) |
tree | commitdiff |
2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: signed mulhw |
tree | commitdiff |
2020-08-20 |
Tobias Platen | start wiring TestCachedMemoryPortInterface |
tree | commitdiff |
2020-08-20 |
Tobias Platen | testcase refactoring |
tree | commitdiff |
2020-08-20 |
Tobias Platen | add new class TestCachedMemoryPortInterface |
tree | commitdiff |
2020-08-20 |
Luke Kenneth Casso... | bugfix wishbone downconvert using wb sram 64-to-32... |
tree | commitdiff |
2020-08-20 |
Luke Kenneth Casso... | add a wishbone upconverter |
tree | commitdiff |
2020-08-19 |
Luke Kenneth Casso... | rename and document fields in shift_rot proof |
tree | commitdiff |
2020-08-19 |
Luke Kenneth Casso... | comments in dcache |
tree | commitdiff |
2020-08-19 |
Luke Kenneth Casso... | more subtle interactions between wishbone bus when... |
tree | commitdiff |
2020-08-19 |
Luke Kenneth Casso... | bit of a reorg of mul proof, tracking down missing |
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