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[soc.git] / src / soc /
2020-07-04 Luke Kenneth Casso... whitespace
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... rename spr1/spr2 to fast1/fast2 in branch
2020-07-04 Luke Kenneth Casso... update trap docstring
2020-07-04 Luke Kenneth Casso... use new consts module
2020-07-04 Luke Kenneth Casso... sorting out trap fastregs
2020-07-04 Luke Kenneth Casso... sort out trap test reg checking
2020-07-04 Luke Kenneth Casso... resolve spr names in ISACaller
2020-07-04 Luke Kenneth Casso... rename spr1 to fast1 in trap data
2020-07-04 Luke Kenneth Casso... sorting out fast/spr naming
2020-07-04 Luke Kenneth Casso... oops initialise Function Unit class with idx
2020-07-04 Luke Kenneth Casso... add first cookie-cut test_trap_compunit.py
2020-07-04 Luke Kenneth Casso... add gitignores
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage
2020-07-04 Luke Kenneth Casso... add spr input record
2020-07-04 Luke Kenneth Casso... add SPR pipeline
2020-07-04 Luke Kenneth Casso... reduce steps per stage to 8
2020-07-03 Luke Kenneth Casso... set only div/rem supported
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... use Mock class (more convenient)
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... name function unit ALUs
2020-07-02 Luke Kenneth Casso... comment out DIV unit for now
2020-07-02 Luke Kenneth Casso... increase combinatorial stages to 8
2020-07-02 Luke Kenneth Casso... reduce DIV radix to 1
2020-07-02 Luke Kenneth Casso... add DIV function unit to compunits
2020-07-02 Luke Kenneth Casso... add trap function unit into compunits
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-07-02 Cesar StraussPresent the ALU result only when valid_o is active
2020-07-01 Luke Kenneth Casso... whoops missed some cases in unit test changing ALUHelpers
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-07-01 Luke Kenneth Casso... whoops swapped trap test instructions accidentally
2020-07-01 Luke Kenneth Casso... print out msr for debug
2020-07-01 Luke Kenneth Casso... attempting to add SPRs to rfid test
2020-07-01 Luke Kenneth Casso... add OP_SC
2020-07-01 Luke Kenneth Casso... trap test check results
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion
2020-07-01 Luke Kenneth Casso... add in trap compunit
2020-07-01 Luke Kenneth Casso... add rfid and td/tw trap test
2020-07-01 Luke Kenneth Casso... continue debugging trap pipeline
2020-07-01 Luke Kenneth Casso... debugging trap pipeline
2020-07-01 Luke Kenneth Casso... start running trap unit test, fixing errors
2020-06-30 Luke Kenneth Casso... add lte ltu for use by twi and other trap functions
2020-06-30 Luke Kenneth Casso... add in pseudocode keyword into mdwn isa files
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... add README for fu directory
2020-06-29 Luke Kenneth Casso... use correct ALUHelpers in div test
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-29 Luke Kenneth Casso... first unit test for div
2020-06-29 Luke Kenneth Casso... add ignore for parsetab.py
2020-06-29 Luke Kenneth Casso... add autogenerated do not commit comment
2020-06-29 Luke Kenneth Casso... separate out divide by zero cases
2020-06-29 Luke Kenneth Casso... update OV and OV32 ISACaller flags if overflow occurs
2020-06-29 Luke Kenneth Casso... attempting to add overflow setting in ISACaller
2020-06-29 Luke Kenneth Casso... whoops, hex parser digits are in multiples of 4 bits
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Luke Kenneth Casso... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth Casso... add test instruction memory
2020-06-28 Luke Kenneth Casso... add readonly option to TestMemory
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-28 Luke Kenneth Casso... parameterise minerva i-cache
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs
2020-06-28 Luke Kenneth Casso... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth Casso... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... name issue in Pi2LSUI
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth Casso... correct address in pi2ls
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