2020-12-31 |
Cesar Strauss | Add sign extend to the Test ALU |
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2020-12-31 |
Cesar Strauss | Show rdmaskn and wrmask in GTKWave |
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2020-12-31 |
Cesar Strauss | Use the increment operator |
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2020-12-31 |
Cesar Strauss | Add support for masked write operations |
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2020-12-31 |
Cesar Strauss | Clarify reason for holding rdmaskn valid during the... |
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2020-12-31 |
Cesar Strauss | Remove previous version of the CompUnit parallel unit... |
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2020-12-31 |
Cesar Strauss | Only hold the decoder signals for one cycle, along... |
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2020-12-30 |
Cesar Strauss | Test the rdmaskn control signal |
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2020-12-29 |
Cesar Strauss | Remove left-over comments. |
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2020-12-28 |
Luke Kenneth Casso... | add CR1 to power_enums |
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2020-12-20 |
Cesar Strauss | Add support for CXXSim simulation |
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2020-12-13 |
Cesar Strauss | Ignore formal verification output in the source directory |
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2020-12-13 |
Cesar Strauss | Allow more test cases to be run with CXXSim |
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2020-12-12 |
Luke Kenneth Casso... | skip madd, not implemented |
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2020-12-07 |
Cesar Strauss | Display the instruction type as a vector on cxxsim |
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2020-12-06 |
Luke Kenneth Casso... | attempt to split into two separate GPIO banks due to... |
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2020-12-06 |
Cesar Strauss | Whitespace |
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2020-12-06 |
Cesar Strauss | Update GTKWave documents to work with latest cxxsim |
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2020-12-05 |
Cesar Strauss | Write a GTKWave document to investigate why the proof... |
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2020-12-05 |
Cesar Strauss | Use the DummyALU regspec and its corresponding OpSubset |
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2020-12-03 |
Luke Kenneth Casso... | put ls180 litex bus width back to 32 bit temporarily |
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2020-12-03 |
Luke Kenneth Casso... | argh issue with yosys ABC |
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2020-12-03 |
Luke Kenneth Casso... | add 3 more 4k SRAMs, change WB bus width to 64 in ls180... |
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2020-11-28 |
Cesar Strauss | Fix signal names: go/rel -> go_i/rel_o |
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2020-11-24 |
Cesar Strauss | Fix some typos and whitespace |
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2020-11-24 |
Cesar Strauss | Port the DummyALU test case to the new parallel issuer |
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2020-11-23 |
Cesar Strauss | Results are now a list, so "expected" should follow... |
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2020-11-23 |
Cesar Strauss | Parameterize the issuer on the number of operands and... |
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2020-11-22 |
Cesar Strauss | Refactor the ALU operation issuer into a class |
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2020-11-22 |
Cesar Strauss | Port the ALU test case to the new parallel test style |
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2020-11-22 |
Cesar Strauss | Add a GTKWave document to the ALU test case |
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2020-11-22 |
Luke Kenneth Casso... | simplify litex-core wishbone interfaces |
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2020-11-19 |
Cesar Strauss | Separate input and output ports by color |
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2020-11-19 |
Cesar Strauss | Explain the test cases |
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2020-11-18 |
Cesar Strauss | Separate individual traces for each rel_o/go_i port |
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2020-11-17 |
Tobias Platen | testcase for dcbz |
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2020-11-16 |
Cesar Strauss | Add a transaction counter to producers and consumers |
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2020-11-16 |
Tobias Platen | add class LoadStore1(PortInterfaceBase) |
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2020-11-15 |
Cesar Strauss | Implement ResultConsumer and port the Shifter unit... |
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2020-11-14 |
Cesar Strauss | Move the DUT driver to within the test case process |
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2020-11-14 |
Cesar Strauss | Fix and enable the regspec test for the Shifter |
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2020-11-14 |
Luke Kenneth Casso... | sigh, direction wrong in IOtypes litex core |
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2020-11-13 |
Luke Kenneth Casso... | reduce number of nc in ls180 to 24 |
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2020-11-13 |
Luke Kenneth Casso... | reduce clkcsel ls180 width (2 pins), rename pll_18... |
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2020-11-13 |
Luke Kenneth Casso... | rename and add pll lock signal to ls180 |
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2020-11-13 |
Luke Kenneth Casso... | rename ls180 litex pll_48 output to pll_18 |
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2020-11-13 |
Luke Kenneth Casso... | add enable/disable arguments (not ideal but it works... |
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2020-11-13 |
Luke Kenneth Casso... | remove io_in/out now it is not needed for niolib |
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2020-11-11 |
Tobias Platen | dcbz and tlbie first test, still incomplete |
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2020-11-11 |
Tobias Platen | fu/mmu/test/test_pipe_caller.py test case for mfspr |
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2020-11-10 |
Luke Kenneth Casso... | add build commands to Makefile for versa ecp5 |
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2020-11-10 |
Luke Kenneth Casso... | remove ClockSelect module, use DummyPLL |
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2020-11-10 |
Luke Kenneth Casso... | add separate DummyPLL module, according to API discussed at |
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2020-11-08 |
Tobias Platen | mmu fsm testcase: add check_fsm_outputs based on functi... |
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2020-11-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-11-08 |
Tobias Platen | mmu/fsm: test case for mtspr |
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2020-11-07 |
Tobias Platen | fixed a bug in src/soc/fu/mmu/fsm.py |
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2020-11-06 |
Luke Kenneth Casso... | sigh sorting out litex pin-connections to sdram |
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2020-11-04 |
Luke Kenneth Casso... | move back to 3.3v on X3 VERSA ECP5 connector |
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2020-11-04 |
Tobias Platen | MMU: begin test case for 'dcbz' |
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2020-11-03 |
Tobias Platen | fix broken unittest after installing power-instruction... |
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2020-11-03 |
Luke Kenneth Casso... | swap jtag pinorder to match ulx3s |
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2020-11-03 |
Luke Kenneth Casso... | change LVCMOS level on versa ecp5 jtag to 2.5v |
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2020-11-01 |
Cesar Strauss | Add a check for liveness. |
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2020-10-31 |
Cole Poirier | versa_ecp5.py add 4 arbitrarily assigned gpio pins... |
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2020-10-31 |
Cesar Strauss | Check that the read and write counters differ at most... |
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2020-10-31 |
Cesar Strauss | Remove stray comment |
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2020-10-30 |
Luke Kenneth Casso... | add JTAG extension to versa_ecp5 then we can use it |
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2020-10-28 |
Cesar Strauss | Implement an operand producer that talks the rel_o... |
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2020-10-24 |
Cesar Strauss | Create a GTKWave document for the test ALU unit tests |
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2020-10-22 |
Luke Kenneth Casso... | add query about cross-domain on the JTAG enable of WB |
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2020-10-22 |
Luke Kenneth Casso... | add detection and disable of Instruction Wishbone based... |
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2020-10-22 |
Luke Kenneth Casso... | add detection and disable of LoadStore Wishbone based... |
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2020-10-22 |
Luke Kenneth Casso... | add JTAG enable/disable of wishbone to TestIssuer |
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2020-10-22 |
Luke Kenneth Casso... | add means to JTAG interface to enable/disable "stuff... |
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2020-10-21 |
Cole Poirier | versa_ecp5 adds ability to build and load for ulx3s85f... |
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2020-10-21 |
Luke Kenneth Casso... | fix up asserts (check correct pads/cores) |
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2020-10-20 |
Tobias Platen | s/alu/fsm/g |
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2020-10-20 |
Tobias Platen | test case for FSMMMUStage |
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2020-10-18 |
Cole Poirier | use random.seed to generate repro cases of the two... |
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2020-10-16 |
Luke Kenneth Casso... | experiment swapping dummy trap stage over to input |
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2020-10-16 |
Luke Kenneth Casso... | re-enable tests |
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2020-10-16 |
Luke Kenneth Casso... | manually run coresync clock for test issuer |
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2020-10-16 |
Luke Kenneth Casso... | set defaults in pspec |
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2020-10-16 |
Luke Kenneth Casso... | add extra (test dummy stage in trap to see if combinato... |
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2020-10-16 |
Luke Kenneth Casso... | add LGPLv3+ notice and add copyright holders |
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2020-10-15 |
Luke Kenneth Casso... | add commented-out connection to JTAG in ECP5 litex |
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2020-10-15 |
Luke Kenneth Casso... | wrong pspec variable in selecting pll clock |
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2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
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2020-10-15 |
Luke Kenneth Casso... | use "enable" and set default actions in getopt |
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2020-10-15 |
Luke Kenneth Casso... | add extra variant to litex core |
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2020-10-15 |
Luke Kenneth Casso... | syntax error |
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2020-10-15 |
Luke Kenneth Casso... | disable gpio in litex core |
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2020-10-15 |
Luke Kenneth Casso... | enable/disable litex irqs based on variant name |
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2020-10-14 |
Cole Poirier | issuer_verilog.py update to use commandline args using... |
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2020-10-12 |
Cole Poirier | litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5... |
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2020-10-12 |
Cole Poirier | fix ModuleNotFound/Import errors found when running... |
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2020-10-12 |
Cole Poirier | add tested working fpga compile/build/load file for... |
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2020-10-11 |
Luke Kenneth Casso... | add way to bypass PLL for ECP5 and sim |
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2020-10-11 |
Luke Kenneth Casso... | comment out XICS/GPIO interrupt test, causes ECP5 litex... |
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