Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src /
2020-05-27 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-27 Tobias Platenelaborate function for DataMerger
2020-05-27 Cesar StraussRemove the monitor process
2020-05-27 Luke Kenneth Casso... make power function unit enum bitmasked
2020-05-27 Luke Kenneth Casso... add extra INT regs port for now, add Fast Regfile
2020-05-27 Luke Kenneth Casso... added XER and CR regfiles, using new VirtualRegPort
2020-05-26 Luke Kenneth Casso... check assertions
2020-05-26 Luke Kenneth Casso... make read/write regs properly internal
2020-05-26 Luke Kenneth Casso... add VirtualRegPort test, seems to demonstrate it working
2020-05-26 Luke Kenneth Casso... remove sync (not needed)
2020-05-26 Luke Kenneth Casso... get score6600_multi.py working again
2020-05-26 Luke Kenneth Casso... redo focus of virtual reg port to do only full datawidt...
2020-05-26 Michael NolanAdd extras from bottom of the file
2020-05-26 Michael NolanRewrite proof to be more in line with what appears...
2020-05-26 Luke Kenneth Casso... sort-of (maybe) implemented a virtual port on top of...
2020-05-26 Luke Kenneth Casso... try new variant of VirtualRegFile
2020-05-26 Luke Kenneth Casso... use nmutil treereduce
2020-05-26 Luke Kenneth Casso... continue virtual regfile port
2020-05-26 Luke Kenneth Casso... whitespace, add commentary
2020-05-26 colepoirierFirst attempt at implementing block access rd and wr...
2020-05-25 Cesar StraussCheck that busy_o doesn't rise on its own
2020-05-25 Cesar StraussImplement the issue_i/busy_o protocol check.
2020-05-25 Cesar StraussMove process list to CompUnitParallelTest
2020-05-25 Michael NolanCorrect polarity of shadow signal
2020-05-25 Luke Kenneth Casso... document shadown inversion
2020-05-25 Michael NolanAdd link to compunit wiki page
2020-05-25 Michael NolanCorrect property numbers, add assertions about busy
2020-05-25 Luke Kenneth Casso... update comments on compalu_multi.py
2020-05-25 Michael NolanAdd assertions about go_wr and wr_rel
2020-05-25 Michael NolanMinor cleanup of comments
2020-05-25 Michael NolanMinor changes to alu_hier.py to allow it to be used...
2020-05-25 Michael NolanBegin working on proof for compunit/fu
2020-05-25 Luke Kenneth Casso... add some more stub comments
2020-05-25 Luke Kenneth Casso... yield blank so test passes
2020-05-25 Luke Kenneth Casso... add stubs
2020-05-25 Luke Kenneth Casso... add comments
2020-05-25 Cesar StraussFix detection of busy_o inside the monitor process
2020-05-25 Cesar StraussProof of concept of a parallel test
2020-05-25 Tobias Platenfix own copy/paste error
2020-05-25 Tobias Platenwhitespace fix in docstring
2020-05-25 Luke Kenneth Casso... correct links in regfile docstring
2020-05-25 Luke Kenneth Casso... document regfiles
2020-05-25 Luke Kenneth Casso... argh! frickin MACos terminal expanded out to 86x30...
2020-05-25 Luke Kenneth Casso... add docstring
2020-05-25 Luke Kenneth Casso... add INT, SPR and CR regfiles
2020-05-25 Tobias Platenrefactoring (see #216 Comment 43)
2020-05-25 Tobias Platenwhitespace changes
2020-05-25 Luke Kenneth Casso... quick addition of zero+immed test to LDSTCompUnit
2020-05-25 Luke Kenneth Casso... must not do rd-req checking when both imm and zero...
2020-05-25 Tobias Platenimplement DataMerger interface
2020-05-25 Luke Kenneth Casso... add zero immed on LDST, untested
2020-05-25 Luke Kenneth Casso... comment out invalid test
2020-05-25 Luke Kenneth Casso... lots of greater than 80 chars
2020-05-25 Luke Kenneth Casso... switch out req rel if immediate enabled
2020-05-25 Cesar StraussShow oper_r and oper_i in the signal list, in simulation
2020-05-25 Luke Kenneth Casso... mention zeroing
2020-05-25 Luke Kenneth Casso... add links to pseudocode
2020-05-24 Luke Kenneth Casso... spelling
2020-05-24 Luke Kenneth Casso... spelling
2020-05-24 Luke Kenneth Casso... add comments for SPR pipe_data
2020-05-24 Luke Kenneth Casso... add SPR pipe_data.py
2020-05-24 Luke Kenneth Casso... over 80 char limit
2020-05-24 Luke Kenneth Casso... add test of reg output, for MFCRF and ISEL
2020-05-24 Cesar StraussAvoid overwriting the first vcd file with the second one
2020-05-24 Cesar StraussRename the internal DFF of latchregisters to avoid...
2020-05-24 Luke Kenneth Casso... add gitignore for branch fu formal
2020-05-24 Luke Kenneth Casso... add OP_CMPB formal proof
2020-05-24 Michael NolanAssert that ctr is only written when needed
2020-05-24 Luke Kenneth Casso... split out Popcount into separate module: visually it...
2020-05-24 Luke Kenneth Casso... copy code for MTMSR from microwatt into comments
2020-05-24 Luke Kenneth Casso... add links for trap main stage
2020-05-24 Luke Kenneth Casso... add untested OP_MTMSR and OP_MFMSR
2020-05-24 Luke Kenneth Casso... add MFMSR and MTMSRD enums to Function
2020-05-24 Luke Kenneth Casso... comment and add links to branch formal proof
2020-05-24 Luke Kenneth Casso... add copy of bpermd proof to logical formal proof (not...
2020-05-24 Luke Kenneth Casso... track down overwrite of variable b
2020-05-24 Michael NolanFix proof of bpermd module
2020-05-24 Michael NolanFix bpermd and make tests pass
2020-05-24 Michael NolanFix test_pipe_caller to conform to new Data() interface...
2020-05-24 Luke Kenneth Casso... add stub regfiles.py
2020-05-24 Luke Kenneth Casso... hmm...
2020-05-24 Luke Kenneth Casso... add very rapid DummyALU for test purposes in MultiCompUnit
2020-05-24 Luke Kenneth Casso... comments on branch pipeline
2020-05-24 Luke Kenneth Casso... convert CR pipeline to Data.ok
2020-05-24 Luke Kenneth Casso... convert ALU to output Data on int reg
2020-05-24 Luke Kenneth Casso... convert logical to output Data on int reg
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-24 Luke Kenneth Casso... cleanup/code-munge on ALU main stage proof
2020-05-24 Luke Kenneth Casso... error in alu output stage formal proof setup
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-24 Luke Kenneth Casso... spelling mistake in variable
2020-05-24 Luke Kenneth Casso... TODO mention OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth Casso... add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth Casso... move docstring to wiki for compunit
2020-05-23 colepoirierAdded branch and shift_rot imports to fu/compunits...
2020-05-23 Cesar StraussAdd a few test cases with zero_a set, in combination...
2020-05-23 Cesar StraussAllow zero_a to be set when simulating an operation
2020-05-23 Luke Kenneth Casso... add input / output stage missing modules
2020-05-23 Luke Kenneth Casso... common function for op zero and op immed
2020-05-23 Cesar StraussChoose between RA (src1) and zero immediate, conditione...
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