2020-05-27 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-27 |
Tobias Platen | elaborate function for DataMerger |
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2020-05-27 |
Cesar Strauss | Remove the monitor process |
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2020-05-27 |
Luke Kenneth Casso... | make power function unit enum bitmasked |
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2020-05-27 |
Luke Kenneth Casso... | add extra INT regs port for now, add Fast Regfile |
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2020-05-27 |
Luke Kenneth Casso... | added XER and CR regfiles, using new VirtualRegPort |
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2020-05-26 |
Luke Kenneth Casso... | check assertions |
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2020-05-26 |
Luke Kenneth Casso... | make read/write regs properly internal |
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2020-05-26 |
Luke Kenneth Casso... | add VirtualRegPort test, seems to demonstrate it working |
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2020-05-26 |
Luke Kenneth Casso... | remove sync (not needed) |
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2020-05-26 |
Luke Kenneth Casso... | get score6600_multi.py working again |
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2020-05-26 |
Luke Kenneth Casso... | redo focus of virtual reg port to do only full datawidt... |
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2020-05-26 |
Michael Nolan | Add extras from bottom of the file |
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2020-05-26 |
Michael Nolan | Rewrite proof to be more in line with what appears... |
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2020-05-26 |
Luke Kenneth Casso... | sort-of (maybe) implemented a virtual port on top of... |
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2020-05-26 |
Luke Kenneth Casso... | try new variant of VirtualRegFile |
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2020-05-26 |
Luke Kenneth Casso... | use nmutil treereduce |
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2020-05-26 |
Luke Kenneth Casso... | continue virtual regfile port |
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2020-05-26 |
Luke Kenneth Casso... | whitespace, add commentary |
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2020-05-26 |
colepoirier | First attempt at implementing block access rd and wr... |
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2020-05-25 |
Cesar Strauss | Check that busy_o doesn't rise on its own |
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2020-05-25 |
Cesar Strauss | Implement the issue_i/busy_o protocol check. |
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2020-05-25 |
Cesar Strauss | Move process list to CompUnitParallelTest |
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2020-05-25 |
Michael Nolan | Correct polarity of shadow signal |
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2020-05-25 |
Luke Kenneth Casso... | document shadown inversion |
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2020-05-25 |
Michael Nolan | Add link to compunit wiki page |
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2020-05-25 |
Michael Nolan | Correct property numbers, add assertions about busy |
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2020-05-25 |
Luke Kenneth Casso... | update comments on compalu_multi.py |
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2020-05-25 |
Michael Nolan | Add assertions about go_wr and wr_rel |
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2020-05-25 |
Michael Nolan | Minor cleanup of comments |
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2020-05-25 |
Michael Nolan | Minor changes to alu_hier.py to allow it to be used... |
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2020-05-25 |
Michael Nolan | Begin working on proof for compunit/fu |
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2020-05-25 |
Luke Kenneth Casso... | add some more stub comments |
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2020-05-25 |
Luke Kenneth Casso... | yield blank so test passes |
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2020-05-25 |
Luke Kenneth Casso... | add stubs |
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2020-05-25 |
Luke Kenneth Casso... | add comments |
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2020-05-25 |
Cesar Strauss | Fix detection of busy_o inside the monitor process |
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2020-05-25 |
Cesar Strauss | Proof of concept of a parallel test |
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2020-05-25 |
Tobias Platen | fix own copy/paste error |
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2020-05-25 |
Tobias Platen | whitespace fix in docstring |
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2020-05-25 |
Luke Kenneth Casso... | correct links in regfile docstring |
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2020-05-25 |
Luke Kenneth Casso... | document regfiles |
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2020-05-25 |
Luke Kenneth Casso... | argh! frickin MACos terminal expanded out to 86x30... |
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2020-05-25 |
Luke Kenneth Casso... | add docstring |
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2020-05-25 |
Luke Kenneth Casso... | add INT, SPR and CR regfiles |
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2020-05-25 |
Tobias Platen | refactoring (see #216 Comment 43) |
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2020-05-25 |
Tobias Platen | whitespace changes |
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2020-05-25 |
Luke Kenneth Casso... | quick addition of zero+immed test to LDSTCompUnit |
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2020-05-25 |
Luke Kenneth Casso... | must not do rd-req checking when both imm and zero... |
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2020-05-25 |
Tobias Platen | implement DataMerger interface |
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2020-05-25 |
Luke Kenneth Casso... | add zero immed on LDST, untested |
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2020-05-25 |
Luke Kenneth Casso... | comment out invalid test |
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2020-05-25 |
Luke Kenneth Casso... | lots of greater than 80 chars |
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2020-05-25 |
Luke Kenneth Casso... | switch out req rel if immediate enabled |
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2020-05-25 |
Cesar Strauss | Show oper_r and oper_i in the signal list, in simulation |
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2020-05-25 |
Luke Kenneth Casso... | mention zeroing |
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2020-05-25 |
Luke Kenneth Casso... | add links to pseudocode |
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2020-05-24 |
Luke Kenneth Casso... | spelling |
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2020-05-24 |
Luke Kenneth Casso... | spelling |
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2020-05-24 |
Luke Kenneth Casso... | add comments for SPR pipe_data |
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2020-05-24 |
Luke Kenneth Casso... | add SPR pipe_data.py |
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2020-05-24 |
Luke Kenneth Casso... | over 80 char limit |
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2020-05-24 |
Luke Kenneth Casso... | add test of reg output, for MFCRF and ISEL |
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2020-05-24 |
Cesar Strauss | Avoid overwriting the first vcd file with the second one |
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2020-05-24 |
Cesar Strauss | Rename the internal DFF of latchregisters to avoid... |
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2020-05-24 |
Luke Kenneth Casso... | add gitignore for branch fu formal |
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2020-05-24 |
Luke Kenneth Casso... | add OP_CMPB formal proof |
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2020-05-24 |
Michael Nolan | Assert that ctr is only written when needed |
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2020-05-24 |
Luke Kenneth Casso... | split out Popcount into separate module: visually it... |
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2020-05-24 |
Luke Kenneth Casso... | copy code for MTMSR from microwatt into comments |
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2020-05-24 |
Luke Kenneth Casso... | add links for trap main stage |
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2020-05-24 |
Luke Kenneth Casso... | add untested OP_MTMSR and OP_MFMSR |
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2020-05-24 |
Luke Kenneth Casso... | add MFMSR and MTMSRD enums to Function |
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2020-05-24 |
Luke Kenneth Casso... | comment and add links to branch formal proof |
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2020-05-24 |
Luke Kenneth Casso... | add copy of bpermd proof to logical formal proof (not... |
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2020-05-24 |
Luke Kenneth Casso... | track down overwrite of variable b |
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2020-05-24 |
Michael Nolan | Fix proof of bpermd module |
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2020-05-24 |
Michael Nolan | Fix bpermd and make tests pass |
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2020-05-24 |
Michael Nolan | Fix test_pipe_caller to conform to new Data() interface... |
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2020-05-24 |
Luke Kenneth Casso... | add stub regfiles.py |
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2020-05-24 |
Luke Kenneth Casso... | hmm... |
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2020-05-24 |
Luke Kenneth Casso... | add very rapid DummyALU for test purposes in MultiCompUnit |
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2020-05-24 |
Luke Kenneth Casso... | comments on branch pipeline |
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2020-05-24 |
Luke Kenneth Casso... | convert CR pipeline to Data.ok |
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2020-05-24 |
Luke Kenneth Casso... | convert ALU to output Data on int reg |
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2020-05-24 |
Luke Kenneth Casso... | convert logical to output Data on int reg |
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2020-05-24 |
Luke Kenneth Casso... | start using Data in pipelines |
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2020-05-24 |
Luke Kenneth Casso... | cleanup/code-munge on ALU main stage proof |
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2020-05-24 |
Luke Kenneth Casso... | error in alu output stage formal proof setup |
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2020-05-24 |
Luke Kenneth Casso... | output registers need to be Data type (consistently) |
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2020-05-24 |
Luke Kenneth Casso... | spelling mistake in variable |
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2020-05-24 |
Luke Kenneth Casso... | TODO mention OP_MTMSR/OP_MFMSR |
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2020-05-24 |
Luke Kenneth Casso... | add RA to trap pipeline, for OP_MTMSR/OP_MFMSR |
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2020-05-24 |
Luke Kenneth Casso... | move docstring to wiki for compunit |
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2020-05-23 |
colepoirier | Added branch and shift_rot imports to fu/compunits... |
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2020-05-23 |
Cesar Strauss | Add a few test cases with zero_a set, in combination... |
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2020-05-23 |
Cesar Strauss | Allow zero_a to be set when simulating an operation |
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2020-05-23 |
Luke Kenneth Casso... | add input / output stage missing modules |
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2020-05-23 |
Luke Kenneth Casso... | common function for op zero and op immed |
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2020-05-23 |
Cesar Strauss | Choose between RA (src1) and zero immediate, conditione... |
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