Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:16:12 +0000 (15:16 +0100)]
cleanup dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:05:37 +0000 (15:05 +0100)]
error using sync, should have been comb
Cesar Strauss [Wed, 21 Apr 2021 20:30:12 +0000 (17:30 -0300)]
Implement CR predication
Read the CR fields in a VL loop, building the masks bit by bit.
TODO: implement reentrancy, by shifting out already used mask bits.
Cesar Strauss [Wed, 21 Apr 2021 19:42:56 +0000 (16:42 -0300)]
CR sub-fields are stored in MSB0 order
Luke Kenneth Casson Leighton [Wed, 21 Apr 2021 19:50:54 +0000 (20:50 +0100)]
experimenting with dcache
Tobias Platen [Wed, 21 Apr 2021 18:48:38 +0000 (20:48 +0200)]
testcase: pass PRTBL to mmu
Cesar Strauss [Wed, 21 Apr 2021 17:43:57 +0000 (14:43 -0300)]
Add CR predication test case for TestIssuer
Directly derived from the corresponding case in
test_caller_svp64_predication.py
It is expected to fail, until CR predication is implemented on TestIssuer.
Cesar Strauss [Wed, 21 Apr 2021 17:22:55 +0000 (14:22 -0300)]
Fix comment in CR predication test case
The comment at the top of the test case was inconsistent with it:
"adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)"
The whole test is consistent with this (mask is NE and first element is
skipped).
The shift amount itself is also consistent with setting of CR4, not CR5.
Cesar Strauss [Wed, 21 Apr 2021 17:06:07 +0000 (14:06 -0300)]
Fix sense of "invert" signal
We want to put "1" in the mask, if the operation is to be performed.
The actual CR bits are: LT, GT, EQ and SO.
So, for those, we just copy the bit directly to the mask, as they are.
For GE, LE, NE and NS, we want to invert the bit first.
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 16:10:39 +0000 (17:10 +0100)]
add enable MMU option to issuer_verilog.py
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 15:57:52 +0000 (16:57 +0100)]
cannot pass in arguments to Core - must be done with pspec
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:37:24 +0000 (15:37 +0100)]
use soc.bus.sram instead of nmigen_soc.wishbone.sram
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:34:34 +0000 (15:34 +0100)]
add wishbone sram.py (move from nmigen-soc)
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 17:55:50 +0000 (18:55 +0100)]
give independent names to spblock512w64b8ws
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:42:48 +0000 (23:42 +0100)]
give spblock512 a name as a submodule
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:27:30 +0000 (21:27 +0100)]
create signal on test_issuer which gives PLL clk_sel_i a useful name
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:17:34 +0000 (21:17 +0100)]
rename SPBlock_512W64B8W to lowercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:40 +0000 (21:06 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:10 +0000 (21:06 +0100)]
rename PLL pins to match LIP6.fr PLL
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 19:01:43 +0000 (20:01 +0100)]
core_stopped_i unused: remove
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 18:26:26 +0000 (19:26 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 15:42:57 +0000 (16:42 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 12:21:19 +0000 (13:21 +0100)]
add pypi upload to Makefile
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 11:44:36 +0000 (12:44 +0100)]
add OS Independent classifier
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:18:59 +0000 (11:18 +0100)]
update README
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:09:43 +0000 (11:09 +0100)]
update setup.py to make it "safe" for uploading to pypi
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:27:39 +0000 (20:27 +0100)]
experiment with alternative PID in radix mmu
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:16:59 +0000 (20:16 +0100)]
pass in SPRs each time on radix test
allows for different tests
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:03:34 +0000 (20:03 +0100)]
add LD/ST radix unit test
Cesar Strauss [Sat, 17 Apr 2021 18:12:29 +0000 (15:12 -0300)]
Implement 1<<r3 directly by a shift
It generates simpler Yosys graphs.
Tobias Platen [Sat, 17 Apr 2021 17:22:12 +0000 (19:22 +0200)]
radixmmu: fix my mistake about pgbase size
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 22:46:02 +0000 (23:46 +0100)]
submodule update
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 19:49:29 +0000 (20:49 +0100)]
jtag utils, send tms before tck
Tobias Platen [Fri, 16 Apr 2021 19:26:19 +0000 (21:26 +0200)]
pass the "old" value of shift to _new_lookup
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 18:03:58 +0000 (19:03 +0100)]
sigh, new_shift wrong bitwidth
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:28:29 +0000 (01:28 +0100)]
put mbits back into segment_check (like it is in microwatt)
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:08:51 +0000 (01:08 +0100)]
radixmmu cleanup
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:04:07 +0000 (01:04 +0100)]
call addrshift and get_pgtable_addr inside while loop for radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:00:01 +0000 (01:00 +0100)]
code-cleanup in radixmmu
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 23:21:09 +0000 (00:21 +0100)]
whitespace and corrections to NLS, RTS1, RTS2
Tobias Platen [Thu, 15 Apr 2021 17:05:51 +0000 (19:05 +0200)]
fix radix testcase
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 15:43:12 +0000 (16:43 +0100)]
concat en_sigs together in JTAG to make sure they are not missed out
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 08:48:37 +0000 (09:48 +0100)]
add icachemmu option to ISACaller
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:38 +0000 (20:08 +0100)]
submodule update
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:28 +0000 (20:08 +0100)]
whitespace
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:04:24 +0000 (17:04 +0100)]
submodule update
Tobias Platen [Wed, 14 Apr 2021 18:22:20 +0000 (20:22 +0200)]
update test_caller_radix.py
Tobias Platen [Wed, 14 Apr 2021 18:16:00 +0000 (20:16 +0200)]
radixmmu: handle badtree
Tobias Platen [Wed, 14 Apr 2021 17:39:08 +0000 (19:39 +0200)]
update test case for radix mmu
Tobias Platen [Wed, 14 Apr 2021 17:34:13 +0000 (19:34 +0200)]
radixmmu: error handling
Tobias Platen [Tue, 13 Apr 2021 17:21:18 +0000 (19:21 +0200)]
more fixes for radixmmu.py
Tobias Platen [Tue, 13 Apr 2021 16:43:37 +0000 (18:43 +0200)]
fix AttributeError in radixmmu testcase
Tobias Platen [Mon, 12 Apr 2021 17:50:20 +0000 (19:50 +0200)]
radixmmu.py: cleanup
Tobias Platen [Sun, 11 Apr 2021 18:48:12 +0000 (20:48 +0200)]
fix bug in radixmmu.py
Tobias Platen [Sun, 11 Apr 2021 06:45:06 +0000 (08:45 +0200)]
radixmmu: more work on segment check
Cesar Strauss [Sat, 10 Apr 2021 20:27:48 +0000 (17:27 -0300)]
Implement 1<<r3 predicate mode
The mask bit selected by r3 is set to one.
A possible optimization would be to do step = r3 directly, but this is only
valid in non-zero mode.
The corresponding test cases now pass.
Cesar Strauss [Sat, 10 Apr 2021 19:59:19 +0000 (16:59 -0300)]
Add 1<<r3 test cases to TestIssuer
They fail, since it's not implemented yet.
Cesar Strauss [Sat, 10 Apr 2021 19:40:09 +0000 (16:40 -0300)]
Add test cases for 1<<r3 predication
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 11:40:48 +0000 (12:40 +0100)]
add blinken lights assembly (not used yet)
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 00:09:32 +0000 (01:09 +0100)]
test firmware upload program needed to branch back further in order to loop
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 23:24:42 +0000 (00:24 +0100)]
sort out pc reset when DMI interface requests reset
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:31 +0000 (21:53 +0100)]
submodule update
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:03 +0000 (21:53 +0100)]
argh, wb jtag stall probably is not working
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:38:55 +0000 (21:38 +0100)]
upload over 32-bit JTAG Wishbone
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:21:09 +0000 (21:21 +0100)]
shrink JTAG master bus to 32-bit (match with litex)
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 19:27:37 +0000 (20:27 +0100)]
submodule update
Tobias Platen [Wed, 7 Apr 2021 19:17:35 +0000 (21:17 +0200)]
WIP: calculate address of first page table entry
Tobias Platen [Wed, 7 Apr 2021 18:26:54 +0000 (20:26 +0200)]
radixmmu: fix segment_check function and its caller
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 21:07:12 +0000 (22:07 +0100)]
4k SRAM Instance needs write-enable @ 8-bit width
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:38:04 +0000 (21:38 +0100)]
8-bit granularity on JTAG wishbone
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:35:12 +0000 (21:35 +0100)]
remove unneeded code
Staf Verhaegen [Tue, 6 Apr 2021 18:50:58 +0000 (20:50 +0200)]
soc-cocotb-sim submodule update
Tobias Platen [Tue, 6 Apr 2021 17:21:14 +0000 (19:21 +0200)]
add mmu_states.dia
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:58:36 +0000 (15:58 +0100)]
git submodule update
Cesar Strauss [Tue, 6 Apr 2021 11:31:14 +0000 (08:31 -0300)]
Make the VL loop reentrant in HDL
This is done by shifting-out already used mask bits, at predicate fetch.
The corresponding test case now passes.
Cesar Strauss [Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)]
Add a HDL test case, where we start at the middle of the VL loop
It is expected to fail, since the HDL is not reentrant at this moment.
Cesar Strauss [Tue, 6 Apr 2021 11:18:26 +0000 (08:18 -0300)]
Start the test case from a point where the predicate bits are zeros
Since SVSTATE is user-programmable, src/dst step can really point anywhere,
at instruction start. Although interrupts will always restore src/dest step
pointing to a set mask bit, this is not guaranteed in general.
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:06:31 +0000 (12:06 +0100)]
litex submodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 10:47:10 +0000 (11:47 +0100)]
submodule update
Staf Verhaegen [Sun, 4 Apr 2021 16:09:17 +0000 (18:09 +0200)]
soc-cocotb-sim submodule update
Cesar Strauss [Sun, 4 Apr 2021 11:59:22 +0000 (08:59 -0300)]
Add test case for reentrant VL loop
We explicitly initialize src/dst step, as if we were returning from an
interrupt.
Cesar Strauss [Sat, 3 Apr 2021 20:12:30 +0000 (17:12 -0300)]
Reminder for a possible hardware optimization
Cesar Strauss [Sat, 3 Apr 2021 20:02:39 +0000 (17:02 -0300)]
Be more precise when using a one-bit constant
Cesar Strauss [Sat, 3 Apr 2021 19:18:56 +0000 (16:18 -0300)]
Fix typo
Cesar Strauss [Sat, 3 Apr 2021 19:16:48 +0000 (16:16 -0300)]
Add test case with all mask bits equal to zero
Cesar Strauss [Sat, 3 Apr 2021 19:04:49 +0000 (16:04 -0300)]
Add a test case for integer single predication
Cesar Strauss [Sat, 3 Apr 2021 18:48:50 +0000 (15:48 -0300)]
Disallow unknown encmodes in SVP64 Assembly
Cesar Strauss [Sat, 3 Apr 2021 18:45:39 +0000 (15:45 -0300)]
Enable remaining disabled test cases
They all work, now, after the ISA Caller fixes.
Cesar Strauss [Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)]
Allow the Simulator to handle back-to-back signaling from TestIssuer
TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.
Cesar Strauss [Sat, 3 Apr 2021 18:21:37 +0000 (15:21 -0300)]
Signal the simulator when completing a VL loop
When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.
Cesar Strauss [Sat, 3 Apr 2021 11:21:21 +0000 (08:21 -0300)]
Fix typo
Cesar Strauss [Sat, 3 Apr 2021 11:07:51 +0000 (08:07 -0300)]
Add twin predication test
Another simulator failure. Seems like the VL loop is still not terminating
properly. Will investigate.
Cesar Strauss [Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)]
End VL loop as soon as either src/dst step reaches VL
Also, avoid incrementing dststep beyond VL-1
Cesar Strauss [Fri, 2 Apr 2021 22:20:26 +0000 (19:20 -0300)]
Fix typo
Cesar Strauss [Fri, 2 Apr 2021 20:43:15 +0000 (17:43 -0300)]
Add VEXPAND test case for the ISA Simulator
The test currently does not pass, there must be a bug somewhere.
Seems like it is skipping the middle source element, as if it was doing
single-pred.
Cesar Strauss [Fri, 2 Apr 2021 20:25:13 +0000 (17:25 -0300)]
Add VCOMPRESS test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 19:58:48 +0000 (16:58 -0300)]
Put sanity check inside the existing '2Pred' case, and simplify
Cesar Strauss [Fri, 2 Apr 2021 19:53:32 +0000 (16:53 -0300)]
Enforce explicit src/dest masks on CR twin-predication
Cesar Strauss [Fri, 2 Apr 2021 19:32:33 +0000 (16:32 -0300)]
Disallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred
Cesar Strauss [Fri, 2 Apr 2021 18:51:46 +0000 (15:51 -0300)]
Disallow dm=xx on single predication
Adjust test cases accordingly.