soclayout.git
3 years agouse auto-generated pinmux ioPadsSpecs
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:38:19 +0000 (17:38 +0000)]
use auto-generated pinmux ioPadsSpecs

3 years agosubmodule conflict (update again)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:23:18 +0000 (17:23 +0000)]
submodule conflict (update again)

3 years agouse verilog version of ls180 in FreePDK_c4m45
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:21:32 +0000 (17:21 +0000)]
use verilog version of ls180 in FreePDK_c4m45

3 years agoUpdate c4m-pdk-freepdk45 submodule.
Staf Verhaegen [Sun, 11 Apr 2021 16:14:07 +0000 (18:14 +0200)]
Update c4m-pdk-freepdk45 submodule.

3 years agocrank up the numbers (again)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 16:07:19 +0000 (16:07 +0000)]
crank up the numbers (again)

3 years agoWip of P&R of ls180 with C4M FreePDK45.
Staf Verhaegen [Sun, 11 Apr 2021 15:38:45 +0000 (17:38 +0200)]
Wip of P&R of ls180 with C4M FreePDK45.

build_full.sh can run til after `make vst`,
`make lvx` fails.

3 years agoexperiments9: Ignore pinmux generated files.
Staf Verhaegen [Sun, 11 Apr 2021 15:14:13 +0000 (17:14 +0200)]
experiments9: Ignore pinmux generated files.

3 years agomksym.sh: Check exitence of alliance-check-toolkit
Staf Verhaegen [Sun, 11 Apr 2021 15:13:47 +0000 (17:13 +0200)]
mksym.sh: Check exitence of alliance-check-toolkit

3 years agoSubmodule for C4M FreePDK45 PDK release files.
Staf Verhaegen [Sun, 11 Apr 2021 15:03:50 +0000 (17:03 +0200)]
Submodule for C4M FreePDK45 PDK release files.

Use released-libresoc branch.

3 years agocrank up the numbers to see if routing completion can be achieved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 11:32:15 +0000 (11:32 +0000)]
crank up the numbers to see if routing completion can be achieved

3 years agoincrease katana tracks reserved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 10:43:20 +0000 (10:43 +0000)]
increase katana tracks reserved

3 years agouse verilog for ls180 instead of ilang
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 19:57:45 +0000 (19:57 +0000)]
use verilog for ls180 instead of ilang

3 years agomake VST names unique, for GHDL to cope
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 11:23:38 +0000 (11:23 +0000)]
make VST names unique, for GHDL to cope

3 years agosigh, broken experiment10_verilog
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 16:16:15 +0000 (16:16 +0000)]
sigh, broken experiment10_verilog

3 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:58:58 +0000 (15:58 +0000)]
whitespace

3 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:38 +0000 (15:55 +0000)]
whitespace cleanup

3 years agopad name starts with p_
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:29 +0000 (15:55 +0000)]
pad name starts with p_

3 years agorename design of experiments10 to match ls180 chip pads
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 12:05:11 +0000 (12:05 +0000)]
rename design of experiments10 to match ls180 chip pads

3 years agoexperiment with nmigen verilog generation
Luke Kenneth Casson Leighton [Fri, 2 Apr 2021 12:37:38 +0000 (12:37 +0000)]
experiment with nmigen verilog generation

3 years agoupdate / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:07 +0000 (22:41 +0000)]
update / refresh full core DFF

3 years agoupdate / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:29:06 +0000 (22:29 +0000)]
update / refresh full core DFF

3 years agorun doChipFloorplan in experiments10
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:35:18 +0000 (16:35 +0000)]
run doChipFloorplan in experiments10

3 years agoincrease experiment10 JTAG tap width to 4
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:30:45 +0000 (16:30 +0000)]
increase experiment10 JTAG tap width to 4

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:04:37 +0000 (16:04 +0000)]
update submodule

3 years agoupdate 4k SRAM ls180.il
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:55:43 +0000 (10:55 +0000)]
update 4k SRAM ls180.il

3 years agoadd yosys version number
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 09:45:45 +0000 (09:45 +0000)]
add yosys version number

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Mon, 29 Mar 2021 18:54:32 +0000 (20:54 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoAdd a placeholder for the PLL in the doDesign.py for ls180.
Jean-Paul Chaput [Mon, 29 Mar 2021 18:53:40 +0000 (20:53 +0200)]
Add a placeholder for the PLL in the doDesign.py for ls180.

3 years agoRevert "enable high fanout in ls180 experiment9 doDesign.py"
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:30:57 +0000 (18:30 +0000)]
Revert "enable high fanout in ls180 experiment9 doDesign.py"

This reverts commit 309301fd58ed12bec149292a40bf1a3c1507d36d.

3 years agoenable high fanout in ls180 experiment9 doDesign.py
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:19:23 +0000 (17:19 +0000)]
enable high fanout in ls180 experiment9 doDesign.py

3 years agoaaagh found bug in litex setup, 64 bit WB bus was truncated
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 07:18:29 +0000 (07:18 +0000)]
aaagh found bug in litex setup, 64 bit WB bus was truncated

3 years agoreduce SPR regfile size considerably
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 17:07:22 +0000 (17:07 +0000)]
reduce SPR regfile size considerably

3 years agoreduce INT and FAST regfile sizes by sharing ports
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 14:41:40 +0000 (14:41 +0000)]
reduce INT and FAST regfile sizes by sharing ports

3 years agoadd missing floorplan function call
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:47 +0000 (20:27 +0000)]
add missing floorplan function call

3 years agohooray, corrected pinouts
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:34 +0000 (20:27 +0000)]
hooray, corrected pinouts

3 years agoreally weird error "unsupported direction for eint" which makes no sense
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 17:38:26 +0000 (17:38 +0000)]
really weird error "unsupported direction for eint" which makes no sense

3 years agoUodated doDesign for the latest ls180 (sram variant).
Jean-Paul Chaput [Tue, 23 Mar 2021 19:25:33 +0000 (20:25 +0100)]
Uodated doDesign for the latest ls180 (sram variant).

3 years agoincrease DFF RAM size slightly
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:20:45 +0000 (17:20 +0000)]
increase DFF RAM size slightly

3 years agoadd very small DFF srams variant
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:15:00 +0000 (17:15 +0000)]
add very small DFF srams variant

3 years agocreate small dff with 4x 4k SRAMs
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:08:46 +0000 (17:08 +0000)]
create small dff with 4x 4k SRAMs

3 years agols180.il update
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:57:00 +0000 (12:57 +0000)]
ls180.il update

3 years agoargh pinmux generating bi-directional SDR DM when it should be output
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:43:36 +0000 (12:43 +0000)]
argh pinmux generating bi-directional SDR DM when it should be output

3 years agoupdate ls180.il
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:51:21 +0000 (12:51 +0000)]
update ls180.il

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Tue, 16 Mar 2021 17:40:41 +0000 (17:40 +0000)]
update submodule

3 years agoupdate ls180.il 4ksram with correct sdram connections
Luke Kenneth Casson Leighton [Tue, 16 Mar 2021 17:39:59 +0000 (17:39 +0000)]
update ls180.il 4ksram with correct sdram connections

3 years agoAdd experiment9/symbolic to test the multiple drivers problem.
Jean-Paul Chaput [Tue, 16 Mar 2021 11:41:34 +0000 (12:41 +0100)]
Add experiment9/symbolic to test the multiple drivers problem.

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Sun, 14 Mar 2021 16:04:58 +0000 (17:04 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
Jean-Paul Chaput [Sun, 14 Mar 2021 15:37:19 +0000 (16:37 +0100)]
Adjusted doDesign.py scripts to use Chip.doChipFloorplan().

3 years agotry alternative pad/core connection
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 11:31:22 +0000 (11:31 +0000)]
try alternative pad/core connection

3 years agoForgot the Makefile, stupid!
Jean-Paul Chaput [Tue, 9 Mar 2021 10:24:50 +0000 (11:24 +0100)]
Forgot the Makefile, stupid!

3 years agoFirst working version of the Flexlib + P&R flow for the ls180+SRAM.
Jean-Paul Chaput [Tue, 9 Mar 2021 10:01:04 +0000 (11:01 +0100)]
First working version of the Flexlib + P&R flow for the ls180+SRAM.

Note: It is working in the sense that the flow complete, but is stills
      contains various errors that needs fixing.
        We discoupled from pinmux as core2chip have problems associating
      the pad instances names with the relevant core signals.
        We guessed a pad placement from pinmux, but it seems a bit odd
      to me...

3 years agoadd blackbox SPBlock 4k SRAM module
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:30:42 +0000 (00:30 +0000)]
add blackbox SPBlock 4k SRAM module

3 years agoremove sram 4k wb bte/cti
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 23:10:35 +0000 (23:10 +0000)]
remove sram 4k wb bte/cti

3 years agolitex expects wishbone "err" signals, added to sram 4k
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:09:25 +0000 (21:09 +0000)]
litex expects wishbone "err" signals, added to sram 4k

3 years agorename sram_4k wishbone interface to actually like include "wishbone"?
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:19:18 +0000 (19:19 +0000)]
rename sram_4k wishbone interface to actually like include "wishbone"?

3 years agoAdded support files for ls180+SRAM on TSMC 180nm.
Jean-Paul Chaput [Fri, 5 Mar 2021 10:14:02 +0000 (11:14 +0100)]
Added support files for ls180+SRAM on TSMC 180nm.

3 years agoadd blackbox attribute manually to SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 22:03:40 +0000 (22:03 +0000)]
add blackbox attribute manually to SPBlock_512W64B8W

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 2 Mar 2021 12:02:14 +0000 (13:02 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoFirst working power plane in experiment12.
Jean-Paul Chaput [Tue, 2 Mar 2021 11:23:36 +0000 (12:23 +0100)]
First working power plane in experiment12.

3 years agoadd 4k sram build
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:25:29 +0000 (15:25 +0000)]
add 4k sram build

3 years agoincrease core size to 50000 (DFF SRAMs)
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:24:02 +0000 (15:24 +0000)]
increase core size to 50000 (DFF SRAMs)

3 years agoexpand core size to 28000
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:37:54 +0000 (12:37 +0000)]
expand core size to 28000

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 17 Feb 2021 23:12:50 +0000 (00:12 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoFirst working integration of a SRAM block.
Jean-Paul Chaput [Wed, 17 Feb 2021 23:10:43 +0000 (00:10 +0100)]
First working integration of a SRAM block.

The placement itself is completely goofy in order to stress the P&R system
to flush out bugs.

3 years agowhitespace
Luke Kenneth Casson Leighton [Tue, 2 Feb 2021 17:53:12 +0000 (17:53 +0000)]
whitespace

3 years agowhitespace
Luke Kenneth Casson Leighton [Tue, 2 Feb 2021 17:47:03 +0000 (17:47 +0000)]
whitespace

3 years agoNetlist integration of the SRAM OK. Layout in progress.
Jean-Paul Chaput [Mon, 1 Feb 2021 16:04:38 +0000 (17:04 +0100)]
Netlist integration of the SRAM OK. Layout in progress.

3 years agoWorking bench design with SRAM in top block.
Jean-Paul Chaput [Thu, 28 Jan 2021 14:02:22 +0000 (15:02 +0100)]
Working bench design with SRAM in top block.

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 27 Jan 2021 13:04:54 +0000 (14:04 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

Conflicts:
experiments9/doDesign.py

3 years agoPinmux loading is now integrated in Coriolis.
Jean-Paul Chaput [Wed, 27 Jan 2021 13:02:55 +0000 (14:02 +0100)]
Pinmux loading is now integrated in Coriolis.

3 years agoadd new Memory experiments13 ls180-24jan2020
Luke Kenneth Casson Leighton [Fri, 15 Jan 2021 13:35:45 +0000 (13:35 +0000)]
add new Memory experiments13

3 years agoadd SPBlock_512W64B8W to memory.py
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 15:02:32 +0000 (15:02 +0000)]
add SPBlock_512W64B8W to memory.py

3 years agorename to memory from add
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 14:54:36 +0000 (14:54 +0000)]
rename to memory from add

3 years agoadd copy of experiments4 to create memory example
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 14:52:01 +0000 (14:52 +0000)]
add copy of experiments4 to create memory example

3 years agoincrease core size (again) to cope with DFFs currently being made
Luke Kenneth Casson Leighton [Fri, 4 Dec 2020 22:30:16 +0000 (22:30 +0000)]
increase core size (again) to cope with DFFs currently being made
instead of SRAM

3 years agoRevert "very weird bug where CoreToChip.buildChip cannot find gpio_o(8)"
Luke Kenneth Casson Leighton [Fri, 4 Dec 2020 22:29:28 +0000 (22:29 +0000)]
Revert "very weird bug where CoreToChip.buildChip cannot find gpio_o(8)"

This reverts commit a4ac6b9543939ffea583be44cfba1141bdaeb7e6.

3 years agovery weird bug where CoreToChip.buildChip cannot find gpio_o(8)
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 18:30:12 +0000 (18:30 +0000)]
very weird bug where CoreToChip.buildChip cannot find gpio_o(8)

3 years agoincrease size to 45,000 to cope with 3x extra SRAMs
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 17:12:05 +0000 (17:12 +0000)]
increase size to 45,000 to cope with 3x extra SRAMs

3 years agoexperiment adding 3x extra SRAMs back in but still @ 32-bit WB
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:51:30 +0000 (16:51 +0000)]
experiment adding 3x extra SRAMs back in but still @ 32-bit WB

3 years agowtf does 32/64 bit bus have to do with gpio_o(8) disappearing??
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:27:01 +0000 (16:27 +0000)]
wtf does 32/64 bit bus have to do with gpio_o(8) disappearing??

3 years agoreduce mem width due to yosys bugs. sigh
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:18:19 +0000 (16:18 +0000)]
reduce mem width due to yosys bugs.  sigh

3 years agoadded 3 more 4k SRAMs
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 15:36:00 +0000 (15:36 +0000)]
added 3 more 4k SRAMs

3 years agoincrease size to 40,000
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:44:51 +0000 (23:44 +0000)]
increase size to 40,000

3 years agobegin random search for appropriate core size. start at 36000
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:36:41 +0000 (23:36 +0000)]
begin random search for appropriate core size.  start at 36000

3 years agoadd full core back in
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:34:30 +0000 (23:34 +0000)]
add full core back in

3 years agoupdate submodule for ls180 pinmux, iopad vss/vdd inversion corrected partial-core-ls180-gdsii
Luke Kenneth Casson Leighton [Mon, 30 Nov 2020 15:04:46 +0000 (15:04 +0000)]
update submodule for ls180 pinmux, iopad vss/vdd inversion corrected

3 years agoAdded experiments11, base for full chip with FlexLib & LibreSOCIO.
Jean-Paul Chaput [Mon, 30 Nov 2020 11:13:07 +0000 (12:13 +0100)]
Added experiments11, base for full chip with FlexLib & LibreSOCIO.

3 years agoadd comment do not use build.sh
Luke Kenneth Casson Leighton [Fri, 27 Nov 2020 17:50:53 +0000 (17:50 +0000)]
add comment do not use build.sh

3 years agoupdate ls180 litex interfaces
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 18:42:50 +0000 (18:42 +0000)]
update ls180 litex interfaces

3 years agoget rid of ibus/dbus/xics advanced wishbone tags
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 16:07:14 +0000 (16:07 +0000)]
get rid of ibus/dbus/xics advanced wishbone tags

3 years agoupdate litex direction of iopads in ls180
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 14:28:28 +0000 (14:28 +0000)]
update litex direction of iopads in ls180

3 years agocorona-core gap too small
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 20:18:17 +0000 (20:18 +0000)]
corona-core gap too small

4 years agoincrease core size yet again, shrink gap
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:39:44 +0000 (18:39 +0000)]
increase core size yet again, shrink gap

4 years agoincrease core size, reduce corona gap again
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:25:07 +0000 (18:25 +0000)]
increase core size, reduce corona gap again

4 years agoreduce nc ls180 pins to match
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:04:41 +0000 (18:04 +0000)]
reduce nc ls180 pins to match

4 years agoincrease chip size by 100, make chipSize closer to ring
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:02:05 +0000 (18:02 +0000)]
increase chip size by 100, make chipSize closer to ring

4 years agofix clk_sel width (2 not 3)
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:48:28 +0000 (17:48 +0000)]
fix clk_sel width (2 not 3)

4 years agotrying to get yosys to stop destroying pll_lck_o signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:43:51 +0000 (17:43 +0000)]
trying to get yosys to stop destroying pll_lck_o signal

4 years agotrying to get yosys to stop destroying pll_lck_o signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:41:38 +0000 (17:41 +0000)]
trying to get yosys to stop destroying pll_lck_o signal

4 years agoupdate full core ls180 (actually with litex peripherals but not core)
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:11:20 +0000 (16:11 +0000)]
update full core ls180 (actually with litex peripherals but not core)