Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:41:05 +0000 (04:41 +0100)]
set SRR0 in OP_SC
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:37:41 +0000 (04:37 +0100)]
add OP_RFID SRR0/SRR1 in PowerDecode2
colepoirier [Thu, 4 Jun 2020 22:37:19 +0000 (15:37 -0700)]
Use a_i and b_i convenience variables instead of a and b registers in
fu/trap/main_stage
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:53:20 +0000 (21:53 +0100)]
testing CRs after writing: not in the right bit-order
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:34:00 +0000 (21:34 +0100)]
remove unneeded code
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:01:11 +0000 (21:01 +0100)]
use common TestCase class in logical
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:00:58 +0000 (21:00 +0100)]
add branch test case to core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:58:01 +0000 (20:58 +0100)]
no global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:54:16 +0000 (20:54 +0100)]
sigh. because POWER. CR index inversion
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:49:32 +0000 (20:49 +0100)]
sigh. weirdness involving bit-inversion, inconsistency on mfcr and isel
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:20:22 +0000 (20:20 +0100)]
no global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:18:18 +0000 (20:18 +0100)]
add ShiftRot test case (works only because CRs are not tested)
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:17:12 +0000 (20:17 +0100)]
add both logical and ALU test core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:13:40 +0000 (20:13 +0100)]
no global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:12:11 +0000 (20:12 +0100)]
no global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:10:37 +0000 (20:10 +0100)]
no global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:05:33 +0000 (20:05 +0100)]
whoops, docstring indentation
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 18:54:36 +0000 (19:54 +0100)]
add docstrings for read/write port connection
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 18:50:46 +0000 (19:50 +0100)]
move core code into separate functions, for clarity
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:57:36 +0000 (18:57 +0100)]
reduce amount of code in SelectableInt
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:53:13 +0000 (18:53 +0100)]
oops forgot to switch write-enable off
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:48:46 +0000 (18:48 +0100)]
comment clarify on core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:45:31 +0000 (18:45 +0100)]
initialise XER from simulation
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:27:27 +0000 (18:27 +0100)]
messing with valid/busy signals in core test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:27:03 +0000 (18:27 +0100)]
add extra argument (not used) to regfile.py
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:26:07 +0000 (18:26 +0100)]
hmmm sync-delay wport write and wen
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:52:21 +0000 (17:52 +0100)]
whitespace
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:45:41 +0000 (17:45 +0100)]
test actual reg values being produced in core test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:34:37 +0000 (17:34 +0100)]
use common TestCase in branch
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:32:56 +0000 (17:32 +0100)]
use common TestCase in shift_rot
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:31:47 +0000 (17:31 +0100)]
use common TestCase in alu
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:29:00 +0000 (17:29 +0100)]
move TestCase to common location
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:28:46 +0000 (17:28 +0100)]
move reg setup to earlier in test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 15:09:20 +0000 (16:09 +0100)]
comment out wrflag as it should already be in the fu.wr.rel logic
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:30:44 +0000 (14:30 +0100)]
test against Logical (hard-coded change)
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:23:26 +0000 (14:23 +0100)]
add first cut at test core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:21:42 +0000 (14:21 +0100)]
sync onto fu.go_wr_i otherwise a loop occurs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:06:42 +0000 (14:06 +0100)]
add rdmask and issue/busy setting
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:51:01 +0000 (13:51 +0100)]
remove unneeded imports
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:48:17 +0000 (13:48 +0100)]
use copy of FHDLTestCase
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:03:04 +0000 (13:03 +0100)]
connect up write-ports from Regfiles to FUs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:54:09 +0000 (12:54 +0100)]
docstring for AllFunctionUnits
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:53:41 +0000 (12:53 +0100)]
missing a fastregs write-port
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:31:38 +0000 (12:31 +0100)]
update docstring on simple/core.py
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:27:10 +0000 (12:27 +0100)]
move regfile/spec organiser to separate function
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:03:55 +0000 (12:03 +0100)]
mention convenience variables
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 10:58:49 +0000 (11:58 +0100)]
rename trap to use convenience variables
colepoirier [Thu, 4 Jun 2020 00:22:32 +0000 (17:22 -0700)]
Undo damage done by deleting VHDL microwatt comments,
merge resolution deletion of convenience variables in
fu/trap/main_stage
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:24:20 +0000 (01:24 +0100)]
collate fu-enable signals
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:18:34 +0000 (01:18 +0100)]
connect up Function Unit operand subsets
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:55:02 +0000 (00:55 +0100)]
forgot to add in rdflag enable
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:52:04 +0000 (00:52 +0100)]
whoops, regfiles are uppercase
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:42:44 +0000 (00:42 +0100)]
whoops needed a bit of a reorg of the data structure for regfile connections
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:02:35 +0000 (00:02 +0100)]
hmmm got naming wrong in regfile-fu connectivity
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:46:17 +0000 (23:46 +0100)]
whoops names of regfiles are lower-case
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:28:56 +0000 (23:28 +0100)]
munge/redirect the regfile port based on the naming
"full" ports are the first indexed.
also only enable the read-port enable if the picker is enabled
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:00:05 +0000 (23:00 +0100)]
connect read-enable and src_i to regfile ports
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 21:45:12 +0000 (22:45 +0100)]
link up PriorityPickers on read channels
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:22:36 +0000 (20:22 +0100)]
put rdspecs into a different dictionary
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:00:07 +0000 (20:00 +0100)]
start putting a non-production core together,
sorting the read ports first, to get a look at them
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 17:29:34 +0000 (18:29 +0100)]
add a simple core, not intended for production use
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 14:22:14 +0000 (15:22 +0100)]
correct comments on regspec decode map
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:57:48 +0000 (14:57 +0100)]
only select xer_xo if OE enabled
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:32:01 +0000 (14:32 +0100)]
decide to elaborate Refiles *into* another class, rather than make them their
own module. this will reduce a level of hierarchy and make access easier
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:30:00 +0000 (14:30 +0100)]
turn RegFiles into module, add all regfiles to it
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:18:02 +0000 (14:18 +0100)]
add a simple class containing all FunctionUnits
Tobias Platen [Wed, 3 Jun 2020 13:15:02 +0000 (15:15 +0200)]
more work on proof_datamerger.py
Tobias Platen [Wed, 3 Jun 2020 13:12:01 +0000 (15:12 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:07:21 +0000 (14:07 +0100)]
add class containing all regfiles
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:40:07 +0000 (13:40 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:35:08 +0000 (13:35 +0100)]
use common get_cu_inputs for CR unit tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:28:24 +0000 (13:28 +0100)]
convert shift_rot tests to use common get_cu_inputs function
Tobias Platen [Wed, 3 Jun 2020 12:19:48 +0000 (14:19 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 3 Jun 2020 12:19:40 +0000 (14:19 +0200)]
whitespace fix for proof_datamerger.py
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:10:51 +0000 (13:10 +0100)]
reorganise ALU tests, move get_cu_inputs function to common location
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:52:25 +0000 (12:52 +0100)]
worked out how to dynamically enable carry-in to ALU: test input_carry against CryIn.CA.value
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:43:25 +0000 (12:43 +0100)]
correct overflow-enable flags for rdmask specs in ALU
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:41:44 +0000 (12:41 +0100)]
attempt to make carry-in and overflow-enable optional on ALU
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:31:16 +0000 (12:31 +0100)]
remove rdflags in pipe_data.py (redundant)
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:29:02 +0000 (12:29 +0100)]
move over to using power_regspec_map.py from PowerDecode2 rather than distributed maps in pipe_data.py
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:10:20 +0000 (12:10 +0100)]
move obtaining simulator data into common function for logical pipe tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:01:37 +0000 (12:01 +0100)]
mention TODO on SPR regfile
Cesar Strauss [Wed, 3 Jun 2020 09:30:04 +0000 (06:30 -0300)]
Check completion of the sub-processes
This detects the case where busy_o goes low before the rel / go
cycle finishes.
colepoirier [Wed, 3 Jun 2020 02:27:54 +0000 (19:27 -0700)]
Fixed missing nia.ok.eq(1) in OP_RFID
colepoirier [Wed, 3 Jun 2020 02:24:24 +0000 (19:24 -0700)]
Fixed merge conflict by using remote changes
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 02:01:50 +0000 (03:01 +0100)]
tidyup branch. comments
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:55:01 +0000 (02:55 +0100)]
convenience variables
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:47:12 +0000 (02:47 +0100)]
FormX not FormXL
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:46:58 +0000 (02:46 +0100)]
add bit more TODO
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:39:29 +0000 (02:39 +0100)]
update submodule for ISA tables
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:37:22 +0000 (02:37 +0100)]
convenience rename for spr pipe_data.py, consistent naming for PowerDecode2
Cesar Strauss [Wed, 3 Jun 2020 01:28:56 +0000 (22:28 -0300)]
Simplify immediate check
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:26:58 +0000 (02:26 +0100)]
add more TODOs
Cesar Strauss [Wed, 3 Jun 2020 01:16:07 +0000 (22:16 -0300)]
Preliminary check of the alu protocol
Still need to check that the operand to the alu is held stable.
For now, it's more like a placeholder of what will become the full check.
Cesar Strauss [Wed, 3 Jun 2020 01:07:33 +0000 (22:07 -0300)]
Pass along the operand, in the cycle in which go is active
colepoirier [Wed, 3 Jun 2020 01:11:02 +0000 (18:11 -0700)]
Fixed OP_RFID and OP_SC in fu/trap/main_stage
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 00:58:36 +0000 (01:58 +0100)]
add some more constants and ref to POWER9 pdf
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 00:45:33 +0000 (01:45 +0100)]
add an if for OP_MTMSR and some comments
colepoirier [Wed, 3 Jun 2020 00:07:39 +0000 (17:07 -0700)]
Attempted to fix OP_RFID in TRAP pipeline
colepoirier [Tue, 2 Jun 2020 23:41:37 +0000 (16:41 -0700)]
Implement TRAP instructions OP_RFID and OP_SC