soc.git
2021-04-22 Luke Kenneth... dcache.py code-comments
2021-04-22 Luke Kenneth... cleanup dcache
2021-04-22 Luke Kenneth... error using sync, should have been comb
2021-04-22 Cesar StraussImplement CR predication
2021-04-21 Cesar StraussCR sub-fields are stored in MSB0 order
2021-04-21 Luke Kenneth... experimenting with dcache
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu
2021-04-21 Cesar StraussAdd CR predication test case for TestIssuer
2021-04-21 Cesar StraussFix comment in CR predication test case
2021-04-21 Cesar StraussFix sense of "invert" signal
2021-04-20 Luke Kenneth... add enable MMU option to issuer_verilog.py
2021-04-20 Luke Kenneth... cannot pass in arguments to Core - must be done with...
2021-04-20 Luke Kenneth... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-20 Luke Kenneth... add wishbone sram.py (move from nmigen-soc)
2021-04-19 Luke Kenneth... give independent names to spblock512w64b8ws
2021-04-18 Luke Kenneth... give spblock512 a name as a submodule
2021-04-18 Luke Kenneth... create signal on test_issuer which gives PLL clk_sel_i...
2021-04-18 Luke Kenneth... rename SPBlock_512W64B8W to lowercase
2021-04-18 Luke Kenneth... submodule update
2021-04-18 Luke Kenneth... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth... core_stopped_i unused: remove
2021-04-18 Luke Kenneth... submodule update
2021-04-18 Luke Kenneth... submodule update
2021-04-18 Luke Kenneth... add pypi upload to Makefile
2021-04-18 Luke Kenneth... add OS Independent classifier
2021-04-18 Luke Kenneth... update README
2021-04-18 Luke Kenneth... update setup.py to make it "safe" for uploading to...
2021-04-17 Luke Kenneth... experiment with alternative PID in radix mmu
2021-04-17 Luke Kenneth... pass in SPRs each time on radix test
2021-04-17 Luke Kenneth... add LD/ST radix unit test
2021-04-17 Cesar StraussImplement 1<<r3 directly by a shift
2021-04-17 Tobias Platenradixmmu: fix my mistake about pgbase size
2021-04-16 Luke Kenneth... submodule update
2021-04-16 Luke Kenneth... jtag utils, send tms before tck
2021-04-16 Tobias Platenpass the "old" value of shift to _new_lookup
2021-04-16 Luke Kenneth... sigh, new_shift wrong bitwidth
2021-04-16 Luke Kenneth... put mbits back into segment_check (like it is in microwatt)
2021-04-16 Luke Kenneth... radixmmu cleanup
2021-04-16 Luke Kenneth... call addrshift and get_pgtable_addr inside while loop...
2021-04-16 Luke Kenneth... code-cleanup in radixmmu
2021-04-15 Luke Kenneth... whitespace and corrections to NLS, RTS1, RTS2
2021-04-15 Tobias Platenfix radix testcase
2021-04-15 Luke Kenneth... concat en_sigs together in JTAG to make sure they are...
2021-04-15 Luke Kenneth... add icachemmu option to ISACaller
2021-04-14 Luke Kenneth... submodule update
2021-04-14 Luke Kenneth... whitespace
2021-04-14 Luke Kenneth... submodule update
2021-04-14 Tobias Platenupdate test_caller_radix.py
2021-04-14 Tobias Platenradixmmu: handle badtree
2021-04-14 Tobias Platenupdate test case for radix mmu
2021-04-14 Tobias Platenradixmmu: error handling
2021-04-13 Tobias Platenmore fixes for radixmmu.py
2021-04-13 Tobias Platenfix AttributeError in radixmmu testcase
2021-04-12 Tobias Platenradixmmu.py: cleanup
2021-04-11 Tobias Platenfix bug in radixmmu.py
2021-04-11 Tobias Platenradixmmu: more work on segment check
2021-04-10 Cesar StraussImplement 1<<r3 predicate mode
2021-04-10 Cesar StraussAdd 1<<r3 test cases to TestIssuer
2021-04-10 Cesar StraussAdd test cases for 1<<r3 predication
2021-04-09 Luke Kenneth... add blinken lights assembly (not used yet)
2021-04-09 Luke Kenneth... test firmware upload program needed to branch back...
2021-04-08 Luke Kenneth... sort out pc reset when DMI interface requests reset
2021-04-08 Luke Kenneth... submodule update
2021-04-08 Luke Kenneth... argh, wb jtag stall probably is not working
2021-04-08 Luke Kenneth... upload over 32-bit JTAG Wishbone
2021-04-08 Luke Kenneth... shrink JTAG master bus to 32-bit (match with litex)
2021-04-07 Luke Kenneth... submodule update
2021-04-07 Tobias PlatenWIP: calculate address of first page table entry
2021-04-07 Tobias Platenradixmmu: fix segment_check function and its caller
2021-04-06 Luke Kenneth... 4k SRAM Instance needs write-enable @ 8-bit width
2021-04-06 Luke Kenneth... 8-bit granularity on JTAG wishbone
2021-04-06 Luke Kenneth... remove unneeded code
2021-04-06 Staf Verhaegensoc-cocotb-sim submodule update
2021-04-06 Tobias Platenadd mmu_states.dia
2021-04-06 Luke Kenneth... git submodule update
2021-04-06 Cesar StraussMake the VL loop reentrant in HDL
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of...
2021-04-06 Cesar StraussStart the test case from a point where the predicate...
2021-04-05 Luke Kenneth... litex submodule update
2021-04-05 Luke Kenneth... submodule update
2021-04-04 Staf Verhaegensoc-cocotb-sim submodule update
2021-04-04 Cesar StraussAdd test case for reentrant VL loop
2021-04-03 Cesar StraussReminder for a possible hardware optimization
2021-04-03 Cesar StraussBe more precise when using a one-bit constant
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero
2021-04-03 Cesar StraussAdd a test case for integer single predication
2021-04-03 Cesar StraussDisallow unknown encmodes in SVP64 Assembly
2021-04-03 Cesar StraussEnable remaining disabled test cases
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-04-03 Cesar StraussSignal the simulator when completing a VL loop
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd twin predication test
2021-04-02 Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussAdd VEXPAND test case for the ISA Simulator
2021-04-02 Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
2021-04-02 Cesar StraussPut sanity check inside the existing '2Pred' case,...
2021-04-02 Cesar StraussEnforce explicit src/dest masks on CR twin-predication
2021-04-02 Cesar StraussDisallow mixing of sm=xx and/or dm=xx with m=xx on...
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