soc.git
2020-06-07 Luke Kenneth... optionally writing out CA/CA32 to XER
2020-06-07 Luke Kenneth... add handling of CA/CA32 in simulator, generated from...
2020-06-07 Luke Kenneth... add CA/CA32 to list of special regs
2020-06-07 Luke Kenneth... add missing arg to ISA in test_compunit
2020-06-07 Luke Kenneth... Revert "if referred to through GPR (GPR[RA]), add to...
2020-06-07 Luke Kenneth... Revert "remove fixedlogical.patch - added gprs to Power...
2020-06-07 Luke Kenneth... Revert "add gprs to PowerParser write_regs in p_atom_name"
2020-06-07 Luke Kenneth... add extra missing args to ISA setup in alu test_pipe_caller
2020-06-07 Luke Kenneth... if referred to through GPR (GPR[RA]), add to read_regs...
2020-06-07 Luke Kenneth... add gprs to PowerParser write_regs in p_atom_name
2020-06-07 Luke Kenneth... add missing args to ISA
2020-06-07 Luke Kenneth... remove fixedlogical.patch - added gprs to PowerParser...
2020-06-07 Luke Kenneth... docstring on caller.py inject() decorator
2020-06-07 Luke Kenneth... add TRAP function, stub
2020-06-07 Luke Kenneth... update submodule for sprset.mdwn
2020-06-07 Luke Kenneth... add MSR to simulator context
2020-06-07 Luke Kenneth... move MSR_PR checking to separate functiong
2020-06-07 colepoirierFix missing 'comb +='
2020-06-06 Luke Kenneth... add python3 env-var if not set in Makefile
2020-06-06 Luke Kenneth... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth... expand regwid to 64 in l0_cache test
2020-06-06 Luke Kenneth... work out how to initialise memory directly
2020-06-06 Luke Kenneth... initialise L0 Memory from simulator memory
2020-06-06 Luke Kenneth... wait a little for wr.rel to activate if wrmask is active
2020-06-06 Luke Kenneth... missing test.mem arg for ISA in test_core
2020-06-06 Luke Kenneth... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth... shift-mask in Simulator Mem class not quite right
2020-06-06 Luke Kenneth... write-mask made from LD and Update mode (for data_o...
2020-06-06 Luke Kenneth... allow Mem in Simulator to be initialised
2020-06-06 Luke Kenneth... use name of unit to write simulator/vcd file
2020-06-06 Luke Kenneth... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth... allow CompLDSTOpSubset to be passed through to LDSTCompUnit
2020-06-06 Luke Kenneth... set up LDSTCompUnit using regspec
2020-06-06 Luke Kenneth... add extra bugreport link
2020-06-06 Luke Kenneth... whitespace
2020-06-06 Luke Kenneth... whitespace indentation
2020-06-06 Luke Kenneth... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth... whoops dest%d_o not dest%d_i
2020-06-06 Luke Kenneth... add beginnings of LDST compunit test
2020-06-06 Luke Kenneth... whitespace
2020-06-06 Luke Kenneth... whitespace / code-munge
2020-06-06 Luke Kenneth... comments / whitespace
2020-06-06 Luke Kenneth... update stage docstring
2020-06-06 Luke Kenneth... code-munge
2020-06-06 Luke Kenneth... remove unneeded imports
2020-06-06 Luke Kenneth... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-05 Luke Kenneth... comment out CR assertion for now
2020-06-05 colepoirierAdded skeleton fu/trap/test/test_pipe_caller using
2020-06-05 colepoirierAdd trap_input_data.py for fu/trap, cookie-cut from
2020-06-05 Tobias Platenfix proof_datamerger (see 216#c56)
2020-06-05 Luke Kenneth... update comments
2020-06-05 Luke Kenneth... add comments and start of elaborate
2020-06-05 Luke Kenneth... more comments
2020-06-05 Luke Kenneth... more comments
2020-06-05 Luke Kenneth... a_i not b_in
2020-06-05 Luke Kenneth... add comments
2020-06-05 Luke Kenneth... experimenting with CR, not quite right
2020-06-05 colepoirierMade small changes to fu/trap/main_stage to bring nmige...
2020-06-05 Tobias Platenimplement init function of DualPortSplitter
2020-06-05 Tobias Platenuncomment rtlil.convert in test_l0_cache that causes...
2020-06-05 Luke Kenneth... whoops returning cr2 for cr3 regspec map
2020-06-05 Luke Kenneth... name regfile ports by name not numerical position
2020-06-05 Luke Kenneth... whoops connecting up CR in wrong order. fixing with...
2020-06-05 Luke Kenneth... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-05 Luke Kenneth... add TODO for MFSPR/MTSPR
2020-06-05 Luke Kenneth... refer to srr0/1 not a/b
2020-06-05 Luke Kenneth... add msr_copy function and use it in OP_TRAP, OP_RFID...
2020-06-05 Luke Kenneth... set SRR0 in OP_SC
2020-06-05 Luke Kenneth... add OP_RFID SRR0/SRR1 in PowerDecode2
2020-06-04 colepoirierUse a_i and b_i convenience variables instead of a...
2020-06-04 Luke Kenneth... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth... remove unneeded code
2020-06-04 Luke Kenneth... use common TestCase class in logical
2020-06-04 Luke Kenneth... add branch test case to core
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth... add both logical and ALU test core
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... whoops, docstring indentation
2020-06-04 Luke Kenneth... add docstrings for read/write port connection
2020-06-04 Luke Kenneth... move core code into separate functions, for clarity
2020-06-04 Luke Kenneth... reduce amount of code in SelectableInt
2020-06-04 Luke Kenneth... oops forgot to switch write-enable off
2020-06-04 Luke Kenneth... comment clarify on core
2020-06-04 Luke Kenneth... initialise XER from simulation
2020-06-04 Luke Kenneth... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth... add extra argument (not used) to regfile.py
2020-06-04 Luke Kenneth... hmmm sync-delay wport write and wen
2020-06-04 Luke Kenneth... whitespace
2020-06-04 Luke Kenneth... test actual reg values being produced in core test
2020-06-04 Luke Kenneth... use common TestCase in branch
2020-06-04 Luke Kenneth... use common TestCase in shift_rot
2020-06-04 Luke Kenneth... use common TestCase in alu
2020-06-04 Luke Kenneth... move TestCase to common location
2020-06-04 Luke Kenneth... move reg setup to earlier in test
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