| 2021-04-09 | 
Luke Kenneth...  | pad name starts with p_ | 
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| 2021-04-09 | 
Luke Kenneth...  | rename design of experiments10 to match ls180 chip...  | 
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| 2021-04-02 | 
Luke Kenneth...  | experiment with nmigen verilog generation | 
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| 2021-04-01 | 
Luke Kenneth...  | update / refresh full core DFF | 
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| 2021-04-01 | 
Luke Kenneth...  | update / refresh full core DFF | 
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| 2021-04-01 | 
Luke Kenneth...  | run doChipFloorplan in experiments10 | 
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| 2021-04-01 | 
Luke Kenneth...  | increase experiment10 JTAG tap width to 4 | 
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| 2021-04-01 | 
Luke Kenneth...  | update submodule | 
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| 2021-03-30 | 
Luke Kenneth...  | update 4k SRAM ls180.il | 
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| 2021-03-30 | 
Luke Kenneth...  | add yosys version number | 
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| 2021-03-29 | 
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922...  | 
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| 2021-03-29 | 
Jean-Paul Chaput | Add a placeholder for the PLL in the doDesign.py for...  | 
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| 2021-03-29 | 
Luke Kenneth...  | Revert "enable high fanout in ls180 experiment9 doDesig...  | 
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| 2021-03-29 | 
Luke Kenneth...  | enable high fanout in ls180 experiment9 doDesign.py | 
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| 2021-03-29 | 
Luke Kenneth...  | aaagh found bug in litex setup, 64 bit WB bus was truncated | 
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| 2021-03-28 | 
Luke Kenneth...  | reduce SPR regfile size considerably | 
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| 2021-03-28 | 
Luke Kenneth...  | reduce INT and FAST regfile sizes by sharing ports | 
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| 2021-03-27 | 
Luke Kenneth...  | add missing floorplan function call | 
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| 2021-03-27 | 
Luke Kenneth...  | hooray, corrected pinouts | 
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| 2021-03-27 | 
Luke Kenneth...  | really weird error "unsupported direction for eint...  | 
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| 2021-03-23 | 
Jean-Paul Chaput | Uodated doDesign for the latest ls180 (sram variant). | 
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| 2021-03-22 | 
Luke Kenneth...  | increase DFF RAM size slightly | 
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| 2021-03-22 | 
Luke Kenneth...  | add very small DFF srams variant | 
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| 2021-03-22 | 
Luke Kenneth...  | create small dff with 4x 4k SRAMs | 
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| 2021-03-22 | 
Luke Kenneth...  | ls180.il update | 
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| 2021-03-22 | 
Luke Kenneth...  | argh pinmux generating bi-directional SDR DM when it...  | 
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| 2021-03-18 | 
Luke Kenneth...  | update ls180.il | 
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| 2021-03-16 | 
Luke Kenneth...  | update submodule | 
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| 2021-03-16 | 
Luke Kenneth...  | update ls180.il 4ksram with correct sdram connections | 
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| 2021-03-16 | 
Jean-Paul Chaput | Add experiment9/symbolic to test the multiple drivers...  | 
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| 2021-03-14 | 
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922...  | 
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| 2021-03-14 | 
Jean-Paul Chaput | Adjusted doDesign.py scripts to use Chip.doChipFloorplan(). | 
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| 2021-03-11 | 
Luke Kenneth...  | try alternative pad/core connection | 
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| 2021-03-09 | 
Jean-Paul Chaput | Forgot the Makefile, stupid! | 
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| 2021-03-09 | 
Jean-Paul Chaput | First working version of the Flexlib + P&R flow for...  | 
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| 2021-03-06 | 
Luke Kenneth...  | add blackbox SPBlock 4k SRAM module | 
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| 2021-03-05 | 
Luke Kenneth...  | remove sram 4k wb bte/cti | 
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| 2021-03-05 | 
Luke Kenneth...  | litex expects wishbone "err" signals, added to sram 4k | 
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| 2021-03-05 | 
Luke Kenneth...  | rename sram_4k wishbone interface to actually like...  | 
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| 2021-03-05 | 
Jean-Paul Chaput | Added support files for ls180+SRAM on TSMC 180nm. | 
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| 2021-03-03 | 
Luke Kenneth...  | add blackbox attribute manually to SPBlock_512W64B8W | 
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| 2021-03-02 | 
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922...  | 
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| 2021-03-02 | 
Jean-Paul Chaput | First working power plane in experiment12. | 
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| 2021-02-20 | 
Luke Kenneth...  | add 4k sram build | 
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| 2021-02-20 | 
Luke Kenneth...  | increase core size to 50000 (DFF SRAMs) | 
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| 2021-02-20 | 
Luke Kenneth...  | expand core size to 28000 | 
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| 2021-02-17 | 
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922...  | 
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| 2021-02-17 | 
Jean-Paul Chaput | First working integration of a SRAM block. | 
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| 2021-02-02 | 
Luke Kenneth...  | whitespace | 
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| 2021-02-02 | 
Luke Kenneth...  | whitespace | 
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| 2021-02-01 | 
Jean-Paul Chaput | Netlist integration of the SRAM OK. Layout in progress. | 
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| 2021-01-28 | 
Jean-Paul Chaput | Working bench design with SRAM in top block. | 
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| 2021-01-27 | 
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922...  | 
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| 2021-01-27 | 
Jean-Paul Chaput | Pinmux loading is now integrated in Coriolis. | 
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| 2021-01-15 | 
Luke Kenneth...  | add new Memory experiments13  ls180-24jan2020 | 
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| 2020-12-22 | 
Luke Kenneth...  | add SPBlock_512W64B8W to memory.py | 
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| 2020-12-22 | 
Luke Kenneth...  | rename to memory from add | 
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| 2020-12-22 | 
Luke Kenneth...  | add copy of experiments4 to create memory example | 
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| 2020-12-04 | 
Luke Kenneth...  | increase core size (again) to cope with DFFs currently...  | 
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| 2020-12-04 | 
Luke Kenneth...  | Revert "very weird bug where CoreToChip.buildChip canno...  | 
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| 2020-12-03 | 
Luke Kenneth...  | very weird bug where CoreToChip.buildChip cannot find...  | 
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| 2020-12-03 | 
Luke Kenneth...  | increase size to 45,000 to cope with 3x extra SRAMs | 
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| 2020-12-03 | 
Luke Kenneth...  | experiment adding 3x extra SRAMs back in but still...  | 
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| 2020-12-03 | 
Luke Kenneth...  | wtf does 32/64 bit bus have to do with gpio_o(8) disapp...  | 
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| 2020-12-03 | 
Luke Kenneth...  | reduce mem width due to yosys bugs.  sigh | 
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| 2020-12-03 | 
Luke Kenneth...  | added 3 more 4k SRAMs | 
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| 2020-12-02 | 
Luke Kenneth...  | increase size to 40,000 | 
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| 2020-12-02 | 
Luke Kenneth...  | begin random search for appropriate core size.  start...  | 
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| 2020-12-02 | 
Luke Kenneth...  | add full core back in | 
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| 2020-11-30 | 
Luke Kenneth...  | update submodule for ls180 pinmux, iopad vss/vdd invers...   partial-core-ls180-gdsii | 
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| 2020-11-30 | 
Jean-Paul Chaput | Added experiments11, base for full chip with FlexLib...  | 
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| 2020-11-27 | 
Luke Kenneth...  | add comment do not use build.sh | 
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| 2020-11-14 | 
Luke Kenneth...  | update ls180 litex interfaces | 
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| 2020-11-14 | 
Luke Kenneth...  | get rid of ibus/dbus/xics advanced wishbone tags | 
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| 2020-11-14 | 
Luke Kenneth...  | update litex direction of iopads in ls180 | 
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| 2020-11-13 | 
Luke Kenneth...  | corona-core gap too small | 
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| 2020-11-13 | 
Luke Kenneth...  | increase core size yet again, shrink gap | 
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| 2020-11-13 | 
Luke Kenneth...  | increase core size, reduce corona gap again | 
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| 2020-11-13 | 
Luke Kenneth...  | reduce nc ls180 pins to match | 
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| 2020-11-13 | 
Luke Kenneth...  | increase chip size by 100, make chipSize closer to...  | 
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| 2020-11-13 | 
Luke Kenneth...  | fix clk_sel width (2 not 3) | 
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| 2020-11-13 | 
Luke Kenneth...  | trying to get yosys to stop destroying pll_lck_o signal | 
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| 2020-11-13 | 
Luke Kenneth...  | trying to get yosys to stop destroying pll_lck_o signal | 
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| 2020-11-13 | 
Luke Kenneth...  | update full core ls180 (actually with litex peripherals...  | 
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| 2020-11-13 | 
Luke Kenneth...  | test of litex peripherals back in (not full core) | 
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| 2020-11-12 | 
Luke Kenneth...  | get core size big enough to fit pads along width | 
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| 2020-11-12 | 
Luke Kenneth...  | remove niolib io_in/out signal, no longer needed | 
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| 2020-11-12 | 
Luke Kenneth...  | remove io_in/io_out from niolib experiments10 | 
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| 2020-11-11 | 
Luke Kenneth...  | submodule update | 
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| 2020-11-11 | 
Luke Kenneth...  | adjust chip/core size to try to fit ls180 core/pads | 
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| 2020-11-11 | 
Luke Kenneth...  | add power/ground pads | 
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| 2020-11-11 | 
Luke Kenneth...  | update CLKSEL / PLLOCK pins for ls180 | 
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| 2020-11-09 | 
Luke Kenneth...  | add code comments for ioring-to-niolib conversion of...  | 
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| 2020-11-08 | 
Luke Kenneth...  | start conversion of ls180 to new niolib | 
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| 2020-11-07 | 
Luke Kenneth...  | add io_in/io_out zero/one to help transition to new...  | 
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| 2020-11-07 | 
Luke Kenneth...  | messing about to get non_generated ls180.vst running...  | 
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| 2020-11-07 | 
Luke Kenneth...  | update full ls180 core | 
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| 2020-11-05 | 
Luke Kenneth...  | update to "full" core | 
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| 2020-11-05 | 
Luke Kenneth...  | add build scripts for ls180 | 
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| 2020-11-04 | 
Luke Kenneth...  | minor reformat of spec, whitespace | 
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| next |