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soc.git
2020-07-22 Luke Kenneth... missed import of Builder, set cpu_type to "None" tempor... commit | commitdiff | tree
2020-07-22 Luke Kenneth... begin converting litex sim to libre-soc commit | commitdiff | tree
2020-07-22 Luke Kenneth... whoops forgot field accessor commit | commitdiff | tree
2020-07-22 Luke Kenneth... do not use wildcard import commit | commitdiff | tree
2020-07-22 Luke Kenneth... start from vexriscv sim.py from commit | commitdiff | tree
2020-07-22 Luke Kenneth... correct syntax error commit | commitdiff | tree
2020-07-22 Luke Kenneth... first version of litex core (to be submitted upstream... commit | commitdiff | tree
2020-07-22 Luke Kenneth... whoops typo, 63-start not 3-start (doh) commit | commitdiff | tree
2020-07-22 Luke Kenneth... field number ordering wrong way round? commit | commitdiff | tree
2020-07-22 Luke Kenneth... syntax error commit | commitdiff | tree
2020-07-22 Luke Kenneth... review trap main_stage.py modifications: we are not... commit | commitdiff | tree
2020-07-22 Luke Kenneth... comments, add page spec numbers for branch ops into... commit | commitdiff | tree
2020-07-22 Luke Kenneth... add comment headings with spec page numbers commit | commitdiff | tree
2020-07-22 Luke Kenneth... comment on op.insn ordering commit | commitdiff | tree
2020-07-22 Luke Kenneth... code-shuffle, add comments commit | commitdiff | tree
2020-07-22 Luke Kenneth... add TT.size and use it in PowerDecoder and trap input... commit | commitdiff | tree
2020-07-22 Luke Kenneth... inline comments in trap proof commit | commitdiff | tree
2020-07-22 Luke Kenneth... note that traptype MUST increase in bitwidth correspond... commit | commitdiff | tree
2020-07-22 Luke Kenneth... fix branch main_stage proof, add ctr 32-bit, fix BCREG commit | commitdiff | tree
2020-07-22 Luke Kenneth... rework branch proof to use br_input_record commit | commitdiff | tree
2020-07-22 Luke Kenneth... update README for pipe_data.py commit | commitdiff | tree
2020-07-22 Luke Kenneth... reduce number of FastRegs read ports commit | commitdiff | tree
2020-07-22 Luke Kenneth... comments on what goes into CommonPipeSpec commit | commitdiff | tree
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions. commit | commitdiff | tree
2020-07-22 Samuel A. Falvo IIPEP8 compliance commit | commitdiff | tree
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage commit | commitdiff | tree
2020-07-22 Jacob Lifshayfix test_div_state_fsm commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IICompleted SC FV properties commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties. commit | commitdiff | tree
2020-07-21 Luke Kenneth... convert branch pipeline to use msr/cia as immediates commit | commitdiff | tree
2020-07-21 Luke Kenneth... put set_msr and set_cia back in for now commit | commitdiff | tree
2020-07-21 Luke Kenneth... interesting bug in test_compunit.py when there are... commit | commitdiff | tree
2020-07-21 Luke Kenneth... testing if MultiCompUnit can handle no input regs ... commit | commitdiff | tree
2020-07-21 Luke Kenneth... disable cxxsim for now commit | commitdiff | tree
2020-07-21 Luke Kenneth... move cia and msr to trap input record commit | commitdiff | tree
2020-07-21 Luke Kenneth... set ISACaller.msr rather than namespace[MSR] commit | commitdiff | tree
2020-07-21 Luke Kenneth... when running an exception (trap) after "reset" must... commit | commitdiff | tree
2020-07-21 Luke Kenneth... spurious imports of FHDLTestCase, should be from nmutil commit | commitdiff | tree
2020-07-21 Luke Kenneth... whitespace commit | commitdiff | tree
2020-07-21 Luke Kenneth... add PC (CIA) to PowerDecode2 "state" for passing into... commit | commitdiff | tree
2020-07-21 Luke Kenneth... add msr exception bits setting function in hardware commit | commitdiff | tree
2020-07-21 Luke Kenneth... make cxxsim optional and print warning commit | commitdiff | tree
2020-07-21 Luke Kenneth... corrections to trap proof see commit | commitdiff | tree
2020-07-21 Luke Kenneth... use alias for msr_i in trap proof commit | commitdiff | tree
2020-07-21 Luke Kenneth... correct trap spec page interrupt ref commit | commitdiff | tree
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style commit | commitdiff | tree
2020-07-20 Samuel A. Falvo IIFormal properties for RFID. commit | commitdiff | tree
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op. commit | commitdiff | tree
2020-07-20 Cesar StraussRemove extra yield from test case. commit | commitdiff | tree
2020-07-19 Luke Kenneth... do not start core in terminated mode commit | commitdiff | tree
2020-07-19 Luke Kenneth... explicitly set up a pc_i_ok signal in test_microwatt.py commit | commitdiff | tree
2020-07-19 Luke Kenneth... expose core_stop_i to outside as well commit | commitdiff | tree
2020-07-19 Luke Kenneth... set go_insn_i to non-resetless commit | commitdiff | tree
2020-07-19 Luke Kenneth... add issuer verilog generator commit | commitdiff | tree
2020-07-19 Luke Kenneth... update to expose signals at top-level of issuer commit | commitdiff | tree
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu... commit | commitdiff | tree
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu... commit | commitdiff | tree
2020-07-19 Luke Kenneth... use same write_vcd for cxxsim as pysim commit | commitdiff | tree
2020-07-19 Luke Kenneth... fix bug in alu_fsm.py found by cxxsim: missing one... commit | commitdiff | tree
2020-07-19 Luke Kenneth... add some CompUnit demo tests of the alu_fsm example commit | commitdiff | tree
2020-07-19 Luke Kenneth... move sdir to CompFSMOpSubset in alu_fsm example commit | commitdiff | tree
2020-07-19 Luke Kenneth... add CompFSMOpSubset, also change dir to sdir commit | commitdiff | tree
2020-07-19 Luke Kenneth... remove unneeded import commit | commitdiff | tree
2020-07-19 Luke Kenneth... if nmigen.sim.pysim import fails use nmigen.back.pysim commit | commitdiff | tree
2020-07-19 Luke Kenneth... use iocontrol PrevControl / NextControl instead of... commit | commitdiff | tree
2020-07-19 Luke Kenneth... add DivTestCase to test_issuer.py (commented out for... commit | commitdiff | tree
2020-07-19 Cesar StraussImplement control path and unit test. commit | commitdiff | tree
2020-07-18 Luke Kenneth... worked out that DivPipeSpec can be given a default... commit | commitdiff | tree
2020-07-18 Luke Kenneth... missing conversion of DIV to Div commit | commitdiff | tree
2020-07-18 Luke Kenneth... add option to generate verilog commit | commitdiff | tree
2020-07-18 Luke Kenneth... whoops use slice not range commit | commitdiff | tree
2020-07-18 Luke Kenneth... syntax error commit | commitdiff | tree
2020-07-18 Cesar StraussImplement the Shifter data path commit | commitdiff | tree
2020-07-18 Cesar StraussDocument move of the next port data commit | commitdiff | tree
2020-07-18 Luke Kenneth... add SR latch cxxrtl backend demo commit | commitdiff | tree
2020-07-18 Luke Kenneth... add comment and copy of pseudo-code for OP_RFID into... commit | commitdiff | tree
2020-07-18 Luke Kenneth... review of OP_RFID showed up some errors commit | commitdiff | tree
2020-07-18 Luke Kenneth... corrections to trap main_stage.py OP_RFID according... commit | commitdiff | tree
2020-07-18 Samuel A. Falvo IIWIP: FV failing for unknown reasons. commit | commitdiff | tree
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests commit | commitdiff | tree
2020-07-18 Samuel A. Falvo IIFailing test: fast1/fast2 vs srr0/srr1? on trap pipe commit | commitdiff | tree
2020-07-18 Samuel A. Falvo IIforgot to clean up workspace in source commit | commitdiff | tree
2020-07-18 Samuel A. Falvo IIFV props for SC instruction commit | commitdiff | tree
2020-07-17 Samuel A. Falvo IIFirst FV property for trap unit commit | commitdiff | tree
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-07-17 Jacob Lifshaystart adding FSMDivCore* commit | commitdiff | tree
2020-07-17 Luke Kenneth... comment explaining why not to call self.trap in PowerDe... commit | commitdiff | tree
2020-07-17 Luke Kenneth... likewise cut across latest Minerva loadstore with line... commit | commitdiff | tree
2020-07-17 Luke Kenneth... sigh easier to just do a line-for-line comparison of... commit | commitdiff | tree
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-07-17 Luke Kenneth... port minerva cache fixes commit | commitdiff | tree
2020-07-17 Jacob Lifshayadd .pylintrc commit | commitdiff | tree
2020-07-17 Luke Kenneth... forward-port minerva loadstore bugfix commit | commitdiff | tree
2020-07-17 Luke Kenneth... comments commit | commitdiff | tree
2020-07-17 Luke Kenneth... submodule update (again. sigh) commit | commitdiff | tree
2020-07-17 Luke Kenneth... whitespace commit | commitdiff | tree
2020-07-17 Luke Kenneth... use convenience vars in spr proof commit | commitdiff | tree
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