| 2021-04-24 |
Jean-Paul Chaput | Forgot to update experiments9 doDesign file for FreePDK 45. |
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| 2021-04-24 |
Jean-Paul Chaput | Keep in synch with the latest Coriolis. SRAM models... |
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| 2021-04-24 |
Jean-Paul Chaput | Correct settings for experiment10_verilog & FreePDK45. |
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| 2021-04-20 |
Luke Kenneth... | manually comment out pll and sdcard pins |
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| 2021-04-19 |
Staf Verhaegen | experiments10_verilog/freepdk_c4m45: Add link for add.py. |
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| 2021-04-19 |
Staf Verhaegen | Top layer -> metal6 |
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| 2021-04-19 |
Staf Verhaegen | experiments9/freepdk_c4m45: Reduce core size. |
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| 2021-04-19 |
Luke Kenneth... | add SPBlock512 instance generator |
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| 2021-04-19 |
Luke Kenneth... | code-comments |
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| 2021-04-19 |
Luke Kenneth... | add two SRAMs, document how to do more |
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| 2021-04-18 |
Luke Kenneth... | argh, found the blackbox problem: yosys is "doing the... |
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| 2021-04-18 |
Luke Kenneth... | try renaming spblock without the underscore |
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| 2021-04-18 |
Luke Kenneth... | try changing layout of blackbox spblock_512w64b8w |
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| 2021-04-18 |
Luke Kenneth... | experimenting with blackboxes |
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| 2021-04-18 |
Luke Kenneth... | rename spblock_512w64b8w, and vco_test_ana for pll |
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| 2021-04-18 |
Luke Kenneth... | rename blackboxes to lowercase, spblock_512w64b8w, pll |
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| 2021-04-18 |
Luke Kenneth... | update ls180 sram4k |
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| 2021-04-18 |
Luke Kenneth... | add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst... |
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| 2021-04-18 |
Luke Kenneth... | must use VST_FLAGS uniquify uppercase |
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| 2021-04-18 |
Luke Kenneth... | sort out adding SPBlock_512 SRAM verilog to ls180 |
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| 2021-04-18 |
Luke Kenneth... | update tsmc_018 4k build script |
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| 2021-04-18 |
Luke Kenneth... | use correct arguments to litex build to create 4k srams... |
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| 2021-04-18 |
Luke Kenneth... | rename ls180sram4k to ls180 |
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| 2021-04-18 |
Luke Kenneth... | add full core variant including 4k sram of ls180 |
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| 2021-04-18 |
Luke Kenneth... | update libresoc.v, c4m-jtag fsm was renamed |
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| 2021-04-18 |
Luke Kenneth... | update libresoc.v, c4m-jtag fsm was renamed |
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| 2021-04-14 |
Luke Kenneth... | add an SRAM and wishbone to add test (makes it bigger) |
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| 2021-04-14 |
Luke Kenneth... | connect up boundary scan to inputs/outputs |
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| 2021-04-13 |
Luke Kenneth... | submodule update |
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| 2021-04-13 |
Luke Kenneth... | use METAL10 for topRoutingLayer |
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| 2021-04-13 |
Luke Kenneth... | whoops forgot settings.py |
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| 2021-04-12 |
Luke Kenneth... | submodule update |
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| 2021-04-12 |
Luke Kenneth... | set routingGauge manually |
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| 2021-04-12 |
Luke Kenneth... | enable HFNS in adder |
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| 2021-04-12 |
Luke Kenneth... | include (but do not use) FreePDK45 in experiments10 |
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| 2021-04-12 |
Luke Kenneth... | different FreePDK45 experiments10 chip size |
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| 2021-04-12 |
Luke Kenneth... | experimentation to get experiment10_verilog work with... |
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| 2021-04-12 |
Luke Kenneth... | add FreePDK45 experiments10_verilog doDesign.py |
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| 2021-04-12 |
Luke Kenneth... | add FreePDK45 variant of experiments10_verilog |
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| 2021-04-12 |
Luke Kenneth... | update PLL signal output names |
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| 2021-04-12 |
Staf Verhaegen | doDesign.py: Disable SRAM placement |
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| 2021-04-12 |
Staf Verhaegen | Reduce core size. |
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| 2021-04-12 |
Luke Kenneth... | rename sys_clk in adder test experiments10_verilog... |
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| 2021-04-12 |
Luke Kenneth... | rename JTAG port in adder test experiments10_verilog... |
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| 2021-04-12 |
Luke Kenneth... | back to "working" verilog add |
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| 2021-04-12 |
Luke Kenneth... | another attempt to get 100% completed route |
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| 2021-04-12 |
Staf Verhaegen | Right branch of c4m-pdk-freedpk45. |
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| 2021-04-11 |
Luke Kenneth... | good grief, increasing ls180 core size to 70,000, 100... |
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| 2021-04-11 |
Luke Kenneth... | increase core size to see if global routing can be... |
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| 2021-04-11 |
Luke Kenneth... | whitespace cleanup |
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| 2021-04-11 |
Luke Kenneth... | use auto-generated pinmux ioPadsSpecs |
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| 2021-04-11 |
Luke Kenneth... | submodule conflict (update again) |
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| 2021-04-11 |
Luke Kenneth... | use verilog version of ls180 in FreePDK_c4m45 |
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| 2021-04-11 |
Staf Verhaegen | Update c4m-pdk-freepdk45 submodule. |
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| 2021-04-11 |
Luke Kenneth... | crank up the numbers (again) |
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| 2021-04-11 |
Staf Verhaegen | Wip of P&R of ls180 with C4M FreePDK45. |
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| 2021-04-11 |
Staf Verhaegen | experiments9: Ignore pinmux generated files. |
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| 2021-04-11 |
Staf Verhaegen | mksym.sh: Check exitence of alliance-check-toolkit |
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| 2021-04-11 |
Staf Verhaegen | Submodule for C4M FreePDK45 PDK release files. |
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| 2021-04-11 |
Luke Kenneth... | crank up the numbers to see if routing completion can... |
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| 2021-04-11 |
Luke Kenneth... | increase katana tracks reserved |
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| 2021-04-10 |
Luke Kenneth... | use verilog for ls180 instead of ilang |
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| 2021-04-10 |
Luke Kenneth... | make VST names unique, for GHDL to cope |
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| 2021-04-09 |
Luke Kenneth... | sigh, broken experiment10_verilog |
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| 2021-04-09 |
Luke Kenneth... | whitespace |
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| 2021-04-09 |
Luke Kenneth... | whitespace cleanup |
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| 2021-04-09 |
Luke Kenneth... | pad name starts with p_ |
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| 2021-04-09 |
Luke Kenneth... | rename design of experiments10 to match ls180 chip... |
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| 2021-04-02 |
Luke Kenneth... | experiment with nmigen verilog generation |
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| 2021-04-01 |
Luke Kenneth... | update / refresh full core DFF |
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| 2021-04-01 |
Luke Kenneth... | update / refresh full core DFF |
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| 2021-04-01 |
Luke Kenneth... | run doChipFloorplan in experiments10 |
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| 2021-04-01 |
Luke Kenneth... | increase experiment10 JTAG tap width to 4 |
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| 2021-04-01 |
Luke Kenneth... | update submodule |
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| 2021-03-30 |
Luke Kenneth... | update 4k SRAM ls180.il |
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| 2021-03-30 |
Luke Kenneth... | add yosys version number |
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| 2021-03-29 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-03-29 |
Jean-Paul Chaput | Add a placeholder for the PLL in the doDesign.py for... |
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| 2021-03-29 |
Luke Kenneth... | Revert "enable high fanout in ls180 experiment9 doDesig... |
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| 2021-03-29 |
Luke Kenneth... | enable high fanout in ls180 experiment9 doDesign.py |
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| 2021-03-29 |
Luke Kenneth... | aaagh found bug in litex setup, 64 bit WB bus was truncated |
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| 2021-03-28 |
Luke Kenneth... | reduce SPR regfile size considerably |
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| 2021-03-28 |
Luke Kenneth... | reduce INT and FAST regfile sizes by sharing ports |
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| 2021-03-27 |
Luke Kenneth... | add missing floorplan function call |
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| 2021-03-27 |
Luke Kenneth... | hooray, corrected pinouts |
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| 2021-03-27 |
Luke Kenneth... | really weird error "unsupported direction for eint... |
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| 2021-03-23 |
Jean-Paul Chaput | Uodated doDesign for the latest ls180 (sram variant). |
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| 2021-03-22 |
Luke Kenneth... | increase DFF RAM size slightly |
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| 2021-03-22 |
Luke Kenneth... | add very small DFF srams variant |
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| 2021-03-22 |
Luke Kenneth... | create small dff with 4x 4k SRAMs |
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| 2021-03-22 |
Luke Kenneth... | ls180.il update |
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| 2021-03-22 |
Luke Kenneth... | argh pinmux generating bi-directional SDR DM when it... |
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| 2021-03-18 |
Luke Kenneth... | update ls180.il |
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| 2021-03-16 |
Luke Kenneth... | update submodule |
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| 2021-03-16 |
Luke Kenneth... | update ls180.il 4ksram with correct sdram connections |
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| 2021-03-16 |
Jean-Paul Chaput | Add experiment9/symbolic to test the multiple drivers... |
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| 2021-03-14 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-03-14 |
Jean-Paul Chaput | Adjusted doDesign.py scripts to use Chip.doChipFloorplan(). |
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| 2021-03-11 |
Luke Kenneth... | try alternative pad/core connection |
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| 2021-03-09 |
Jean-Paul Chaput | Forgot the Makefile, stupid! |
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