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soc.git
2020-07-24 Luke Kenneth... bug found in pseudocode reader when assembly code has... commit | commitdiff | tree
2020-07-24 Luke Kenneth... submodule update commit | commitdiff | tree
2020-07-24 Luke Kenneth... code review comments for trap and proof commit | commitdiff | tree
2020-07-24 Luke Kenneth... made it clear what is meant by the slice numbering... commit | commitdiff | tree
2020-07-24 Samuel A. Falvo IIRefactorin of common code commit | commitdiff | tree
2020-07-24 Samuel A. Falvo IIAddress code review comments commit | commitdiff | tree
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller commit | commitdiff | tree
2020-07-24 Jacob Lifshayadd power-instruction-analyzer as a dependency commit | commitdiff | tree
2020-07-24 Jacob Lifshayformat commit | commitdiff | tree
2020-07-23 Luke Kenneth... syntax error commit | commitdiff | tree
2020-07-23 Luke Kenneth... support 32-bit mem width setting commit | commitdiff | tree
2020-07-23 Luke Kenneth... try SDRAM SDR commit | commitdiff | tree
2020-07-23 Luke Kenneth... allow imem to be 64/32 bit wide commit | commitdiff | tree
2020-07-23 Luke Kenneth... begin core in running state commit | commitdiff | tree
2020-07-23 Luke Kenneth... try different MEMTEST_xxx sizes with 64 bit bus width commit | commitdiff | tree
2020-07-23 Cole PoirierUpdate libreriscv HDL_workflow/coriolis2 commit | commitdiff | tree
2020-07-23 Jacob Lifshayadd all div* and mod* instructions to test_pipe_caller commit | commitdiff | tree
2020-07-22 Jacob Lifshayworking on fsm commit | commitdiff | tree
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' commit | commitdiff | tree
2020-07-22 Jacob Lifshayformat code commit | commitdiff | tree
2020-07-22 Luke Kenneth... re-add CRG (clock reset generator) commit | commitdiff | tree
2020-07-22 Luke Kenneth... missing ports from issuer, when doing verilog commit | commitdiff | tree
2020-07-22 Luke Kenneth... add clock domain using snippet taken from random file commit | commitdiff | tree
2020-07-22 Luke Kenneth... cleanup in litex core.py commit | commitdiff | tree
2020-07-22 Luke Kenneth... update comments commit | commitdiff | tree
2020-07-22 Luke Kenneth... add dummy irq set/get commit | commitdiff | tree
2020-07-22 Luke Kenneth... add boot-helper.S etc from microwatt litex core commit | commitdiff | tree
2020-07-22 Luke Kenneth... set additional MSR bits according to v3.0B spec when... commit | commitdiff | tree
2020-07-22 Luke Kenneth... use (new) MSRb and PIb which has auto-bigendian numbers commit | commitdiff | tree
2020-07-22 Luke Kenneth... sigh, auto-create some little/big-endian classes for... commit | commitdiff | tree
2020-07-22 Luke Kenneth... missed import of Builder, set cpu_type to "None" tempor... commit | commitdiff | tree
2020-07-22 Luke Kenneth... begin converting litex sim to libre-soc commit | commitdiff | tree
2020-07-22 Luke Kenneth... whoops forgot field accessor commit | commitdiff | tree
2020-07-22 Luke Kenneth... do not use wildcard import commit | commitdiff | tree
2020-07-22 Luke Kenneth... start from vexriscv sim.py from commit | commitdiff | tree
2020-07-22 Luke Kenneth... correct syntax error commit | commitdiff | tree
2020-07-22 Luke Kenneth... first version of litex core (to be submitted upstream... commit | commitdiff | tree
2020-07-22 Luke Kenneth... whoops typo, 63-start not 3-start (doh) commit | commitdiff | tree
2020-07-22 Luke Kenneth... field number ordering wrong way round? commit | commitdiff | tree
2020-07-22 Luke Kenneth... syntax error commit | commitdiff | tree
2020-07-22 Luke Kenneth... review trap main_stage.py modifications: we are not... commit | commitdiff | tree
2020-07-22 Luke Kenneth... comments, add page spec numbers for branch ops into... commit | commitdiff | tree
2020-07-22 Luke Kenneth... add comment headings with spec page numbers commit | commitdiff | tree
2020-07-22 Luke Kenneth... comment on op.insn ordering commit | commitdiff | tree
2020-07-22 Luke Kenneth... code-shuffle, add comments commit | commitdiff | tree
2020-07-22 Luke Kenneth... add TT.size and use it in PowerDecoder and trap input... commit | commitdiff | tree
2020-07-22 Luke Kenneth... inline comments in trap proof commit | commitdiff | tree
2020-07-22 Luke Kenneth... note that traptype MUST increase in bitwidth correspond... commit | commitdiff | tree
2020-07-22 Luke Kenneth... fix branch main_stage proof, add ctr 32-bit, fix BCREG commit | commitdiff | tree
2020-07-22 Luke Kenneth... rework branch proof to use br_input_record commit | commitdiff | tree
2020-07-22 Luke Kenneth... update README for pipe_data.py commit | commitdiff | tree
2020-07-22 Luke Kenneth... reduce number of FastRegs read ports commit | commitdiff | tree
2020-07-22 Luke Kenneth... comments on what goes into CommonPipeSpec commit | commitdiff | tree
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions. commit | commitdiff | tree
2020-07-22 Samuel A. Falvo IIPEP8 compliance commit | commitdiff | tree
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage commit | commitdiff | tree
2020-07-22 Jacob Lifshayfix test_div_state_fsm commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IICompleted SC FV properties commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from commit | commitdiff | tree
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties. commit | commitdiff | tree
2020-07-21 Luke Kenneth... convert branch pipeline to use msr/cia as immediates commit | commitdiff | tree
2020-07-21 Luke Kenneth... put set_msr and set_cia back in for now commit | commitdiff | tree
2020-07-21 Luke Kenneth... interesting bug in test_compunit.py when there are... commit | commitdiff | tree
2020-07-21 Luke Kenneth... testing if MultiCompUnit can handle no input regs ... commit | commitdiff | tree
2020-07-21 Luke Kenneth... disable cxxsim for now commit | commitdiff | tree
2020-07-21 Luke Kenneth... move cia and msr to trap input record commit | commitdiff | tree
2020-07-21 Luke Kenneth... set ISACaller.msr rather than namespace[MSR] commit | commitdiff | tree
2020-07-21 Luke Kenneth... when running an exception (trap) after "reset" must... commit | commitdiff | tree
2020-07-21 Luke Kenneth... spurious imports of FHDLTestCase, should be from nmutil commit | commitdiff | tree
2020-07-21 Luke Kenneth... whitespace commit | commitdiff | tree
2020-07-21 Luke Kenneth... add PC (CIA) to PowerDecode2 "state" for passing into... commit | commitdiff | tree
2020-07-21 Luke Kenneth... add msr exception bits setting function in hardware commit | commitdiff | tree
2020-07-21 Luke Kenneth... make cxxsim optional and print warning commit | commitdiff | tree
2020-07-21 Luke Kenneth... corrections to trap proof see commit | commitdiff | tree
2020-07-21 Luke Kenneth... use alias for msr_i in trap proof commit | commitdiff | tree
2020-07-21 Luke Kenneth... correct trap spec page interrupt ref commit | commitdiff | tree
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style commit | commitdiff | tree
2020-07-20 Samuel A. Falvo IIFormal properties for RFID. commit | commitdiff | tree
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op. commit | commitdiff | tree
2020-07-20 Cesar StraussRemove extra yield from test case. commit | commitdiff | tree
2020-07-19 Luke Kenneth... do not start core in terminated mode commit | commitdiff | tree
2020-07-19 Luke Kenneth... explicitly set up a pc_i_ok signal in test_microwatt.py commit | commitdiff | tree
2020-07-19 Luke Kenneth... expose core_stop_i to outside as well commit | commitdiff | tree
2020-07-19 Luke Kenneth... set go_insn_i to non-resetless commit | commitdiff | tree
2020-07-19 Luke Kenneth... add issuer verilog generator commit | commitdiff | tree
2020-07-19 Luke Kenneth... update to expose signals at top-level of issuer commit | commitdiff | tree
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu... commit | commitdiff | tree
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu... commit | commitdiff | tree
2020-07-19 Luke Kenneth... use same write_vcd for cxxsim as pysim commit | commitdiff | tree
2020-07-19 Luke Kenneth... fix bug in alu_fsm.py found by cxxsim: missing one... commit | commitdiff | tree
2020-07-19 Luke Kenneth... add some CompUnit demo tests of the alu_fsm example commit | commitdiff | tree
2020-07-19 Luke Kenneth... move sdir to CompFSMOpSubset in alu_fsm example commit | commitdiff | tree
2020-07-19 Luke Kenneth... add CompFSMOpSubset, also change dir to sdir commit | commitdiff | tree
2020-07-19 Luke Kenneth... remove unneeded import commit | commitdiff | tree
2020-07-19 Luke Kenneth... if nmigen.sim.pysim import fails use nmigen.back.pysim commit | commitdiff | tree
2020-07-19 Luke Kenneth... use iocontrol PrevControl / NextControl instead of... commit | commitdiff | tree
2020-07-19 Luke Kenneth... add DivTestCase to test_issuer.py (commented out for... commit | commitdiff | tree
2020-07-19 Cesar StraussImplement control path and unit test. commit | commitdiff | tree
2020-07-18 Luke Kenneth... worked out that DivPipeSpec can be given a default... commit | commitdiff | tree
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