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soc.git
2020-07-22
Luke Kenneth...
begin converting litex sim to libre-soc
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2020-07-22
Luke Kenneth...
whoops forgot field accessor
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2020-07-22
Luke Kenneth...
do not use wildcard import
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2020-07-22
Luke Kenneth...
start from vexriscv sim.py from
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2020-07-22
Luke Kenneth...
correct syntax error
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2020-07-22
Luke Kenneth...
first version of litex core (to be submitted upstream...
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2020-07-22
Luke Kenneth...
whoops typo, 63-start not 3-start (doh)
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2020-07-22
Luke Kenneth...
field number ordering wrong way round?
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2020-07-22
Luke Kenneth...
syntax error
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2020-07-22
Luke Kenneth...
review trap main_stage.py modifications: we are not...
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2020-07-22
Luke Kenneth...
comments, add page spec numbers for branch ops into...
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2020-07-22
Luke Kenneth...
add comment headings with spec page numbers
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2020-07-22
Luke Kenneth...
comment on op.insn ordering
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2020-07-22
Luke Kenneth...
code-shuffle, add comments
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2020-07-22
Luke Kenneth...
add TT.size and use it in PowerDecoder and trap input...
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2020-07-22
Luke Kenneth...
inline comments in trap proof
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2020-07-22
Luke Kenneth...
note that traptype MUST increase in bitwidth correspond...
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2020-07-22
Luke Kenneth...
fix branch main_stage proof, add ctr 32-bit, fix BCREG
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2020-07-22
Luke Kenneth...
rework branch proof to use br_input_record
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2020-07-22
Luke Kenneth...
update README for pipe_data.py
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2020-07-22
Luke Kenneth...
reduce number of FastRegs read ports
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2020-07-22
Luke Kenneth...
comments on what goes into CommonPipeSpec
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2020-07-22
Samuel A. Falvo II
Complete FV properties for OP_TRAP instructions.
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2020-07-22
Samuel A. Falvo II
PEP8 compliance
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2020-07-22
Jacob Lifshay
working on FSMDivCoreStage
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2020-07-22
Jacob Lifshay
fix test_div_state_fsm
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2020-07-21
Samuel A. Falvo II
Completed SC FV properties
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2020-07-21
Samuel A. Falvo II
Refine properties to comply with spec
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2020-07-21
Samuel A. Falvo II
Fix where msr_i gets its value from
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2020-07-21
Samuel A. Falvo II
Merge in recent updates to TRAP FV properties.
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2020-07-21
Luke Kenneth...
convert branch pipeline to use msr/cia as immediates
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2020-07-21
Luke Kenneth...
put set_msr and set_cia back in for now
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2020-07-21
Luke Kenneth...
interesting bug in test_compunit.py when there are...
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2020-07-21
Luke Kenneth...
testing if MultiCompUnit can handle no input regs ...
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2020-07-21
Luke Kenneth...
disable cxxsim for now
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2020-07-21
Luke Kenneth...
move cia and msr to trap input record
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2020-07-21
Luke Kenneth...
set ISACaller.msr rather than namespace[MSR]
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2020-07-21
Luke Kenneth...
when running an exception (trap) after "reset" must...
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2020-07-21
Luke Kenneth...
spurious imports of FHDLTestCase, should be from nmutil
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2020-07-21
Luke Kenneth...
whitespace
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2020-07-21
Luke Kenneth...
add PC (CIA) to PowerDecode2 "state" for passing into...
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2020-07-21
Luke Kenneth...
add msr exception bits setting function in hardware
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2020-07-21
Luke Kenneth...
make cxxsim optional and print warning
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2020-07-21
Luke Kenneth...
corrections to trap proof see
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2020-07-21
Luke Kenneth...
use alias for msr_i in trap proof
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2020-07-21
Luke Kenneth...
correct trap spec page interrupt ref
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2020-07-20
Samuel A. Falvo II
Rework SC properties to conform to style
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2020-07-20
Samuel A. Falvo II
Formal properties for RFID.
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2020-07-20
Cesar Strauss
Document the move of sdir from data_i to op.
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2020-07-20
Cesar Strauss
Remove extra yield from test case.
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2020-07-19
Luke Kenneth...
do not start core in terminated mode
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2020-07-19
Luke Kenneth...
explicitly set up a pc_i_ok signal in test_microwatt.py
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2020-07-19
Luke Kenneth...
expose core_stop_i to outside as well
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2020-07-19
Luke Kenneth...
set go_insn_i to non-resetless
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2020-07-19
Luke Kenneth...
add issuer verilog generator
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2020-07-19
Luke Kenneth...
update to expose signals at top-level of issuer
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2020-07-19
Luke Kenneth...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth...
use same write_vcd for cxxsim as pysim
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2020-07-19
Luke Kenneth...
fix bug in alu_fsm.py found by cxxsim: missing one...
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2020-07-19
Luke Kenneth...
add some CompUnit demo tests of the alu_fsm example
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2020-07-19
Luke Kenneth...
move sdir to CompFSMOpSubset in alu_fsm example
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2020-07-19
Luke Kenneth...
add CompFSMOpSubset, also change dir to sdir
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2020-07-19
Luke Kenneth...
remove unneeded import
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2020-07-19
Luke Kenneth...
if nmigen.sim.pysim import fails use nmigen.back.pysim
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2020-07-19
Luke Kenneth...
use iocontrol PrevControl / NextControl instead of...
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2020-07-19
Luke Kenneth...
add DivTestCase to test_issuer.py (commented out for...
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2020-07-19
Cesar Strauss
Implement control path and unit test.
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2020-07-18
Luke Kenneth...
worked out that DivPipeSpec can be given a default...
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2020-07-18
Luke Kenneth...
missing conversion of DIV to Div
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2020-07-18
Luke Kenneth...
add option to generate verilog
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2020-07-18
Luke Kenneth...
whoops use slice not range
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2020-07-18
Luke Kenneth...
syntax error
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2020-07-18
Cesar Strauss
Implement the Shifter data path
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2020-07-18
Cesar Strauss
Document move of the next port data
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2020-07-18
Luke Kenneth...
add SR latch cxxrtl backend demo
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2020-07-18
Luke Kenneth...
add comment and copy of pseudo-code for OP_RFID into...
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2020-07-18
Luke Kenneth...
review of OP_RFID showed up some errors
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2020-07-18
Luke Kenneth...
corrections to trap main_stage.py OP_RFID according...
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2020-07-18
Samuel A. Falvo II
WIP: FV failing for unknown reasons.
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2020-07-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-18
Jacob Lifshay
add div fsm core (`DivState*`) with tests
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2020-07-18
Samuel A. Falvo II
Failing test: fast1/fast2 vs srr0/srr1? on trap pipe
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2020-07-18
Samuel A. Falvo II
forgot to clean up workspace in source
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2020-07-18
Samuel A. Falvo II
FV props for SC instruction
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2020-07-17
Samuel A. Falvo II
First FV property for trap unit
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Jacob Lifshay
start adding FSMDivCore*
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2020-07-17
Luke Kenneth...
comment explaining why not to call self.trap in PowerDe...
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2020-07-17
Luke Kenneth...
likewise cut across latest Minerva loadstore with line...
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2020-07-17
Luke Kenneth...
sigh easier to just do a line-for-line comparison of...
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Luke Kenneth...
port minerva cache fixes
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2020-07-17
Jacob Lifshay
add .pylintrc
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2020-07-17
Luke Kenneth...
forward-port minerva loadstore bugfix
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2020-07-17
Luke Kenneth...
comments
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2020-07-17
Luke Kenneth...
submodule update (again. sigh)
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2020-07-17
Luke Kenneth...
whitespace
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2020-07-17
Luke Kenneth...
use convenience vars in spr proof
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2020-07-17
Samuel A. Falvo II
Flesh out SPR-related FV properties.
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