soc.git
2020-06-06 Luke Kenneth... set up LDSTCompUnit using regspec
2020-06-06 Luke Kenneth... add extra bugreport link
2020-06-06 Luke Kenneth... whitespace
2020-06-06 Luke Kenneth... whitespace indentation
2020-06-06 Luke Kenneth... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth... whoops dest%d_o not dest%d_i
2020-06-06 Luke Kenneth... add beginnings of LDST compunit test
2020-06-06 Luke Kenneth... whitespace
2020-06-06 Luke Kenneth... whitespace / code-munge
2020-06-06 Luke Kenneth... comments / whitespace
2020-06-06 Luke Kenneth... update stage docstring
2020-06-06 Luke Kenneth... code-munge
2020-06-06 Luke Kenneth... remove unneeded imports
2020-06-06 Luke Kenneth... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-05 Luke Kenneth... comment out CR assertion for now
2020-06-05 colepoirierAdded skeleton fu/trap/test/test_pipe_caller using
2020-06-05 colepoirierAdd trap_input_data.py for fu/trap, cookie-cut from
2020-06-05 Tobias Platenfix proof_datamerger (see 216#c56)
2020-06-05 Luke Kenneth... update comments
2020-06-05 Luke Kenneth... add comments and start of elaborate
2020-06-05 Luke Kenneth... more comments
2020-06-05 Luke Kenneth... more comments
2020-06-05 Luke Kenneth... a_i not b_in
2020-06-05 Luke Kenneth... add comments
2020-06-05 Luke Kenneth... experimenting with CR, not quite right
2020-06-05 colepoirierMade small changes to fu/trap/main_stage to bring nmige...
2020-06-05 Tobias Platenimplement init function of DualPortSplitter
2020-06-05 Tobias Platenuncomment rtlil.convert in test_l0_cache that causes...
2020-06-05 Luke Kenneth... whoops returning cr2 for cr3 regspec map
2020-06-05 Luke Kenneth... name regfile ports by name not numerical position
2020-06-05 Luke Kenneth... whoops connecting up CR in wrong order. fixing with...
2020-06-05 Luke Kenneth... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-05 Luke Kenneth... add TODO for MFSPR/MTSPR
2020-06-05 Luke Kenneth... refer to srr0/1 not a/b
2020-06-05 Luke Kenneth... add msr_copy function and use it in OP_TRAP, OP_RFID...
2020-06-05 Luke Kenneth... set SRR0 in OP_SC
2020-06-05 Luke Kenneth... add OP_RFID SRR0/SRR1 in PowerDecode2
2020-06-04 colepoirierUse a_i and b_i convenience variables instead of a...
2020-06-04 Luke Kenneth... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth... remove unneeded code
2020-06-04 Luke Kenneth... use common TestCase class in logical
2020-06-04 Luke Kenneth... add branch test case to core
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth... add both logical and ALU test core
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... no global variables in test suites
2020-06-04 Luke Kenneth... whoops, docstring indentation
2020-06-04 Luke Kenneth... add docstrings for read/write port connection
2020-06-04 Luke Kenneth... move core code into separate functions, for clarity
2020-06-04 Luke Kenneth... reduce amount of code in SelectableInt
2020-06-04 Luke Kenneth... oops forgot to switch write-enable off
2020-06-04 Luke Kenneth... comment clarify on core
2020-06-04 Luke Kenneth... initialise XER from simulation
2020-06-04 Luke Kenneth... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth... add extra argument (not used) to regfile.py
2020-06-04 Luke Kenneth... hmmm sync-delay wport write and wen
2020-06-04 Luke Kenneth... whitespace
2020-06-04 Luke Kenneth... test actual reg values being produced in core test
2020-06-04 Luke Kenneth... use common TestCase in branch
2020-06-04 Luke Kenneth... use common TestCase in shift_rot
2020-06-04 Luke Kenneth... use common TestCase in alu
2020-06-04 Luke Kenneth... move TestCase to common location
2020-06-04 Luke Kenneth... move reg setup to earlier in test
2020-06-04 Luke Kenneth... comment out wrflag as it should already be in the fu...
2020-06-04 Luke Kenneth... test against Logical (hard-coded change)
2020-06-04 Luke Kenneth... add first cut at test core
2020-06-04 Luke Kenneth... sync onto fu.go_wr_i otherwise a loop occurs
2020-06-04 Luke Kenneth... add rdmask and issue/busy setting
2020-06-04 Luke Kenneth... remove unneeded imports
2020-06-04 Luke Kenneth... use copy of FHDLTestCase
2020-06-04 Luke Kenneth... connect up write-ports from Regfiles to FUs
2020-06-04 Luke Kenneth... docstring for AllFunctionUnits
2020-06-04 Luke Kenneth... missing a fastregs write-port
2020-06-04 Luke Kenneth... update docstring on simple/core.py
2020-06-04 Luke Kenneth... move regfile/spec organiser to separate function
2020-06-04 Luke Kenneth... mention convenience variables
2020-06-04 Luke Kenneth... rename trap to use convenience variables
2020-06-04 colepoirierUndo damage done by deleting VHDL microwatt comments,
2020-06-04 Luke Kenneth... collate fu-enable signals
2020-06-04 Luke Kenneth... connect up Function Unit operand subsets
2020-06-03 Luke Kenneth... forgot to add in rdflag enable
2020-06-03 Luke Kenneth... whoops, regfiles are uppercase
2020-06-03 Luke Kenneth... whoops needed a bit of a reorg of the data structure...
2020-06-03 Luke Kenneth... hmmm got naming wrong in regfile-fu connectivity
2020-06-03 Luke Kenneth... whoops names of regfiles are lower-case
2020-06-03 Luke Kenneth... munge/redirect the regfile port based on the naming
2020-06-03 Luke Kenneth... connect read-enable and src_i to regfile ports
2020-06-03 Luke Kenneth... link up PriorityPickers on read channels
2020-06-03 Luke Kenneth... put rdspecs into a different dictionary
2020-06-03 Luke Kenneth... start putting a non-production core together,
2020-06-03 Luke Kenneth... add a simple core, not intended for production use
2020-06-03 Luke Kenneth... correct comments on regspec decode map
2020-06-03 Luke Kenneth... only select xer_xo if OE enabled
2020-06-03 Luke Kenneth... decide to elaborate Refiles *into* another class, rathe...
2020-06-03 Luke Kenneth... turn RegFiles into module, add all regfiles to it
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