soclayout.git
2021-04-13 Luke Kenneth... use METAL10 for topRoutingLayer
2021-04-13 Luke Kenneth... whoops forgot settings.py
2021-04-12 Luke Kenneth... submodule update
2021-04-12 Luke Kenneth... set routingGauge manually
2021-04-12 Luke Kenneth... enable HFNS in adder
2021-04-12 Luke Kenneth... include (but do not use) FreePDK45 in experiments10
2021-04-12 Luke Kenneth... different FreePDK45 experiments10 chip size
2021-04-12 Luke Kenneth... experimentation to get experiment10_verilog work with...
2021-04-12 Luke Kenneth... add FreePDK45 experiments10_verilog doDesign.py
2021-04-12 Luke Kenneth... add FreePDK45 variant of experiments10_verilog
2021-04-12 Luke Kenneth... update PLL signal output names
2021-04-12 Staf VerhaegendoDesign.py: Disable SRAM placement
2021-04-12 Staf VerhaegenReduce core size.
2021-04-12 Luke Kenneth... rename sys_clk in adder test experiments10_verilog...
2021-04-12 Luke Kenneth... rename JTAG port in adder test experiments10_verilog...
2021-04-12 Luke Kenneth... back to "working" verilog add
2021-04-12 Luke Kenneth... another attempt to get 100% completed route
2021-04-12 Staf VerhaegenRight branch of c4m-pdk-freedpk45.
2021-04-11 Luke Kenneth... good grief, increasing ls180 core size to 70,000, 100...
2021-04-11 Luke Kenneth... increase core size to see if global routing can be...
2021-04-11 Luke Kenneth... whitespace cleanup
2021-04-11 Luke Kenneth... use auto-generated pinmux ioPadsSpecs
2021-04-11 Luke Kenneth... submodule conflict (update again)
2021-04-11 Luke Kenneth... use verilog version of ls180 in FreePDK_c4m45
2021-04-11 Staf VerhaegenUpdate c4m-pdk-freepdk45 submodule.
2021-04-11 Luke Kenneth... crank up the numbers (again)
2021-04-11 Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45.
2021-04-11 Staf Verhaegenexperiments9: Ignore pinmux generated files.
2021-04-11 Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit
2021-04-11 Staf VerhaegenSubmodule for C4M FreePDK45 PDK release files.
2021-04-11 Luke Kenneth... crank up the numbers to see if routing completion can...
2021-04-11 Luke Kenneth... increase katana tracks reserved
2021-04-10 Luke Kenneth... use verilog for ls180 instead of ilang
2021-04-10 Luke Kenneth... make VST names unique, for GHDL to cope
2021-04-09 Luke Kenneth... sigh, broken experiment10_verilog
2021-04-09 Luke Kenneth... whitespace
2021-04-09 Luke Kenneth... whitespace cleanup
2021-04-09 Luke Kenneth... pad name starts with p_
2021-04-09 Luke Kenneth... rename design of experiments10 to match ls180 chip...
2021-04-02 Luke Kenneth... experiment with nmigen verilog generation
2021-04-01 Luke Kenneth... update / refresh full core DFF
2021-04-01 Luke Kenneth... update / refresh full core DFF
2021-04-01 Luke Kenneth... run doChipFloorplan in experiments10
2021-04-01 Luke Kenneth... increase experiment10 JTAG tap width to 4
2021-04-01 Luke Kenneth... update submodule
2021-03-30 Luke Kenneth... update 4k SRAM ls180.il
2021-03-30 Luke Kenneth... add yosys version number
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-29 Jean-Paul ChaputAdd a placeholder for the PLL in the doDesign.py for...
2021-03-29 Luke Kenneth... Revert "enable high fanout in ls180 experiment9 doDesig...
2021-03-29 Luke Kenneth... enable high fanout in ls180 experiment9 doDesign.py
2021-03-29 Luke Kenneth... aaagh found bug in litex setup, 64 bit WB bus was truncated
2021-03-28 Luke Kenneth... reduce SPR regfile size considerably
2021-03-28 Luke Kenneth... reduce INT and FAST regfile sizes by sharing ports
2021-03-27 Luke Kenneth... add missing floorplan function call
2021-03-27 Luke Kenneth... hooray, corrected pinouts
2021-03-27 Luke Kenneth... really weird error "unsupported direction for eint...
2021-03-23 Jean-Paul ChaputUodated doDesign for the latest ls180 (sram variant).
2021-03-22 Luke Kenneth... increase DFF RAM size slightly
2021-03-22 Luke Kenneth... add very small DFF srams variant
2021-03-22 Luke Kenneth... create small dff with 4x 4k SRAMs
2021-03-22 Luke Kenneth... ls180.il update
2021-03-22 Luke Kenneth... argh pinmux generating bi-directional SDR DM when it...
2021-03-18 Luke Kenneth... update ls180.il
2021-03-16 Luke Kenneth... update submodule
2021-03-16 Luke Kenneth... update ls180.il 4ksram with correct sdram connections
2021-03-16 Jean-Paul ChaputAdd experiment9/symbolic to test the multiple drivers...
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-14 Jean-Paul ChaputAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
2021-03-11 Luke Kenneth... try alternative pad/core connection
2021-03-09 Jean-Paul ChaputForgot the Makefile, stupid!
2021-03-09 Jean-Paul ChaputFirst working version of the Flexlib + P&R flow for...
2021-03-06 Luke Kenneth... add blackbox SPBlock 4k SRAM module
2021-03-05 Luke Kenneth... remove sram 4k wb bte/cti
2021-03-05 Luke Kenneth... litex expects wishbone "err" signals, added to sram 4k
2021-03-05 Luke Kenneth... rename sram_4k wishbone interface to actually like...
2021-03-05 Jean-Paul ChaputAdded support files for ls180+SRAM on TSMC 180nm.
2021-03-03 Luke Kenneth... add blackbox attribute manually to SPBlock_512W64B8W
2021-03-02 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-02 Jean-Paul ChaputFirst working power plane in experiment12.
2021-02-20 Luke Kenneth... add 4k sram build
2021-02-20 Luke Kenneth... increase core size to 50000 (DFF SRAMs)
2021-02-20 Luke Kenneth... expand core size to 28000
2021-02-17 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-02-17 Jean-Paul ChaputFirst working integration of a SRAM block.
2021-02-02 Luke Kenneth... whitespace
2021-02-02 Luke Kenneth... whitespace
2021-02-01 Jean-Paul ChaputNetlist integration of the SRAM OK. Layout in progress.
2021-01-28 Jean-Paul ChaputWorking bench design with SRAM in top block.
2021-01-27 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-01-27 Jean-Paul ChaputPinmux loading is now integrated in Coriolis.
2021-01-15 Luke Kenneth... add new Memory experiments13 ls180-24jan2020
2020-12-22 Luke Kenneth... add SPBlock_512W64B8W to memory.py
2020-12-22 Luke Kenneth... rename to memory from add
2020-12-22 Luke Kenneth... add copy of experiments4 to create memory example
2020-12-04 Luke Kenneth... increase core size (again) to cope with DFFs currently...
2020-12-04 Luke Kenneth... Revert "very weird bug where CoreToChip.buildChip canno...
2020-12-03 Luke Kenneth... very weird bug where CoreToChip.buildChip cannot find...
2020-12-03 Luke Kenneth... increase size to 45,000 to cope with 3x extra SRAMs
2020-12-03 Luke Kenneth... experiment adding 3x extra SRAMs back in but still...
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