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soclayout.git
2021-04-14
Luke Kenneth...
connect up boundary scan to inputs/outputs
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2021-04-13
Luke Kenneth...
submodule update
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2021-04-13
Luke Kenneth...
use METAL10 for topRoutingLayer
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2021-04-13
Luke Kenneth...
whoops forgot settings.py
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2021-04-12
Luke Kenneth...
submodule update
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2021-04-12
Luke Kenneth...
set routingGauge manually
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2021-04-12
Luke Kenneth...
enable HFNS in adder
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2021-04-12
Luke Kenneth...
include (but do not use) FreePDK45 in experiments10
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2021-04-12
Luke Kenneth...
different FreePDK45 experiments10 chip size
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2021-04-12
Luke Kenneth...
experimentation to get experiment10_verilog work with...
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2021-04-12
Luke Kenneth...
add FreePDK45 experiments10_verilog doDesign.py
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2021-04-12
Luke Kenneth...
add FreePDK45 variant of experiments10_verilog
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2021-04-12
Luke Kenneth...
update PLL signal output names
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2021-04-12
Staf Verhaegen
doDesign.py: Disable SRAM placement
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2021-04-12
Staf Verhaegen
Reduce core size.
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2021-04-12
Luke Kenneth...
rename sys_clk in adder test experiments10_verilog...
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2021-04-12
Luke Kenneth...
rename JTAG port in adder test experiments10_verilog...
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2021-04-12
Luke Kenneth...
back to "working" verilog add
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2021-04-12
Luke Kenneth...
another attempt to get 100% completed route
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2021-04-12
Staf Verhaegen
Right branch of c4m-pdk-freedpk45.
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2021-04-11
Luke Kenneth...
good grief, increasing ls180 core size to 70,000, 100...
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2021-04-11
Luke Kenneth...
increase core size to see if global routing can be...
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2021-04-11
Luke Kenneth...
whitespace cleanup
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2021-04-11
Luke Kenneth...
use auto-generated pinmux ioPadsSpecs
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2021-04-11
Luke Kenneth...
submodule conflict (update again)
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2021-04-11
Luke Kenneth...
use verilog version of ls180 in FreePDK_c4m45
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2021-04-11
Staf Verhaegen
Update c4m-pdk-freepdk45 submodule.
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2021-04-11
Luke Kenneth...
crank up the numbers (again)
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2021-04-11
Staf Verhaegen
Wip of P&R of ls180 with C4M FreePDK45.
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2021-04-11
Staf Verhaegen
experiments9: Ignore pinmux generated files.
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2021-04-11
Staf Verhaegen
mksym.sh: Check exitence of alliance-check-toolkit
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2021-04-11
Staf Verhaegen
Submodule for C4M FreePDK45 PDK release files.
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2021-04-11
Luke Kenneth...
crank up the numbers to see if routing completion can...
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2021-04-11
Luke Kenneth...
increase katana tracks reserved
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2021-04-10
Luke Kenneth...
use verilog for ls180 instead of ilang
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2021-04-10
Luke Kenneth...
make VST names unique, for GHDL to cope
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2021-04-09
Luke Kenneth...
sigh, broken experiment10_verilog
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2021-04-09
Luke Kenneth...
whitespace
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2021-04-09
Luke Kenneth...
whitespace cleanup
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2021-04-09
Luke Kenneth...
pad name starts with p_
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2021-04-09
Luke Kenneth...
rename design of experiments10 to match ls180 chip...
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2021-04-02
Luke Kenneth...
experiment with nmigen verilog generation
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2021-04-01
Luke Kenneth...
update / refresh full core DFF
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2021-04-01
Luke Kenneth...
update / refresh full core DFF
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2021-04-01
Luke Kenneth...
run doChipFloorplan in experiments10
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2021-04-01
Luke Kenneth...
increase experiment10 JTAG tap width to 4
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2021-04-01
Luke Kenneth...
update submodule
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2021-03-30
Luke Kenneth...
update 4k SRAM ls180.il
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2021-03-30
Luke Kenneth...
add yosys version number
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2021-03-29
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-03-29
Jean-Paul Chaput
Add a placeholder for the PLL in the doDesign.py for...
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2021-03-29
Luke Kenneth...
Revert "enable high fanout in ls180 experiment9 doDesig...
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2021-03-29
Luke Kenneth...
enable high fanout in ls180 experiment9 doDesign.py
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2021-03-29
Luke Kenneth...
aaagh found bug in litex setup, 64 bit WB bus was truncated
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2021-03-28
Luke Kenneth...
reduce SPR regfile size considerably
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2021-03-28
Luke Kenneth...
reduce INT and FAST regfile sizes by sharing ports
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2021-03-27
Luke Kenneth...
add missing floorplan function call
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2021-03-27
Luke Kenneth...
hooray, corrected pinouts
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2021-03-27
Luke Kenneth...
really weird error "unsupported direction for eint...
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2021-03-23
Jean-Paul Chaput
Uodated doDesign for the latest ls180 (sram variant).
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2021-03-22
Luke Kenneth...
increase DFF RAM size slightly
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2021-03-22
Luke Kenneth...
add very small DFF srams variant
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2021-03-22
Luke Kenneth...
create small dff with 4x 4k SRAMs
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2021-03-22
Luke Kenneth...
ls180.il update
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2021-03-22
Luke Kenneth...
argh pinmux generating bi-directional SDR DM when it...
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2021-03-18
Luke Kenneth...
update ls180.il
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2021-03-16
Luke Kenneth...
update submodule
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2021-03-16
Luke Kenneth...
update ls180.il 4ksram with correct sdram connections
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2021-03-16
Jean-Paul Chaput
Add experiment9/symbolic to test the multiple drivers...
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2021-03-14
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-03-14
Jean-Paul Chaput
Adjusted doDesign.py scripts to use Chip.doChipFloorplan().
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2021-03-11
Luke Kenneth...
try alternative pad/core connection
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2021-03-09
Jean-Paul Chaput
Forgot the Makefile, stupid!
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2021-03-09
Jean-Paul Chaput
First working version of the Flexlib + P&R flow for...
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2021-03-06
Luke Kenneth...
add blackbox SPBlock 4k SRAM module
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2021-03-05
Luke Kenneth...
remove sram 4k wb bte/cti
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2021-03-05
Luke Kenneth...
litex expects wishbone "err" signals, added to sram 4k
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2021-03-05
Luke Kenneth...
rename sram_4k wishbone interface to actually like...
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2021-03-05
Jean-Paul Chaput
Added support files for ls180+SRAM on TSMC 180nm.
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2021-03-03
Luke Kenneth...
add blackbox attribute manually to SPBlock_512W64B8W
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2021-03-02
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-03-02
Jean-Paul Chaput
First working power plane in experiment12.
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2021-02-20
Luke Kenneth...
add 4k sram build
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2021-02-20
Luke Kenneth...
increase core size to 50000 (DFF SRAMs)
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2021-02-20
Luke Kenneth...
expand core size to 28000
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2021-02-17
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-02-17
Jean-Paul Chaput
First working integration of a SRAM block.
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2021-02-02
Luke Kenneth...
whitespace
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2021-02-02
Luke Kenneth...
whitespace
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2021-02-01
Jean-Paul Chaput
Netlist integration of the SRAM OK. Layout in progress.
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2021-01-28
Jean-Paul Chaput
Working bench design with SRAM in top block.
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2021-01-27
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-01-27
Jean-Paul Chaput
Pinmux loading is now integrated in Coriolis.
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2021-01-15
Luke Kenneth...
add new Memory experiments13
ls180-24jan2020
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2020-12-22
Luke Kenneth...
add SPBlock_512W64B8W to memory.py
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2020-12-22
Luke Kenneth...
rename to memory from add
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2020-12-22
Luke Kenneth...
add copy of experiments4 to create memory example
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2020-12-04
Luke Kenneth...
increase core size (again) to cope with DFFs currently...
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2020-12-04
Luke Kenneth...
Revert "very weird bug where CoreToChip.buildChip canno...
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2020-12-03
Luke Kenneth...
very weird bug where CoreToChip.buildChip cannot find...
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