git.libre-soc.org Git - soc.git/history - src/soc/simple/issuer

2020-08-24	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw
2020-08-21	Luke Kenneth Casso...	testing 64-bit wishbone bus after 32-bit still fails...	blob \| commitdiff \| raw
2020-08-21	Luke Kenneth Casso...	get litex sim enabled with 32-bit wishbone bus	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	put multi-ports back (for read) on int and fast regfiles	blob \| commitdiff \| raw \| diff to current
2020-08-05	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-05	Luke Kenneth Casso...	add div FSM as default for test_issuer in verilog and...	blob \| commitdiff \| raw \| diff to current
2020-07-30	Luke Kenneth Casso...	ha! have to explicitly specify the ports when writing...	blob \| commitdiff \| raw \| diff to current
2020-07-23	Luke Kenneth Casso...	support 32-bit mem width setting	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	add issuer verilog generator	blob \| commitdiff \| raw \| diff to current