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incompatibility with POWER9 on mulhw/u due to lack of spec clarity
[soc.git] / src /
2020-08-27 Luke Kenneth Casso... incompatibility with POWER9 on mulhw/u due to lack... tree | commitdiff
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations tree | commitdiff
2020-08-27 Luke Kenneth Casso... oink, write_cr shiftrot record width was zero (??) tree | commitdiff
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data... tree | commitdiff
2020-08-27 Luke Kenneth Casso... need to read SO if Rc=1 tree | commitdiff
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0 tree | commitdiff
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with... tree | commitdiff
2020-08-26 Luke Kenneth Casso... use sub-test in logical test_pipe_caller tree | commitdiff
2020-08-26 Luke Kenneth Casso... investigating div fsm and simulator bug tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions... tree | commitdiff
2020-08-25 Jacob Lifshayfix broken remainder for div FSM tree | commitdiff
2020-08-25 Jacob Lifshayclean up formatting tree | commitdiff
2020-08-25 Luke Kenneth Casso... although shift-rot does not alter XER.so it still needs... tree | commitdiff
2020-08-25 Luke Kenneth Casso... add way to capture CR from DMI in litex sim tree | commitdiff
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface tree | commitdiff
2020-08-25 Luke Kenneth Casso... shorten using temp vars tree | commitdiff
2020-08-25 Luke Kenneth Casso... add CR DMI interface tree | commitdiff
2020-08-25 Luke Kenneth Casso... add crxor unit test to qemu tree | commitdiff
2020-08-25 Cole Poirierdcache.py fix whitespace, fomatting, syntax tree | commitdiff
2020-08-25 Cole Poirierdcache.py fix formatting tree | commitdiff
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file tree | commitdiff
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file tree | commitdiff
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top... tree | commitdiff
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file tree | commitdiff
2020-08-24 Luke Kenneth Casso... argh, reading regfile over DMI was overlapped and corru... tree | commitdiff
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working) tree | commitdiff
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup tree | commitdiff
2020-08-24 Luke Kenneth Casso... make it easier to select FSM/Pipe DIV unit tree | commitdiff
2020-08-24 Luke Kenneth Casso... fix *another* ld-update-related timing / FSM issue tree | commitdiff
2020-08-24 Luke Kenneth Casso... tidyup / shuffle after review tree | commitdiff
2020-08-24 Luke Kenneth Casso... remove default parameter tree | commitdiff
2020-08-24 Luke Kenneth Casso... "WAY" does not exist - range(NUM_WAYS) was intended tree | commitdiff
2020-08-24 Luke Kenneth Casso... use WAY_BITS in appropriate locations tree | commitdiff
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about... tree | commitdiff
2020-08-23 Luke Kenneth Casso... update copyright notices to include additional primary... tree | commitdiff
2020-08-23 Luke Kenneth Casso... add load algebraic immediate unit test tree | commitdiff
2020-08-23 Luke Kenneth Casso... add algebraic ld tests lwax, lwaux tree | commitdiff
2020-08-23 Michael NolanAdd copyright to files I primarily authored in simulator/ tree | commitdiff
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary... tree | commitdiff
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py tree | commitdiff
2020-08-23 Luke Kenneth Casso... bring "core stopped" signal out through DMI interface tree | commitdiff
2020-08-23 Luke Kenneth Casso... add in DMI "stat" loop which monitors core "stopping" tree | commitdiff
2020-08-23 Cesar StraussAllow an empty style, and passing default styles as... tree | commitdiff
2020-08-23 Cesar StraussAdd comment node type tree | commitdiff
2020-08-23 Cesar StraussAdd base and display styles tree | commitdiff
2020-08-23 Cesar StraussApply style from node own name tree | commitdiff
2020-08-23 Cesar StraussAdd color style tree | commitdiff
2020-08-23 Cesar StraussCollect styles from the tuple tree | commitdiff
2020-08-23 Cesar StraussPropagate the root style to all signals tree | commitdiff
2020-08-23 Luke Kenneth Casso... comment why litex sim mem map is altered tree | commitdiff
2020-08-23 Luke Kenneth Casso... multiply does not have invert_in, zero_a or invert_out tree | commitdiff
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB tree | commitdiff
2020-08-22 Luke Kenneth Casso... load bios not 1.bin unit test tree | commitdiff
2020-08-22 Luke Kenneth Casso... add extra div regression tests tree | commitdiff
2020-08-22 Cesar StraussMove comments to the docstring tree | commitdiff
2020-08-22 Cesar StraussWalk the DOM and emit the trace names tree | commitdiff
2020-08-22 Luke Kenneth Casso... add eqv to logical unit test tree | commitdiff
2020-08-22 Luke Kenneth Casso... add nor and nand to unit test tree | commitdiff
2020-08-22 Luke Kenneth Casso... moved to div pipe temporarily in compunits tree | commitdiff
2020-08-22 Luke Kenneth Casso... bug in andc and orc, complement was taking place on... tree | commitdiff
2020-08-22 Luke Kenneth Casso... extend addis test tree | commitdiff
2020-08-22 Luke Kenneth Casso... add andc and orc tests, failing because RB needs invers... tree | commitdiff
2020-08-22 Luke Kenneth Casso... modsd bug, https://bugs.libre-soc.org/show_bug.cgi... tree | commitdiff
2020-08-22 Cesar StraussFirst draft of a mini-language to describe GTKWave... tree | commitdiff
2020-08-22 Luke Kenneth Casso... add regression test for nonzero addis tree | commitdiff
2020-08-22 Luke Kenneth Casso... add means to run microwatt test binaries tree | commitdiff
2020-08-22 Luke Kenneth Casso... r0 zero tests on addis, fails tree | commitdiff
2020-08-22 Luke Kenneth Casso... investigating litex sdrinit function tree | commitdiff
2020-08-22 Luke Kenneth Casso... add pseudo-op conversion tree | commitdiff
2020-08-22 Luke Kenneth Casso... add start of litex bios counter loop tree | commitdiff
2020-08-21 Luke Kenneth Casso... remove extraneous comments tree | commitdiff
2020-08-21 Luke Kenneth Casso... testing 64-bit wishbone bus after 32-bit *still* fails... tree | commitdiff
2020-08-21 Tobias Platentypo fix in test_l0_cache_buffer2.py tree | commitdiff
2020-08-21 Cole Poirierdcache.py fix asserts, use backslash and two strings... tree | commitdiff
2020-08-21 Cole Poirierdcache.py replace functions that return signals with... tree | commitdiff
2020-08-21 Cole Poirierwb_types fix typo tree | commitdiff
2020-08-21 Tobias Platenconnect TestCachedMemoryPortInterface to LDSTSplitter tree | commitdiff
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus tree | commitdiff
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface tree | commitdiff
2020-08-21 Luke Kenneth Casso... comment formatting tree | commitdiff
2020-08-21 Luke Kenneth Casso... remove default values tree | commitdiff
2020-08-21 Luke Kenneth Casso... just range(the_constant) tree | commitdiff
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered. tree | commitdiff
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP tree | commitdiff
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry... tree | commitdiff
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP. tree | commitdiff
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u) tree | commitdiff
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw tree | commitdiff
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface tree | commitdiff
2020-08-20 Tobias Platentestcase refactoring tree | commitdiff
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface tree | commitdiff
2020-08-20 Luke Kenneth Casso... bugfix wishbone downconvert using wb sram 64-to-32... tree | commitdiff
2020-08-20 Luke Kenneth Casso... add a wishbone upconverter tree | commitdiff
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