pass addr/mask through to PortInterfaceBase rd/wr addr
[soc.git] / src /
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth Casso... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... name issue in Pi2LSUI
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth Casso... correct address in pi2ls
2020-06-26 Luke Kenneth Casso... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth Casso... add in LenExpand shift/mask
2020-06-26 Luke Kenneth Casso... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth Casso... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth Casso... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth Casso... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth Casso... unit test broken is ok :)
2020-06-26 Luke Kenneth Casso... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth Casso... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth Casso... add reconfigureable Load/Store class
2020-06-26 Luke Kenneth Casso... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth Casso... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth Casso... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth Casso... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth Casso... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... move comments to minerva LoadStoreInterface
2020-06-24 Luke Kenneth Casso... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-23 Luke Kenneth Casso... TstL0CacheBuffer returns array of ports differently now
2020-06-22 Luke Kenneth Casso... remove unused module
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth Casso... comments for LDST CompUnit test
2020-06-22 Luke Kenneth Casso... enable byte-reverse in CompLDSTUnit test
2020-06-22 Luke Kenneth Casso... remove CompLDSTOpSubset, replace with just data_len.
2020-06-22 Luke Kenneth Casso... move BE/LE byte-reverse into LDSTCompUnit
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in...
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct
2020-06-20 Luke Kenneth Casso... add test_sram_wishbone.py
2020-06-20 colepoirierAdd code, commented-out, for TRAP so as to not break...
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-19 Luke Kenneth Casso... move trunc_div and trunc_rem to nmutil
2020-06-19 Luke Kenneth Casso... add comments on trunc_div and trunc_rem
2020-06-19 Luke Kenneth Casso... add divide-by-zero test to test_div_sim.py
2020-06-19 Luke Kenneth Casso... add docstring comment for SelectableInt
2020-06-19 Luke Kenneth Casso... add test_0_moduw and correct name to trunc_rem
2020-06-19 Luke Kenneth Casso... add abs SelectableInt unit test (very quick)
2020-06-19 Luke Kenneth Casso... add SelectableInt.abs
2020-06-19 Luke Kenneth Casso... add another bad hack in parser.py which identifies...
2020-06-19 Luke Kenneth Casso... add in really bad hack which calls trunc_div or trunc_mod
2020-06-19 Luke Kenneth Casso... add trunc_div and trunch_rem to decoder helpers
2020-06-19 Luke Kenneth Casso... auto-assign needs to use concat / selectconcat
2020-06-19 Luke Kenneth Casso... whoops detected page name wrong, for special case fixed...
2020-06-19 Luke Kenneth Casso... bit of a mess. getting carry recognised and output...
2020-06-19 Luke Kenneth Casso... add auto-assign mode detecting uninitialised variable...
2020-06-19 Luke Kenneth Casso... div needs to be floordiv
2020-06-19 Luke Kenneth Casso... add true and floor div to SelectableInt
2020-06-19 Luke Kenneth Casso... add simulator test for divw
2020-06-19 Luke Kenneth Casso... do mix-in for test_sim.py so that jacob can write some...
2020-06-19 Luke Kenneth Casso... add TODO comments to upgrade L0CacheBuffer to a new...
next