2020-08-13 |
Luke Kenneth Casso... | code-shuffle |
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2020-08-13 |
Luke Kenneth Casso... | remove use of latchregigister, replace with sync on... |
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2020-08-13 |
Cole Poirier | dcache.py add initial imports |
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2020-08-13 |
Cole Poirier | mem_types.py add more types from common.vhdl |
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2020-08-13 |
Cole Poirier | move memory related types from mmu.py into new file... |
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2020-08-13 |
Luke Kenneth Casso... | sync on reset in compalu |
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2020-08-13 |
Luke Kenneth Casso... | sync on port interface address in ld/st compunit, and... |
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2020-08-13 |
Luke Kenneth Casso... | another sync to cut latency |
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2020-08-13 |
Cole Poirier | Initial commit of translation of microwatt dcache.vhdl... |
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2020-08-13 |
Luke Kenneth Casso... | remove latchregister, sync src oper_i into MultiCompUnit |
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2020-08-13 |
Luke Kenneth Casso... | minor tidyup on alu compunit: |
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2020-08-13 |
Luke Kenneth Casso... | plenty of time to wait for operand, so use "sync" in... |
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2020-08-12 |
Cole Poirier | mmu.py add skeleton sim and test functions from regfile... |
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2020-08-12 |
Cole Poirier | Delete unnecessary mmu dir, move mmu.py out of mmu... |
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2020-08-12 |
Cole Poirier | Revert "Remove mmu dir and associated mmu/test/ dir... |
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2020-08-12 |
Cole Poirier | Remove mmu dir and associated mmu/test/ dir |
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2020-08-12 |
Cole Poirier | Remove rst signals, fix len of hex Consts, fix variable... |
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2020-08-12 |
Cole Poirier | Create dir experiment/mmu then mmu/test with skeleton... |
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2020-08-12 |
Cole Poirier | mmu.py add RecordObject classes from common.vhdl input... |
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2020-08-12 |
Cole Poirier | mmu.py remove TODOs for vhdl (others => '0') as they... |
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2020-08-12 |
Cole Poirier | mmu.py fix or(block of logic) to be (block of logic... |
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2020-08-12 |
Cole Poirier | mmu.py fix length of hex const https://bugs.libre-soc... |
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2020-08-12 |
Cole Poirier | mmu.py remove class AddrShifter |
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2020-08-12 |
Cole Poirier | Fix typo in mmu.py |
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2020-08-11 |
Cole Poirier | mmu.py fix formatting, use Cat() where '&' in mmu.vhdl |
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2020-08-11 |
Tobias Platen | initial version of L0CacheBuffer2 |
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2020-08-10 |
Cole Poirier | Fix typo in mmu.py |
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2020-08-10 |
Cole Poirier | Fix typo mmu.py |
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2020-08-10 |
Cole Poirier | Global search and replace (^, |), fixes bug 450 comment... |
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2020-08-10 |
Cole Poirier | fix bug 450 comments 8,9,10 |
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2020-08-10 |
Cole Poirier | Fix bug 450 comment 7 |
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2020-08-10 |
Cole Poirier | mmu.py add line I forgot to translate from mmu.vhdl |
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2020-08-10 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-10 |
Cole Poirier | mmu.vhdl translation to mmu.py 95 percent complete |
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2020-08-09 |
Luke Kenneth Casso... | stop combinatorial loop in pi2ls |
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2020-08-09 |
Luke Kenneth Casso... | fix combinatorial loop in ldst compunit |
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2020-08-09 |
Luke Kenneth Casso... | compalu combinatorial loop detected |
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2020-08-06 |
Cole Poirier | Fix mmu.py formatting |
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2020-08-06 |
Cole Poirier | Initial commit of translation of microwatt mmu.vhdl... |
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2020-08-06 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-06 |
Luke Kenneth Casso... | fix LDST PortInterface FSM interaction |
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2020-08-04 |
Luke Kenneth Casso... | swap over byte-reverse if/else in LDSTCompUnit |
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2020-08-04 |
Luke Kenneth Casso... | tracked down byte-reversal in LDST ISACaller and LDSTCo... |
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2020-08-03 |
Luke Kenneth Casso... | https://bugs.libre-soc.org/show_bug.cgi?id=446 |
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2020-08-03 |
Tobias Platen | LDSTSplitter: report exception |
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2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-08-03 |
Tobias Platen | TstDataMerger2 |
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2020-07-30 |
Tobias Platen | begin work on TestCase for two DataMergers/Cache |
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2020-07-30 |
Tobias Platen | add CacheRecord |
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2020-07-30 |
Luke Kenneth Casso... | ha! have to explicitly specify the ports when writing... |
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2020-07-29 |
Luke Kenneth Casso... | forgot to rename ad/st in LDSTCompUnitRecord |
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2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
tree | commitdiff |
2020-07-29 |
Jacob Lifshay | clean up some tests |
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2020-07-29 |
Jacob Lifshay | format some tests |
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2020-07-26 |
Luke Kenneth Casso... | do not need lod_l.q | lsto_l.q can just use lsd_l.q |
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2020-07-26 |
Luke Kenneth Casso... | argh add yet another latch to detect when LD/ST has... |
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2020-07-25 |
Luke Kenneth Casso... | going on a bit of a "naming" spree, this for Jean-Paul... |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-21 |
Luke Kenneth Casso... | testing if MultiCompUnit can handle no input regs ... |
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2020-07-21 |
Luke Kenneth Casso... | disable cxxsim for now |
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2020-07-20 |
Cesar Strauss | Document the move of sdir from data_i to op. |
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2020-07-20 |
Cesar Strauss | Remove extra yield from test case. |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | convert compalu multi test to Simulator() (was run_simu... |
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2020-07-19 |
Luke Kenneth Casso... | convert compalu multi test to Simulator() (was run_simu... |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | fix bug in alu_fsm.py found by cxxsim: missing one... |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | add some CompUnit demo tests of the alu_fsm example |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | move sdir to CompFSMOpSubset in alu_fsm example |
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2020-07-19 |
Luke Kenneth Casso... | add CompFSMOpSubset, also change dir to sdir |
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2020-07-19 |
Luke Kenneth Casso... | use iocontrol PrevControl / NextControl instead of... |
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2020-07-19 |
Cesar Strauss | Implement control path and unit test. |
tree | commitdiff |
2020-07-18 |
Cesar Strauss | Implement the Shifter data path |
tree | commitdiff |
2020-07-18 |
Cesar Strauss | Document move of the next port data |
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2020-07-18 |
Luke Kenneth Casso... | add SR latch cxxrtl backend demo |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | change CSV LD/ST update field to LDSTMode (support... |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | update-mode request write signalled too early |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | sort out core write latching: gate by busy, and use... |
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2020-07-11 |
Luke Kenneth Casso... | * clarifying core function unit enable |
tree | commitdiff |
2020-07-09 |
Luke Kenneth Casso... | munge alu_fsm Shifter into looking like CompALU API... |
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2020-07-09 |
Cesar Strauss | Define ports for a simple sequential Shifter |
tree | commitdiff |
2020-07-08 |
Cesar Strauss | Start the FSM-based ALU example. |
tree | commitdiff |
2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-07-07 |
Cesar Strauss | Clear input data along with valid_i |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Assert n.ready_i at the beginning of the cycle |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Remove wait state to demonstrate zero-delay reception. |
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2020-07-06 |
Cesar Strauss | Simplify waiting loops |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Finally add some well needed comments |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Simplify waiting loops |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Add some wait states in each process |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Negate inputs after use |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Add other tests |
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2020-07-06 |
Cesar Strauss | Implement receiver |
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2020-07-06 |
Cesar Strauss | Implement sender. |
tree | commitdiff |
2020-07-06 |
Cesar Strauss | Begin a new parallel test |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | add gitignores |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | fix unit tests due to change in using pspec |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | allow ALU names to propagate through from FU to CompUni... |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add bare wishbone option to TestIssuer, sort out ports |
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