finally, fix decoder combinatorial loop
[soc.git] / src / soc / experiment /
2020-08-13 Luke Kenneth Casso... code-shuffle
2020-08-13 Luke Kenneth Casso... remove use of latchregigister, replace with sync on...
2020-08-13 Cole Poirierdcache.py add initial imports
2020-08-13 Cole Poiriermem_types.py add more types from common.vhdl
2020-08-13 Cole Poiriermove memory related types from mmu.py into new file...
2020-08-13 Luke Kenneth Casso... sync on reset in compalu
2020-08-13 Luke Kenneth Casso... sync on port interface address in ld/st compunit, and...
2020-08-13 Luke Kenneth Casso... another sync to cut latency
2020-08-13 Cole PoirierInitial commit of translation of microwatt dcache.vhdl...
2020-08-13 Luke Kenneth Casso... remove latchregister, sync src oper_i into MultiCompUnit
2020-08-13 Luke Kenneth Casso... minor tidyup on alu compunit:
2020-08-13 Luke Kenneth Casso... plenty of time to wait for operand, so use "sync" in...
2020-08-12 Cole Poiriermmu.py add skeleton sim and test functions from regfile...
2020-08-12 Cole PoirierDelete unnecessary mmu dir, move mmu.py out of mmu...
2020-08-12 Cole PoirierRevert "Remove mmu dir and associated mmu/test/ dir...
2020-08-12 Cole PoirierRemove mmu dir and associated mmu/test/ dir
2020-08-12 Cole PoirierRemove rst signals, fix len of hex Consts, fix variable...
2020-08-12 Cole PoirierCreate dir experiment/mmu then mmu/test with skeleton...
2020-08-12 Cole Poiriermmu.py add RecordObject classes from common.vhdl input...
2020-08-12 Cole Poiriermmu.py remove TODOs for vhdl (others => '0') as they...
2020-08-12 Cole Poiriermmu.py fix or(block of logic) to be (block of logic...
2020-08-12 Cole Poiriermmu.py fix length of hex const https://bugs.libre-soc...
2020-08-12 Cole Poiriermmu.py remove class AddrShifter
2020-08-12 Cole PoirierFix typo in mmu.py
2020-08-11 Cole Poiriermmu.py fix formatting, use Cat() where '&' in mmu.vhdl
2020-08-11 Tobias Plateninitial version of L0CacheBuffer2
2020-08-10 Cole PoirierFix typo in mmu.py
2020-08-10 Cole PoirierFix typo mmu.py
2020-08-10 Cole PoirierGlobal search and replace (^, |), fixes bug 450 comment...
2020-08-10 Cole Poirierfix bug 450 comments 8,9,10
2020-08-10 Cole PoirierFix bug 450 comment 7
2020-08-10 Cole Poiriermmu.py add line I forgot to translate from mmu.vhdl
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-10 Cole Poiriermmu.vhdl translation to mmu.py 95 percent complete
2020-08-09 Luke Kenneth Casso... stop combinatorial loop in pi2ls
2020-08-09 Luke Kenneth Casso... fix combinatorial loop in ldst compunit
2020-08-09 Luke Kenneth Casso... compalu combinatorial loop detected
2020-08-06 Cole PoirierFix mmu.py formatting
2020-08-06 Cole PoirierInitial commit of translation of microwatt mmu.vhdl...
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Luke Kenneth Casso... fix LDST PortInterface FSM interaction
2020-08-04 Luke Kenneth Casso... swap over byte-reverse if/else in LDSTCompUnit
2020-08-04 Luke Kenneth Casso... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-03 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=446
2020-08-03 Tobias PlatenLDSTSplitter: report exception
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Tobias PlatenTstDataMerger2
2020-07-30 Tobias Platenbegin work on TestCase for two DataMergers/Cache
2020-07-30 Tobias Platenadd CacheRecord
2020-07-30 Luke Kenneth Casso... ha! have to explicitly specify the ports when writing...
2020-07-29 Luke Kenneth Casso... forgot to rename ad/st in LDSTCompUnitRecord
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayclean up some tests
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... do not need lod_l.q | lsto_l.q can just use lsd_l.q
2020-07-26 Luke Kenneth Casso... argh add yet another latch to detect when LD/ST has...
2020-07-25 Luke Kenneth Casso... going on a bit of a "naming" spree, this for Jean-Paul...
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... testing if MultiCompUnit can handle no input regs ...
2020-07-21 Luke Kenneth Casso... disable cxxsim for now
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op.
2020-07-20 Cesar StraussRemove extra yield from test case.
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-19 Luke Kenneth Casso... add some CompUnit demo tests of the alu_fsm example
2020-07-19 Luke Kenneth Casso... move sdir to CompFSMOpSubset in alu_fsm example
2020-07-19 Luke Kenneth Casso... add CompFSMOpSubset, also change dir to sdir
2020-07-19 Luke Kenneth Casso... use iocontrol PrevControl / NextControl instead of...
2020-07-19 Cesar StraussImplement control path and unit test.
2020-07-18 Cesar StraussImplement the Shifter data path
2020-07-18 Cesar StraussDocument move of the next port data
2020-07-18 Luke Kenneth Casso... add SR latch cxxrtl backend demo
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... change CSV LD/ST update field to LDSTMode (support...
2020-07-12 Luke Kenneth Casso... update-mode request write signalled too early
2020-07-11 Luke Kenneth Casso... sort out core write latching: gate by busy, and use...
2020-07-11 Luke Kenneth Casso... * clarifying core function unit enable
2020-07-09 Luke Kenneth Casso... munge alu_fsm Shifter into looking like CompALU API...
2020-07-09 Cesar StraussDefine ports for a simple sequential Shifter
2020-07-08 Cesar StraussStart the FSM-based ALU example.
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Cesar StraussClear input data along with valid_i
2020-07-06 Cesar StraussAssert n.ready_i at the beginning of the cycle
2020-07-06 Cesar StraussRemove wait state to demonstrate zero-delay reception.
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussFinally add some well needed comments
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussAdd some wait states in each process
2020-07-06 Cesar StraussNegate inputs after use
2020-07-06 Cesar StraussAdd other tests
2020-07-06 Cesar StraussImplement receiver
2020-07-06 Cesar StraussImplement sender.
2020-07-06 Cesar StraussBegin a new parallel test
2020-07-04 Luke Kenneth Casso... add gitignores
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
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