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tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
[soc.git]
/
src
/
soc
/
experiment
/
2020-08-04
Luke Kenneth Casso...
tracked down byte-reversal in LDST ISACaller and LDSTCo...
tree
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commitdiff
2020-08-03
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=446
tree
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commitdiff
2020-08-03
Tobias Platen
LDSTSplitter: report exception
tree
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commitdiff
2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-08-03
Tobias Platen
TstDataMerger2
tree
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commitdiff
2020-07-30
Tobias Platen
begin work on TestCase for two DataMergers/Cache
tree
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commitdiff
2020-07-30
Tobias Platen
add CacheRecord
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commitdiff
2020-07-30
Luke Kenneth Casso...
ha! have to explicitly specify the ports when writing...
tree
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commitdiff
2020-07-29
Luke Kenneth Casso...
forgot to rename ad/st in LDSTCompUnitRecord
tree
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commitdiff
2020-07-29
Luke Kenneth Casso...
bit of a big change: add prefixes "cu_" to all CompUnit...
tree
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commitdiff
2020-07-29
Jacob Lifshay
add __init__.py to all source directories
tree
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commitdiff
2020-07-29
Jacob Lifshay
clean up some tests
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commitdiff
2020-07-29
Jacob Lifshay
format some tests
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commitdiff
2020-07-26
Luke Kenneth Casso...
do not need lod_l.q | lsto_l.q can just use lsd_l.q
tree
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commitdiff
2020-07-26
Luke Kenneth Casso...
argh add yet another latch to detect when LD/ST has...
tree
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commitdiff
2020-07-25
Luke Kenneth Casso...
going on a bit of a "naming" spree, this for Jean-Paul...
tree
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commitdiff
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
tree
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commitdiff
2020-07-22
Jacob Lifshay
format code
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commitdiff
2020-07-21
Luke Kenneth Casso...
testing if MultiCompUnit can handle no input regs ...
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commitdiff
2020-07-21
Luke Kenneth Casso...
disable cxxsim for now
tree
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commitdiff
2020-07-20
Cesar Strauss
Document the move of sdir from data_i to op.
tree
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commitdiff
2020-07-20
Cesar Strauss
Remove extra yield from test case.
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
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commitdiff
2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
fix bug in alu_fsm.py found by cxxsim: missing one...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
add some CompUnit demo tests of the alu_fsm example
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
move sdir to CompFSMOpSubset in alu_fsm example
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commitdiff
2020-07-19
Luke Kenneth Casso...
add CompFSMOpSubset, also change dir to sdir
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commitdiff
2020-07-19
Luke Kenneth Casso...
use iocontrol PrevControl / NextControl instead of...
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commitdiff
2020-07-19
Cesar Strauss
Implement control path and unit test.
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commitdiff
2020-07-18
Cesar Strauss
Implement the Shifter data path
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commitdiff
2020-07-18
Cesar Strauss
Document move of the next port data
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commitdiff
2020-07-18
Luke Kenneth Casso...
add SR latch cxxrtl backend demo
tree
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commitdiff
2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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commitdiff
2020-07-12
Luke Kenneth Casso...
change CSV LD/ST update field to LDSTMode (support...
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commitdiff
2020-07-12
Luke Kenneth Casso...
update-mode request write signalled too early
tree
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commitdiff
2020-07-11
Luke Kenneth Casso...
sort out core write latching: gate by busy, and use...
tree
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commitdiff
2020-07-11
Luke Kenneth Casso...
* clarifying core function unit enable
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commitdiff
2020-07-09
Luke Kenneth Casso...
munge alu_fsm Shifter into looking like CompALU API...
tree
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commitdiff
2020-07-09
Cesar Strauss
Define ports for a simple sequential Shifter
tree
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commitdiff
2020-07-08
Cesar Strauss
Start the FSM-based ALU example.
tree
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commitdiff
2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-07-07
Cesar Strauss
Clear input data along with valid_i
tree
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commitdiff
2020-07-06
Cesar Strauss
Assert n.ready_i at the beginning of the cycle
tree
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commitdiff
2020-07-06
Cesar Strauss
Remove wait state to demonstrate zero-delay reception.
tree
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commitdiff
2020-07-06
Cesar Strauss
Simplify waiting loops
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commitdiff
2020-07-06
Cesar Strauss
Finally add some well needed comments
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commitdiff
2020-07-06
Cesar Strauss
Simplify waiting loops
tree
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commitdiff
2020-07-06
Cesar Strauss
Add some wait states in each process
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commitdiff
2020-07-06
Cesar Strauss
Negate inputs after use
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commitdiff
2020-07-06
Cesar Strauss
Add other tests
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commitdiff
2020-07-06
Cesar Strauss
Implement receiver
tree
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commitdiff
2020-07-06
Cesar Strauss
Implement sender.
tree
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commitdiff
2020-07-06
Cesar Strauss
Begin a new parallel test
tree
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commitdiff
2020-07-04
Luke Kenneth Casso...
add gitignores
tree
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commitdiff
2020-07-02
Luke Kenneth Casso...
fix unit tests due to change in using pspec
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commitdiff
2020-07-02
Luke Kenneth Casso...
allow ALU names to propagate through from FU to CompUni...
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commitdiff
2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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commitdiff
2020-07-02
Luke Kenneth Casso...
use single-arg pspec for TestIssuer and Core
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commitdiff
2020-07-02
Cesar Strauss
Present the ALU result only when valid_o is active
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commitdiff
2020-07-01
Luke Kenneth Casso...
minor reorg on how Bus and Config classes are set up
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commitdiff
2020-06-29
Luke Kenneth Casso...
fetch instructions from bare wishbone fetch unit
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commitdiff
2020-06-28
Cesar Strauss
Start with a simpler test case
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commitdiff
2020-06-28
Cesar Strauss
Let p.ready_o be active while the test ALU is idle
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commitdiff
2020-06-28
Cesar Strauss
Add missing ports to the test ALU
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commitdiff
2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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commitdiff
2020-06-28
Luke Kenneth Casso...
add Config Fetch interface and quick unit test
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commitdiff
2020-06-28
Luke Kenneth Casso...
add test instruction memory
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commitdiff
2020-06-28
Luke Kenneth Casso...
add readonly option to TestMemory
tree
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commitdiff
2020-06-28
Luke Kenneth Casso...
got Pi2LSUI FSM working
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commitdiff
2020-06-28
Luke Kenneth Casso...
new Pi2LSUI working, using PortInterfaceBase
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commitdiff
2020-06-28
Luke Kenneth Casso...
start new version of Pi2LSUI based on PortInterfaceBase
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commitdiff
2020-06-28
Luke Kenneth Casso...
pass addr/mask through to PortInterfaceBase rd/wr addr
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commitdiff
2020-06-28
Luke Kenneth Casso...
cleanup (remove unneeded imports)
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commitdiff
2020-06-28
Luke Kenneth Casso...
more code-shuffle for TestMemoryPortInterface
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commitdiff
2020-06-28
Luke Kenneth Casso...
more code-shuffle for TestMemoryPortInterface
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commitdiff
2020-06-28
Luke Kenneth Casso...
minor cleanup, put get/set rdport/wrport into function
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commitdiff
2020-06-28
Luke Kenneth Casso...
merge LDSTPort into TestMemoryPortInterface
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commitdiff
2020-06-28
Luke Kenneth Casso...
use PortInterface connect_port
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commitdiff
2020-06-28
Luke Kenneth Casso...
use PortInterface connect_port
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commitdiff
2020-06-28
Luke Kenneth Casso...
attempt to get Pi2LSUI FSM working
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commitdiff
2020-06-27
Luke Kenneth Casso...
only activate ld_in_progress if addr is ok
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commitdiff
2020-06-27
Luke Kenneth Casso...
increase (double) address width in TstL0CacheBuffer
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commitdiff
2020-06-27
Luke Kenneth Casso...
unit test in l0_cache to connect to testpi and test_bare_wb
tree
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commitdiff
2020-06-27
Luke Kenneth Casso...
make PortInterface modules consistent with same API
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commitdiff
2020-06-27
Luke Kenneth Casso...
use ConfigMemoryPortInterface in TstL0CacheBuffer
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commitdiff
2020-06-27
Luke Kenneth Casso...
fix TestMemLoadStoreUnit, it required a FSM to monitor...
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commitdiff
2020-06-27
Luke Kenneth Casso...
add wishbone Pi2LSUI test
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commitdiff
2020-06-27
Luke Kenneth Casso...
reconfigureable PortInterface testing now possible
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commitdiff
2020-06-26
Luke Kenneth Casso...
name issue in Pi2LSUI
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commitdiff
2020-06-26
Luke Kenneth Casso...
slight reorg on test_pi2ls.py
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commitdiff
2020-06-26
Luke Kenneth Casso...
correct address in pi2ls
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commitdiff
2020-06-26
Luke Kenneth Casso...
oops forgot to initialise base class of TestMemLoadStor...
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commitdiff
2020-06-26
Luke Kenneth Casso...
add in LenExpand shift/mask
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commitdiff
2020-06-26
Luke Kenneth Casso...
add quick test showing Pi2LSUI not quite reading/writing to
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commitdiff
2020-06-26
Luke Kenneth Casso...
remove extraneous yields
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commitdiff
2020-06-26
Michael Nolan
Modify pi2ls so it passes the portinterface unit tests
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commitdiff
2020-06-26
Luke Kenneth Casso...
set address ok and fix unit test to check it properly
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commitdiff
2020-06-26
Luke Kenneth Casso...
add pi.busy_o connection, increase to 64 bit
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commitdiff
2020-06-26
Luke Kenneth Casso...
unit test broken is ok :)
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