2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-13 |
Cesar Strauss | Skip vector test case, and add a scalar case |
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2021-02-13 |
Cesar Strauss | Fix imports and whitespace |
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2021-02-13 |
Luke Kenneth Casso... | add SVP64 TestIssuer separate unit test |
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2021-02-12 |
Luke Kenneth Casso... | add one SVP64 ALU test case to get started |
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2021-01-31 |
Luke Kenneth Casso... | adjusting ISACaller unit test to use ISACaller.setup_one() |
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2020-10-16 |
Luke Kenneth Casso... | add LGPLv3+ notice and add copyright holders |
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2020-10-06 |
Luke Kenneth Casso... | use pdecode2.do not pdecode2.e in test_pipe_caller... |
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2020-09-26 |
Luke Kenneth Casso... | fix annoying alu test_pipe_caller bug, missing asmcode |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-09-07 |
Luke Kenneth Casso... | bit of a big reorg of data structures |
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2020-09-02 |
Luke Kenneth Casso... | fix bug in cmpli (and cmplw) |
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2020-09-02 |
Luke Kenneth Casso... | bug in carry32 handling in OP_CMP |
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2020-09-02 |
Luke Kenneth Casso... | add cmpl regression test (one binary, one assembly) |
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2020-09-02 |
Luke Kenneth Casso... | add cmpl microwatt 1.bin test, cmpl |
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2020-08-30 |
Luke Kenneth Casso... | redo OP_CMP based on microwatt. L=1 had been ignored |
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2020-08-27 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-27 |
Luke Kenneth Casso... | xer so is not being passed through to CR0 |
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2020-08-27 |
Luke Kenneth Casso... | augment addme test case to show bug #476 |
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2020-08-27 |
Luke Kenneth Casso... | add addze and addme uni tests |
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2020-08-27 |
Luke Kenneth Casso... | reorg of SO handling related to CR0 |
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2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-23 |
Michael Nolan | Add copyright to files in fu/ that I was the primary... |
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2020-08-22 |
Luke Kenneth Casso... | rename invert_a to invert_in because logical inverts RB |
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2020-08-22 |
Luke Kenneth Casso... | add regression test for nonzero addis |
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2020-08-22 |
Luke Kenneth Casso... | r0 zero tests on addis, fails |
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2020-08-17 |
Luke Kenneth Casso... | fix signed variants of cmp in alu |
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2020-08-17 |
Luke Kenneth Casso... | add new cmp test for alu |
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2020-08-16 |
Luke Kenneth Casso... | attempting to track down bug in litex bios memtest |
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2020-08-14 |
Luke Kenneth Casso... | divide alu pipeline into 2 (simple last) |
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2020-07-29 |
Luke Kenneth Casso... | move actual ALU test out of subTest indentation just... |
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2020-07-29 |
Jacob Lifshay | clean up alu test_pipe_caller |
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2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
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2020-07-29 |
Jacob Lifshay | format some tests |
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2020-07-26 |
Luke Kenneth Casso... | convert ALU to new accumulator style |
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2020-07-25 |
Luke Kenneth Casso... | add spec page numbers to logical ops |
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2020-07-25 |
Luke Kenneth Casso... | add page-number comments to ALU main_stage |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-21 |
Luke Kenneth Casso... | whitespace |
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2020-07-21 |
Luke Kenneth Casso... | make cxxsim optional and print warning |
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2020-07-19 |
Luke Kenneth Casso... | use same write_vcd for cxxsim as pysim |
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2020-07-19 |
Luke Kenneth Casso... | fix bug in alu_fsm.py found by cxxsim: missing one... |
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2020-07-15 |
Luke Kenneth Casso... | use Record Assert and also check muxid |
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2020-07-14 |
Luke Kenneth Casso... | reduce code size by using CompOpSubsetBase for ALU... |
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2020-07-14 |
Luke Kenneth Casso... | attempting running cxxsim on ALU pipeline test |
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2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
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2020-07-11 |
Luke Kenneth Casso... | sorting out bigendian/littleendian including in qemu |
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2020-07-09 |
Luke Kenneth Casso... | also set so only if OE requires it |
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2020-07-09 |
Luke Kenneth Casso... | whoops test gets copied 4 times on the If. |
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2020-07-09 |
Luke Kenneth Casso... | ALU output stage, change logic slightly |
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2020-07-09 |
Luke Kenneth Casso... | clarifying comments on setting xer_ov/so |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
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2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
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2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-06-11 |
Luke Kenneth Casso... | read and write version of get_sim_xer_ca are different |
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2020-06-11 |
Luke Kenneth Casso... | rename get_sim_cr_a to get_wr_sim_cr_a for now |
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2020-06-10 |
Luke Kenneth Casso... | use sim-get helpers in ALU input fetch |
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2020-06-10 |
Luke Kenneth Casso... | continue ALUHelpers check alu outputs code-morph |
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2020-06-10 |
Luke Kenneth Casso... | code-morph ALU output test check phase |
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2020-06-10 |
Luke Kenneth Casso... | code-munge test_pipe_caller for ALU, |
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2020-06-08 |
Luke Kenneth Casso... | more verbose debug information tracking down SO/OV... |
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2020-06-08 |
Luke Kenneth Casso... | set only the SO bit as sticky, not the OV flags as... |
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2020-06-08 |
Luke Kenneth Casso... | clarify using microwatt calc_ov function. |
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2020-06-08 |
Luke Kenneth Casso... | added check which shows that OV32 in "adde." is not... |
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2020-06-07 |
Luke Kenneth Casso... | add extra missing args to ISA setup in alu test_pipe_caller |
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2020-06-06 |
Luke Kenneth Casso... | update stage docstring |
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2020-06-06 |
Luke Kenneth Casso... | code-munge |
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2020-06-06 |
Luke Kenneth Casso... | remove unneeded imports |
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2020-06-06 |
Luke Kenneth Casso... | noticed the regular pattern in all pipe_data.py (regspecs). |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
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2020-06-04 |
Luke Kenneth Casso... | use common TestCase in alu |
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2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | reorganise ALU tests, move get_cu_inputs function to... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | attempt to make carry-in and overflow-enable optional... |
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2020-06-03 |
Luke Kenneth Casso... | remove rdflags in pipe_data.py (redundant) |
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2020-06-02 |
Luke Kenneth Casso... | rename regspecs to give a consistent naming scheme |
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2020-06-01 |
Luke Kenneth Casso... | okaaay add a "rdflags" function which obtains the yes... |
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2020-06-01 |
Luke Kenneth Casso... | RS moved to port 1 (from port 3), remove need in ALU... |
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2020-05-31 |
Luke Kenneth Casso... | clarify |
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2020-05-31 |
Luke Kenneth Casso... | OP_CMPEQB also requesting change of output reg (stop... |
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2020-05-31 |
Luke Kenneth Casso... | OP_CMP is requesting a change of the output register... |
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2020-05-31 |
Luke Kenneth Casso... | still investigating |
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2020-05-31 |
Luke Kenneth Casso... | start with zero, try not to compare against 9 bytes... |
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2020-05-31 |
Luke Kenneth Casso... | add in more CR debug statements |
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2020-05-31 |
Luke Kenneth Casso... | remove commented-out vars from ALU input record |
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2020-05-31 |
Luke Kenneth Casso... | add write_cr to ALU record subset |
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2020-05-30 |
Luke Kenneth Casso... | select CR0 write out only when RC=1 |
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2020-05-28 |
Luke Kenneth Casso... | remove trick of not setting SO |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | LogicalOutputData does not need XER.so |
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2020-05-27 |
Luke Kenneth Casso... | comments |
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2020-05-27 |
Luke Kenneth Casso... | check cr0, ov and ca ok signals in ALU main_stage proof |
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2020-05-27 |
Luke Kenneth Casso... | add carry-out, overflow and cr0 ok setting in ALU main_... |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | add links to bugreports into ALu formal proof as well |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | add links to bugreports into alu output stage proof |
tree | commitdiff |
2020-05-27 |
Michael Nolan | Fix bug in alu main stage proof |
tree | commitdiff |
2020-05-24 |
Luke Kenneth Casso... | convert ALU to output Data on int reg |
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