| 2021-12-21 |
Luke Kenneth Casso... | for each unit test case in test_issuer_mmu_data_path... |
tree | commitdiff |
| 2021-12-21 |
Luke Kenneth Casso... | test_issuer_mmu_data_path.py needs to use wb_get because of |
tree | commitdiff |
| 2021-12-20 |
Luke Kenneth Casso... | unit tests for SPRs when MMU enabled, |
tree | commitdiff |
| 2021-12-18 |
Luke Kenneth Casso... | forgot to connect up I-Cache to MMU |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | get OP_FETCH_FAILED to respond/return an exception... |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | MMU LOOKUP for fetch failed, priv mode is inversion... |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | link MSR.PR into MMU FSM OP_FETCH_FAILED |
tree | commitdiff |
| 2021-12-13 |
Luke Kenneth Casso... | add msr to MMU Op Subset record |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | delay MMU LOOKUP done by one clock so that the exceptio... |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | bring MMU exception out where AllFunctionUnits (and... |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | bring exception out from MMU FSM, correct "done" |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | add LDSTException output to MMU |
tree | commitdiff |
| 2021-12-09 |
Luke Kenneth Casso... | add I-Cache to FSM local variables |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | add parent_pspec everywhere |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | format code |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | add OP_FETCH_FAILED to MMU Function Unit |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | remove MSR and add CIA to MMU Input Record |
tree | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | wishbone bus convert on dcache |
tree | commitdiff |
| 2021-12-04 |
Luke Kenneth Casso... | sigh in MMU FSM use direct access to ldst.dar/dsisr... |
tree | commitdiff |
| 2021-12-04 |
Luke Kenneth Casso... | add means to update dsisr from MMU FSM. TODO: add a... |
tree | commitdiff |
| 2021-12-03 |
Luke Kenneth Casso... | priv_mode/virt_mode are set in the request, which is... |
tree | commitdiff |
| 2021-12-03 |
Luke Kenneth Casso... | comment out dsisr and dar in mmu FSM for now |
tree | commitdiff |
| 2021-11-10 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
| 2021-11-08 |
Tobias Platen | mmu unit test working again |
tree | commitdiff |
| 2021-11-06 |
Tobias Platen | update test_issuer_mmu.py testcase, add needed debug... |
tree | commitdiff |
| 2021-11-04 |
Luke Kenneth Casso... | fix missing naming ready_i -> i_ready |
tree | commitdiff |
| 2021-11-03 |
Tobias Platen | cleanup fsm |
tree | commitdiff |
| 2021-11-03 |
Tobias Platen | add first tlbie test case |
tree | commitdiff |
| 2021-11-02 |
Tobias Platen | mmu fsm: symbols have been renamed |
tree | commitdiff |
| 2021-11-02 |
Tobias Platen | hack to fix UnusedElaboratables in src/soc/fu/mmu/test... |
tree | commitdiff |
| 2021-11-01 |
Tobias Platen | hack: resolve DriverConflict in src/soc/fu/mmu/fsm.py |
tree | commitdiff |
| 2021-09-03 |
Luke Kenneth Casso... | another batch of ready/valid i/o prefix-suffix swaps |
tree | commitdiff |
| 2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
tree | commitdiff |
| 2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
tree | commitdiff |
| 2021-05-11 |
Luke Kenneth Casso... | whoops names changed in MMU FSM |
tree | commitdiff |
| 2021-05-09 |
Luke Kenneth Casso... | add MMU bugtracker link |
tree | commitdiff |
| 2021-05-09 |
Luke Kenneth Casso... | preference is to create a temp variable for comb and... |
tree | commitdiff |
| 2021-05-08 |
Luke Kenneth Casso... | add bugreport link to mmu |
tree | commitdiff |
| 2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
tree | commitdiff |
| 2021-05-07 |
Luke Kenneth Casso... | update comments and docstrings |
tree | commitdiff |
| 2021-05-07 |
Luke Kenneth Casso... | whoops, import error |
tree | commitdiff |
| 2021-05-07 |
Luke Kenneth Casso... | move LoadStore1 class to soc.fu.ldst.loadstore |
tree | commitdiff |
| 2021-05-07 |
Luke Kenneth Casso... | move dsisr and dar into LoadStore1 |
tree | commitdiff |
| 2021-05-05 |
Tobias Platen | fix bug in mmu/fsm.py |
tree | commitdiff |
| 2021-05-04 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
| 2021-05-04 |
Tobias Platen | implement MFSPR the same way as fu/spr/main_stage.py |
tree | commitdiff |
| 2021-05-04 |
Tobias Platen | upate dsisr and dar using sync |
tree | commitdiff |
| 2021-05-04 |
Luke Kenneth Casso... | more rename of exception_o to exc_o, add convenience... |
tree | commitdiff |
| 2021-05-04 |
Luke Kenneth Casso... | rename IntegerData to FUBaseData |
tree | commitdiff |
| 2021-05-04 |
Luke Kenneth Casso... | comment out nc (nocache), it seems to actually work |
tree | commitdiff |
| 2021-05-03 |
Luke Kenneth Casso... | MMU: get store to activate only when data is available... |
tree | commitdiff |
| 2021-05-03 |
Luke Kenneth Casso... | disable the cache for now, whilst testing read/write... |
tree | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | use Const to define bit-length when comparing top nibbl... |
tree | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | mmu FSM store in dcache: only put data onto d_in on... |
tree | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | return d_out.valid instead of always "ok" in MMU FSM |
tree | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | HACK WARNING: disable d-cache on hard-coded address... |
tree | commitdiff |
| 2021-05-01 |
Luke Kenneth Casso... | store data in microwatt dcache goes in one cycle AFTER... |
tree | commitdiff |
| 2021-05-01 |
Luke Kenneth Casso... | only do dcache lookup for now |
tree | commitdiff |
| 2021-04-30 |
Luke Kenneth Casso... | debug and stop on mmu test_pipe_caller.py |
tree | commitdiff |
| 2021-04-30 |
Luke Kenneth Casso... | comments on dcache-to-mmu link |
tree | commitdiff |
| 2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
tree | commitdiff |
| 2021-04-30 |
Luke Kenneth Casso... | hook up dcache wb_in/out to PortInterfaceBase Wishbone... |
tree | commitdiff |
| 2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
tree | commitdiff |
| 2021-04-29 |
Luke Kenneth Casso... | comment out adding mmu and dcache to pspec in MMU FSM |
tree | commitdiff |
| 2021-04-29 |
Luke Kenneth Casso... | move dcache into Loadstore1 |
tree | commitdiff |
| 2021-04-27 |
Luke Kenneth Casso... | return read data out from Loadstore1 only when valid |
tree | commitdiff |
| 2021-04-26 |
Luke Kenneth Casso... | hook up MSR into MMU (TODO, use a lot less bits) |
tree | commitdiff |
| 2021-04-23 |
Luke Kenneth Casso... | move MMU Testcase to openpower.test |
tree | commitdiff |
| 2021-04-23 |
Luke Kenneth Casso... | import from openpower.endian |
tree | commitdiff |
| 2021-04-23 |
Luke Kenneth Casso... | use openpower.test.common |
tree | commitdiff |
| 2021-04-23 |
Luke Kenneth Casso... | more openpower-isa conversion |
tree | commitdiff |
| 2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
tree | commitdiff |
| 2021-04-20 |
Luke Kenneth Casso... | cannot pass in arguments to Core - must be done with... |
tree | commitdiff |
| 2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
| 2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
tree | commitdiff |
| 2021-03-02 |
Luke Kenneth Casso... | comment out changing SPR 720 because 720 is not support... |
tree | commitdiff |
| 2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
tree | commitdiff |
| 2021-03-02 |
Luke Kenneth Casso... | operating correctly, not directing MMU SPRs to SPR... |
tree | commitdiff |
| 2021-03-02 |
Luke Kenneth Casso... | must always set ok for writing out data otherwise it... |
tree | commitdiff |
| 2021-02-24 |
Tobias Platen | update mmu testcase |
tree | commitdiff |
| 2021-02-20 |
Luke Kenneth Casso... | correct arguments, set microwatt_mmu=True, pass in... |
tree | commitdiff |
| 2021-02-20 |
Luke Kenneth Casso... | minor whitespace cleanup |
tree | commitdiff |
| 2021-02-20 |
Tobias Platen | mmu testcase: set MMU SPRs |
tree | commitdiff |
| 2021-02-20 |
Tobias Platen | add rom debugger |
tree | commitdiff |
| 2021-02-20 |
Tobias Platen | add mmu rom testcase |
tree | commitdiff |
| 2021-02-18 |
Tobias Platen | mmu: remove TestMemory |
tree | commitdiff |
| 2021-02-16 |
Tobias Platen | mmureq handling |
tree | commitdiff |
| 2021-02-16 |
Tobias Platen | dcache error handling |
tree | commitdiff |
| 2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
| 2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
tree | commitdiff |
| 2021-02-05 |
Tobias Platen | fix hanging simulation |
tree | commitdiff |
| 2021-02-04 |
Tobias Platen | src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave |
tree | commitdiff |
| 2021-02-04 |
Tobias Platen | update test_issuer_mmu_data_path.py to handle SPRs |
tree | commitdiff |
| 2021-01-19 |
Tobias Platen | test_issuer_mmu_data_path.py: test both ld and st instr... |
tree | commitdiff |
| 2021-01-19 |
Tobias Platen | connect LDSTException to MMU and DCache |
tree | commitdiff |
| 2021-01-19 |
Tobias Platen | connect wishbone bus to test memory |
tree | commitdiff |
| 2021-01-18 |
Tobias Platen | fu/mmu/fsm.py: connect valid and load signals |
tree | commitdiff |
| 2021-01-17 |
Tobias Platen | add test memory for simulation |
tree | commitdiff |
| 2021-01-17 |
Tobias Platen | cleanup test_issuer_mmu_data_path.py |
tree | commitdiff |
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