whoops names changed in MMU FSM
[soc.git] / src / soc / simple /
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1
2021-05-09 Luke Kenneth Casso... add comment about LD/ST exception needs copying into...
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that...
2021-05-07 Luke Kenneth Casso... whoops setup of core.sv_pred_sm/dm not indented and...
2021-05-06 Luke Kenneth Casso... whoops disabled tests agaaaaain
2021-05-06 Luke Kenneth Casso... pass relevant predicate mask bits through to Decoders...
2021-05-06 Luke Kenneth Casso... add in predicate mask bit detection when zeroing is...
2021-05-06 Luke Kenneth Casso... pass SVP64 ReMap field through to core and then on...
2021-05-06 Luke Kenneth Casso... moved exts* SVP64 unit tests to a different location
2021-05-05 Luke Kenneth Casso... whoops wrong signal name, set exc_happened
2021-05-04 Luke Kenneth Casso... whoops disabled some test_issuer group tests
2021-05-04 Luke Kenneth Casso... new fast3 needs to be remapped to fast1 port in "reduce...
2021-05-04 Luke Kenneth Casso... add TODO comments and cross-reference to bug
2021-05-04 Luke Kenneth Casso... note a way to see if an exception happened, in TestIssuer
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit
2021-05-01 Luke Kenneth Casso... enable issuer_verilog.py to generate new MMU/DCache...
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test.
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth Casso... add LD/ST cases to MMU, which should all still work
2021-05-01 Luke Kenneth Casso... add MMUTestCaseROM
2021-05-01 Luke Kenneth Casso... use new AllFunctionUnits.get_fu function
2021-05-01 Luke Kenneth Casso... use SPRreduced to match PowerDecoder2
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte...
2021-04-30 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=635
2021-04-30 Luke Kenneth Casso... better reporting on gpr comparisons
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-25 Cesar StraussShift-out skipped mask bits for both crpred and intpred
2021-04-24 Luke Kenneth Casso... whitespace
2021-04-23 Luke Kenneth Casso... add comments on TestIssuer TestRunner
2021-04-23 Luke Kenneth Casso... comment tests back in
2021-04-23 Luke Kenneth Casso... error in setting fast regs test values
2021-04-23 Luke Kenneth Casso... import from openpower.tests
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-22 Cesar StraussImplement CR predication
2021-04-21 Cesar StraussCR sub-fields are stored in MSB0 order
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu
2021-04-21 Cesar StraussFix sense of "invert" signal
2021-04-20 Luke Kenneth Casso... add enable MMU option to issuer_verilog.py
2021-04-18 Luke Kenneth Casso... create signal on test_issuer which gives PLL clk_sel_i...
2021-04-18 Luke Kenneth Casso... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth Casso... core_stopped_i unused: remove
2021-04-17 Cesar StraussImplement 1<<r3 directly by a shift
2021-04-10 Cesar StraussImplement 1<<r3 predicate mode
2021-04-09 Luke Kenneth Casso... test firmware upload program needed to branch back...
2021-04-08 Luke Kenneth Casso... sort out pc reset when DMI interface requests reset
2021-04-06 Cesar StraussMake the VL loop reentrant in HDL
2021-04-03 Cesar StraussReminder for a possible hardware optimization
2021-04-03 Cesar StraussBe more precise when using a one-bit constant
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-04-03 Cesar StraussSignal the simulator when completing a VL loop
2021-04-01 Luke Kenneth Casso... TWI enabled in JTAG boundary scan
2021-04-01 Luke Kenneth Casso... reduce subset of functions to be created in JTAG bounda...
2021-04-01 Luke Kenneth Casso... bug in iverilog, segfaults due to empty case statement
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Cesar StraussSkip leading zero bits on predicate masks
2021-03-30 Luke Kenneth Casso... use port name for INT regfile to match up with test_run...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-28 Luke Kenneth Casso... svp64-enable passed through to PowerDecoderSubsets...
2021-03-28 Cesar StraussMove DECODE_SV to its place between MASK_WAIT and INSN_...
2021-03-28 Cesar StraussMove instruction decoding to after predication
2021-03-28 Cesar StraussPrepare to advance src/dst step after getting the predi...
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-28 Luke Kenneth Casso... add option to reduce number of regfile ports (get DFFs...
2021-03-28 Luke Kenneth Casso... reduce number of regfile ports
2021-03-28 Luke Kenneth Casso... reduce regfile port usage on non-svp64
2021-03-24 Luke Kenneth Casso... comment about using PriorityEncoder
2021-03-22 Luke Kenneth Casso... do not set sv_changed
2021-03-22 Luke Kenneth Casso... make sure non-svp64-mode works
2021-03-22 Luke Kenneth Casso... have get_predint return indicator that mask is all 1s
2021-03-22 Cesar StraussSkip fetching integer predicate mask when register...
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding
2021-03-22 Cesar StraussDecode and fetch integer predicate registers
2021-03-21 Cesar StraussFix typo
2021-03-21 Cesar StraussAdd unique name to decoded predication signals
2021-03-21 Cesar StraussRevert removal of *.value from Enums
2021-03-21 Cesar StraussFix syntax
2021-03-21 Luke Kenneth Casso... more TODO comments
2021-03-21 Luke Kenneth Casso... add for-loop pseudocode for CR predicate mask reading
2021-03-21 Luke Kenneth Casso... code comments in TestIssuer
2021-03-21 Cesar StraussStart work on the predicate fetch FSM
2021-03-20 Luke Kenneth Casso... more pseudocode in TestIssuer
2021-03-20 Luke Kenneth Casso... add harmless code and commented-out pseudocode for...
2021-03-19 Luke Kenneth Casso... more comments for TestIssuer when adding predication
2021-03-19 Luke Kenneth Casso... comments for TestIssuer get_predint and get_predcr
2021-03-19 Luke Kenneth Casso... add more pieces of predication reading puzzle to TestIssuer
2021-03-19 Luke Kenneth Casso... cleanup TestIssuer (comments)
2021-03-19 Luke Kenneth Casso... spelling
2021-03-19 Luke Kenneth Casso... code-shuffle in TestIssuer, split out setting up periph...
2021-03-19 Luke Kenneth Casso... move duplicated code to a function in TestIssuer
2021-03-18 Luke Kenneth Casso... more hint/comments
2021-03-18 Luke Kenneth Casso... update TestIssuer comments
2021-03-18 Luke Kenneth Casso... add comments on most likely place to put predicate...
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