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add misalign flag to PortInterfaceBase
[soc.git]
/
src
/
soc
/
simple
/
2021-05-07
Luke Kenneth Casso...
how we managed to get this far without noticing that...
tree
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commitdiff
2021-05-07
Luke Kenneth Casso...
whoops setup of core.sv_pred_sm/dm not indented and...
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
whoops disabled tests agaaaaain
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
pass relevant predicate mask bits through to Decoders...
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
add in predicate mask bit detection when zeroing is...
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
pass SVP64 ReMap field through to core and then on...
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
moved exts* SVP64 unit tests to a different location
tree
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commitdiff
2021-05-05
Luke Kenneth Casso...
whoops wrong signal name, set exc_happened
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
whoops disabled some test_issuer group tests
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
new fast3 needs to be remapped to fast1 port in "reduce...
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
add TODO comments and cross-reference to bug
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
note a way to see if an exception happened, in TestIssuer
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
code-comments for LDSTCompUnit
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
enable issuer_verilog.py to generate new MMU/DCache...
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
send a DMI RESET at the end of the test.
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
store data in microwatt dcache goes in one cycle AFTER...
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
add LD/ST cases to MMU, which should all still work
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
add MMUTestCaseROM
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
use new AllFunctionUnits.get_fu function
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
use SPRreduced to match PowerDecoder2
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add a TestSRAM variant of LoadStore1, for being able...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add basic test_issuer_mmu.py
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add option to use new mmu_cache_wb ConfigMemoryPortInte...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=635
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
better reporting on gpr comparisons
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
set up LoadStore1 in ConfigMemoryPortInterface and...
tree
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commitdiff
2021-04-25
Cesar Strauss
Shift-out skipped mask bits for both crpred and intpred
tree
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commitdiff
2021-04-24
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
add comments on TestIssuer TestRunner
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
comment tests back in
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
error in setting fast regs test values
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
import from openpower.tests
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
use openpower.test.common
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
move more files to openpower-isa
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
more openpower-isa conversion
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
correct migration of openpower-isa
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
tree
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commitdiff
2021-04-22
Cesar Strauss
Implement CR predication
tree
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commitdiff
2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
tree
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commitdiff
2021-04-21
Tobias Platen
testcase: pass PRTBL to mmu
tree
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commitdiff
2021-04-21
Cesar Strauss
Fix sense of "invert" signal
tree
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commitdiff
2021-04-20
Luke Kenneth Casso...
add enable MMU option to issuer_verilog.py
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
create signal on test_issuer which gives PLL clk_sel_i...
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
core_stopped_i unused: remove
tree
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commitdiff
2021-04-17
Cesar Strauss
Implement 1<<r3 directly by a shift
tree
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commitdiff
2021-04-10
Cesar Strauss
Implement 1<<r3 predicate mode
tree
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commitdiff
2021-04-09
Luke Kenneth Casso...
test firmware upload program needed to branch back...
tree
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commitdiff
2021-04-08
Luke Kenneth Casso...
sort out pc reset when DMI interface requests reset
tree
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commitdiff
2021-04-06
Cesar Strauss
Make the VL loop reentrant in HDL
tree
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commitdiff
2021-04-03
Cesar Strauss
Reminder for a possible hardware optimization
tree
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commitdiff
2021-04-03
Cesar Strauss
Be more precise when using a one-bit constant
tree
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commitdiff
2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
tree
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commitdiff
2021-04-03
Cesar Strauss
Signal the simulator when completing a VL loop
tree
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commitdiff
2021-04-01
Luke Kenneth Casso...
TWI enabled in JTAG boundary scan
tree
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commitdiff
2021-04-01
Luke Kenneth Casso...
reduce subset of functions to be created in JTAG bounda...
tree
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commitdiff
2021-04-01
Luke Kenneth Casso...
bug in iverilog, segfaults due to empty case statement
tree
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commitdiff
2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2021-03-30
Cesar Strauss
Skip leading zero bits on predicate masks
tree
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commitdiff
2021-03-30
Luke Kenneth Casso...
use port name for INT regfile to match up with test_run...
tree
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commitdiff
2021-03-30
Cesar Strauss
Memory port seems to have been renamed
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
svp64-enable passed through to PowerDecoderSubsets...
tree
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commitdiff
2021-03-28
Cesar Strauss
Move DECODE_SV to its place between MASK_WAIT and INSN_...
tree
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commitdiff
2021-03-28
Cesar Strauss
Move instruction decoding to after predication
tree
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commitdiff
2021-03-28
Cesar Strauss
Prepare to advance src/dst step after getting the predi...
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
add option to reduce number of regfile ports (get DFFs...
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
reduce number of regfile ports
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
reduce regfile port usage on non-svp64
tree
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commitdiff
2021-03-24
Luke Kenneth Casso...
comment about using PriorityEncoder
tree
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commitdiff
2021-03-22
Luke Kenneth Casso...
do not set sv_changed
tree
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commitdiff
2021-03-22
Luke Kenneth Casso...
make sure non-svp64-mode works
tree
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commitdiff
2021-03-22
Luke Kenneth Casso...
have get_predint return indicator that mask is all 1s
tree
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commitdiff
2021-03-22
Cesar Strauss
Skip fetching integer predicate mask when register...
tree
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commitdiff
2021-03-22
Cesar Strauss
Add traces for the new FSM and integer predicate decoding
tree
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commitdiff
2021-03-22
Cesar Strauss
Decode and fetch integer predicate registers
tree
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commitdiff
2021-03-21
Cesar Strauss
Fix typo
tree
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commitdiff
2021-03-21
Cesar Strauss
Add unique name to decoded predication signals
tree
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commitdiff
2021-03-21
Cesar Strauss
Revert removal of *.value from Enums
tree
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commitdiff
2021-03-21
Cesar Strauss
Fix syntax
tree
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commitdiff
2021-03-21
Luke Kenneth Casso...
more TODO comments
tree
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commitdiff
2021-03-21
Luke Kenneth Casso...
add for-loop pseudocode for CR predicate mask reading
tree
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commitdiff
2021-03-21
Luke Kenneth Casso...
code comments in TestIssuer
tree
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commitdiff
2021-03-21
Cesar Strauss
Start work on the predicate fetch FSM
tree
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commitdiff
2021-03-20
Luke Kenneth Casso...
more pseudocode in TestIssuer
tree
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commitdiff
2021-03-20
Luke Kenneth Casso...
add harmless code and commented-out pseudocode for...
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
more comments for TestIssuer when adding predication
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
comments for TestIssuer get_predint and get_predcr
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
add more pieces of predication reading puzzle to TestIssuer
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
cleanup TestIssuer (comments)
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
spelling
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
code-shuffle in TestIssuer, split out setting up periph...
tree
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commitdiff
2021-03-19
Luke Kenneth Casso...
move duplicated code to a function in TestIssuer
tree
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commitdiff
2021-03-18
Luke Kenneth Casso...
more hint/comments
tree
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commitdiff
2021-03-18
Luke Kenneth Casso...
update TestIssuer comments
tree
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commitdiff
2021-03-18
Luke Kenneth Casso...
add comments on most likely place to put predicate...
tree
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commitdiff
2021-03-18
Luke Kenneth Casso...
comments TestIssuer, add a stub FSM
tree
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commitdiff
2021-03-17
Luke Kenneth Casso...
add SVP64 dststep incrementing in PowerDecoder2, Testis...
tree
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commitdiff
2021-03-14
Cesar Strauss
Activate the VL==0 loop with any SVP64 prefix whatsoever
tree
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commitdiff
2021-03-12
Luke Kenneth Casso...
use PowerDecoder2.loop_continue instead of no_out_vec
tree
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commitdiff
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