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Revert "working on div's test_pipe_caller"
[soc.git] / src / soc / simple /
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting tree | commitdiff
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide tree | commitdiff
2020-07-23 Luke Kenneth Casso... begin core in running state tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Jacob Lifshayformat code tree | commitdiff
2020-07-22 Luke Kenneth Casso... missing ports from issuer, when doing verilog tree | commitdiff
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports tree | commitdiff
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into... tree | commitdiff
2020-07-19 Luke Kenneth Casso... do not start core in terminated mode tree | commitdiff
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py tree | commitdiff
2020-07-19 Luke Kenneth Casso... expose core_stop_i to outside as well tree | commitdiff
2020-07-19 Luke Kenneth Casso... set go_insn_i to non-resetless tree | commitdiff
2020-07-19 Luke Kenneth Casso... add issuer verilog generator tree | commitdiff
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer tree | commitdiff
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for... tree | commitdiff
2020-07-18 Luke Kenneth Casso... add option to generate verilog tree | commitdiff
2020-07-14 Luke Kenneth Casso... add MSR reading to issue FSM tree | commitdiff
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp tree | commitdiff
2020-07-12 Luke Kenneth Casso... add OP_ATTN test back in tree | commitdiff
2020-07-12 Luke Kenneth Casso... exit FSM when termination detected tree | commitdiff
2020-07-12 Luke Kenneth Casso... code-morph on core connect_instruction tree | commitdiff
2020-07-12 Luke Kenneth Casso... msb of instruction causing sign-overflow tree | commitdiff
2020-07-11 Luke Kenneth Casso... sort out core write latching: gate by busy, and use... tree | commitdiff
2020-07-11 Luke Kenneth Casso... * clarifying core function unit enable tree | commitdiff
2020-07-11 Luke Kenneth Casso... fix spr setting, set endianness tree | commitdiff
2020-07-11 Luke Kenneth Casso... more setting bigendian tree | commitdiff
2020-07-11 Luke Kenneth Casso... add bigendian mode to helloworld test tree | commitdiff
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim tree | commitdiff
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs tree | commitdiff
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs tree | commitdiff
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup tree | commitdiff
2020-07-08 Luke Kenneth Casso... sorting out setting of XER tree | commitdiff
2020-07-08 Luke Kenneth Casso... got test_issuer operational on one unit test tree | commitdiff
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking... tree | commitdiff
2020-07-08 Luke Kenneth Casso... copy binary loaded from disk into data memory as well tree | commitdiff
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-07 Luke Kenneth Casso... add hello world binary test tree | commitdiff
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working tree | commitdiff
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files... tree | commitdiff
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems... tree | commitdiff
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN) tree | commitdiff
2020-07-07 Luke Kenneth Casso... update opcode map for OP_ATTN tree | commitdiff
2020-07-07 Luke Kenneth Casso... debugging termination / OP_ATTN tree | commitdiff
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support tree | commitdiff
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py tree | commitdiff
2020-07-06 Luke Kenneth Casso... add mul unit to test_issuer tree | commitdiff
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type tree | commitdiff
2020-07-05 Luke Kenneth Casso... add SPR test case, commented out for now tree | commitdiff
2020-07-05 Luke Kenneth Casso... move valid signal out of Decode2ToExecute1Type and... tree | commitdiff
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support tree | commitdiff
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py tree | commitdiff
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py tree | commitdiff
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs tree | commitdiff
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports tree | commitdiff
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core tree | commitdiff
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion tree | commitdiff
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit tree | commitdiff
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface tree | commitdiff
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a... tree | commitdiff
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API tree | commitdiff
2020-06-23 Luke Kenneth Casso... TstL0CacheBuffer returns array of ports differently now tree | commitdiff
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer tree | commitdiff
2020-06-18 Luke Kenneth Casso... got loop example operational by noting when PC fastreg... tree | commitdiff
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer... tree | commitdiff
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases tree | commitdiff
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC tree | commitdiff
2020-06-18 Luke Kenneth Casso... whoops generate core ilang not TestIssuer tree | commitdiff
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module tree | commitdiff
2020-06-17 Luke Kenneth Casso... remove unneeded yield tree | commitdiff
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py tree | commitdiff
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack tree | commitdiff
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working tree | commitdiff
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd tree | commitdiff
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer tree | commitdiff
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer tree | commitdiff
2020-06-16 Luke Kenneth Casso... move debug statements to check function tree | commitdiff
2020-06-16 Luke Kenneth Casso... hack LD/ST ad/st together, allow PC to be set externally tree | commitdiff
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function tree | commitdiff
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function tree | commitdiff
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct... tree | commitdiff
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio... tree | commitdiff
2020-06-16 Luke Kenneth Casso... weird: adding TestMemory with no port causes nmigen... tree | commitdiff
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core tree | commitdiff
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM tree | commitdiff
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up... tree | commitdiff
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests... tree | commitdiff
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU... tree | commitdiff
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily tree | commitdiff
2020-06-10 Luke Kenneth Casso... code-morph regspecmap functions, split into separate... tree | commitdiff
2020-06-08 Luke Kenneth Casso... re-add unit tests back in tree | commitdiff
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV... tree | commitdiff
2020-06-08 Luke Kenneth Casso... code-morph test_core for XER bit clarity tree | commitdiff
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not... tree | commitdiff
2020-06-07 Luke Kenneth Casso... assert XER SO/OV/CA registers, check these are ok ... tree | commitdiff
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in... tree | commitdiff
2020-06-07 Luke Kenneth Casso... add msr to ISA in test_core.py tree | commitdiff
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core tree | commitdiff
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now tree | commitdiff
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right tree | commitdiff
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