2021-06-18 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: keep data for the whole... |
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2021-06-14 |
Tobias Platen | update testcase for ldst |
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2021-06-10 |
Luke Kenneth Casso... | whoops Popcount datalen too big (wasted bits). reduce |
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2021-06-09 |
Luke Kenneth Casso... | git submodule update |
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2021-06-09 |
Luke Kenneth Casso... | disconnect pll clock, connected in peripheral interconnect |
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2021-06-09 |
Luke Kenneth Casso... | add in/out of ref_clk and pllclk_clk when PLL enabled |
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2021-06-06 |
Cesar Strauss | Start a new self-contained test suite for LDSTCompUnit |
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2021-06-03 |
Luke Kenneth Casso... | comment out domains that have already been created |
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2021-06-03 |
Luke Kenneth Casso... | no, do not assign clock to clock! |
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2021-06-03 |
Luke Kenneth Casso... | rename ref to ref_v in PLL due to ref being a verilog... |
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2021-06-03 |
Luke Kenneth Casso... | sort out PLL domains but bypass PLL due to lack of... |
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2021-06-03 |
Luke Kenneth Casso... | use DomainRenamer on all sub-components of TestIssuer |
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2021-06-03 |
Luke Kenneth Casso... | make core_rst a member of TestIssuerInternal |
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2021-06-01 |
Tobias Platen | test_ldst_pi.py: add new test case |
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2021-05-29 |
Tobias Platen | test_ldst_pi.py: first version of test_dcache_random() |
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2021-05-29 |
Tobias Platen | test_ldst_pi.py: more test_dcache_regression() |
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2021-05-27 |
Luke Kenneth Casso... | adjust PLL connections looking for coriolis2 issue |
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2021-05-27 |
Luke Kenneth Casso... | corrections on spblock ack |
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2021-05-27 |
Luke Kenneth Casso... | classic wishbone mode: must not do ack if already acked |
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2021-05-26 |
Luke Kenneth Casso... | arse. PLL test_issuer clk_sel_i accidentally only 1... |
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2021-05-26 |
Luke Kenneth Casso... | remove err feature from sram4k wb |
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2021-05-26 |
Luke Kenneth Casso... | add ldst PortInterface misalign unit test (underway) |
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2021-05-26 |
Luke Kenneth Casso... | rename PLL signals |
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2021-05-25 |
Tobias Platen | test_ldst_pi.py: fix race condition causing early stop |
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2021-05-25 |
Tobias Platen | wait_ldok: add debug output count |
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2021-05-24 |
Luke Kenneth Casso... | whoops sort out name of SPBlock RAM |
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2021-05-24 |
Luke Kenneth Casso... | change name of submodule to real_pll |
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2021-05-24 |
Luke Kenneth Casso... | match up PLL names |
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2021-05-22 |
Cesar Strauss | Move the reset code outside of the sub-test |
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2021-05-22 |
Luke Kenneth Casso... | update submodule |
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2021-05-22 |
Luke Kenneth Casso... | update PLL to use Instance |
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2021-05-15 |
Tobias Platen | test_ldst_pi.py: add dcache regression and random test... |
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2021-05-14 |
Luke Kenneth Casso... | add radix MMU "miss" test |
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2021-05-14 |
Luke Kenneth Casso... | clear out request data on return to idle |
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2021-05-14 |
Luke Kenneth Casso... | sort out LoadStore1 misalignment FSM, also required... |
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2021-05-14 |
Luke Kenneth Casso... | remove minerva units previously missed in cleanout |
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2021-05-14 |
Luke Kenneth Casso... | add misaligned load through MMU (which is incorrectly... |
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2021-05-13 |
Luke Kenneth Casso... | minor rework of wb_get, make generic |
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2021-05-13 |
Luke Kenneth Casso... | added STORE test in test_ldst_pi.py, and it worked... |
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2021-05-13 |
Luke Kenneth Casso... | update comments in issuer.py regarding a 4th FSM |
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2021-05-13 |
Luke Kenneth Casso... | yet more debug log stuff for DCache, this time on Cache... |
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2021-05-13 |
Luke Kenneth Casso... | fix wb_get error where data was being corrupted |
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2021-05-13 |
Luke Kenneth Casso... | add read at different locations in test_ldst_pi.py |
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2021-05-13 |
Luke Kenneth Casso... | add some data for MMU to actually look up |
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2021-05-13 |
Luke Kenneth Casso... | ha, hilarious: swapped TLBUpdate output sizes db_out... |
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2021-05-13 |
Luke Kenneth Casso... | whoops TLBIE must *clear* the valid bit not set it... |
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2021-05-13 |
Luke Kenneth Casso... | more debug Display in dcache.py |
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2021-05-13 |
Luke Kenneth Casso... | putting in a lot more debug print statements in DCache... |
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2021-05-12 |
Luke Kenneth Casso... | add dcache tlb / pte test |
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2021-05-12 |
Luke Kenneth Casso... | set m_out.load from ldst_r(egister) in LoadStore1 |
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2021-05-12 |
Luke Kenneth Casso... | move dcache unit test to separate test_dcache.py |
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2021-05-12 |
Luke Kenneth Casso... | experimentation with MMU-enabled LoadStore1 through... |
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2021-05-12 |
Luke Kenneth Casso... | add debug info, update comments, disable dcache in... |
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2021-05-12 |
Luke Kenneth Casso... | start doing virtual memory queries via PortInterface... |
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2021-05-12 |
Luke Kenneth Casso... | whoops missing default zero (no idea how) |
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2021-05-12 |
Luke Kenneth Casso... | addcomments for MMU PortInterface test (how it, um... |
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2021-05-12 |
Luke Kenneth Casso... | bit of a hack to get test_mmu_dcache_pi.py operational. |
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2021-05-12 |
Luke Kenneth Casso... | whitespace |
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2021-05-12 |
Luke Kenneth Casso... | no need for sel0 |
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2021-05-11 |
Luke Kenneth Casso... | pass through MSR.PR through PortInterface, into LoadStore1 |
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2021-05-11 |
Luke Kenneth Casso... | connect MSR.PR to PortInterface in LDSTCompUnit |
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2021-05-11 |
Luke Kenneth Casso... | add msr_pr bit in PortInterface |
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2021-05-11 |
Luke Kenneth Casso... | add MSR to LD/ST Input Record |
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2021-05-11 |
Luke Kenneth Casso... | comment tidyup |
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2021-05-11 |
Luke Kenneth Casso... | must also pass through instruction fault exception... |
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2021-05-11 |
Luke Kenneth Casso... | whoops names changed in MMU FSM |
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2021-05-11 |
Luke Kenneth Casso... | tidyup comments and remove LoadStore COMPLETE state |
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2021-05-11 |
Luke Kenneth Casso... | cleanup on exception setting |
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2021-05-11 |
Luke Kenneth Casso... | rename LoadStore1 data structures back to microwatt... |
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2021-05-10 |
Luke Kenneth Casso... | add block for MMU activation to LoadStore1 |
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2021-05-10 |
Luke Kenneth Casso... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP... |
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2021-05-10 |
Luke Kenneth Casso... | whoops, indentation issue on m.If/m.Else in dcache.py |
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2021-05-10 |
Tobias Platen | style-wise: use ~self.instr_fault not self.instr_fault==0 |
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2021-05-10 |
Tobias Platen | LoadStore1: add rules for MMU_LOOKUP |
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2021-05-10 |
Luke Kenneth Casso... | add links to set associative image, and bugreport |
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2021-05-09 |
Luke Kenneth Casso... | add comments on translation of MMU_LOOKUP |
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2021-05-09 |
Luke Kenneth Casso... | install MMU_LOOKUP vhdl to be translated to nmigen |
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2021-05-09 |
Luke Kenneth Casso... | move (unused) ACK_WAIT code into FSM |
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2021-05-09 |
Luke Kenneth Casso... | add comments in LoadStore1 |
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2021-05-09 |
Luke Kenneth Casso... | remove invalid setting of d_in.valid from self.mmureq |
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2021-05-09 |
Luke Kenneth Casso... | no SECOND_REQ |
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2021-05-09 |
Luke Kenneth Casso... | remove SECOND_REQ |
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2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py drive output d_in.valid |
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2021-05-09 |
Tobias Platen | move skeleton to elaborate |
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2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: add skeleton for fsm |
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2021-05-09 |
Luke Kenneth Casso... | add comment about LD/ST exception needs copying into... |
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2021-05-09 |
Luke Kenneth Casso... | run LD/ST Exception test case for MMU |
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2021-05-09 |
Luke Kenneth Casso... | add MMU bugtracker link |
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2021-05-09 |
Luke Kenneth Casso... | git submodule update |
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2021-05-09 |
Luke Kenneth Casso... | update code-comments |
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2021-05-09 |
Luke Kenneth Casso... | add in alignment exception capture/reporting in LoadStore1 |
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2021-05-09 |
Luke Kenneth Casso... | preference is to create a temp variable for comb and... |
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2021-05-09 |
Luke Kenneth Casso... | add misalign flag to PortInterfaceBase |
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2021-05-08 |
Luke Kenneth Casso... | LoadStore1 tidyup |
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2021-05-08 |
Luke Kenneth Casso... | transferring more over to LoadStore FSM |
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2021-05-08 |
Luke Kenneth Casso... | start putting state info into LoadStore1, slowly puttin... |
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2021-05-08 |
Luke Kenneth Casso... | add LoadStore State enum |
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2021-05-08 |
Luke Kenneth Casso... | add bugreport link to mmu |
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2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
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2021-05-07 |
Luke Kenneth Casso... | start setting DSISR bits but commented out |
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