Add new traces to the GTKWave document
[soc.git] / src /
2021-07-10 Cesar StraussAdd new traces to the GTKWave document
2021-07-10 Cesar StraussAdd operand producers to the parallel LDST Compunit...
2021-07-10 Cesar StraussDetect unexpected operand fetches and produced results
2021-07-07 Cesar StraussStart of a GTKWave document for the LDST CompUnit paral...
2021-07-04 Cesar StraussBeginning of a class to make a parallel test case for...
2021-06-30 Tobias Platencut down on time by uncommenting data not needed, addin...
2021-06-28 Tobias Platenupdate ldst test case by adding precise timing
2021-06-24 Luke Kenneth Casso... propagate new use_svp64_ldst_dec mode through TestCore...
2021-06-24 Luke Kenneth Casso... add an explicit PowerDecoder.is_svp64_mode flag to...
2021-06-20 Tobias Platendcache: add debug output
2021-06-20 Tobias Platenupdate test_ldst_pi.py
2021-06-18 Tobias Platenuncomment test_dcache_random
2021-06-18 Tobias Platensrc/soc/fu/ldst/loadstore.py: keep data for the whole...
2021-06-14 Tobias Platenupdate testcase for ldst
2021-06-10 Luke Kenneth Casso... whoops Popcount datalen too big (wasted bits). reduce
2021-06-09 Luke Kenneth Casso... git submodule update
2021-06-09 Luke Kenneth Casso... disconnect pll clock, connected in peripheral interconnect
2021-06-09 Luke Kenneth Casso... add in/out of ref_clk and pllclk_clk when PLL enabled
2021-06-06 Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-03 Luke Kenneth Casso... comment out domains that have already been created
2021-06-03 Luke Kenneth Casso... no, do not assign clock to clock!
2021-06-03 Luke Kenneth Casso... rename ref to ref_v in PLL due to ref being a verilog...
2021-06-03 Luke Kenneth Casso... sort out PLL domains but bypass PLL due to lack of...
2021-06-03 Luke Kenneth Casso... use DomainRenamer on all sub-components of TestIssuer
2021-06-03 Luke Kenneth Casso... make core_rst a member of TestIssuerInternal
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-27 Luke Kenneth Casso... adjust PLL connections looking for coriolis2 issue
2021-05-27 Luke Kenneth Casso... corrections on spblock ack
2021-05-27 Luke Kenneth Casso... classic wishbone mode: must not do ack if already acked
2021-05-26 Luke Kenneth Casso... arse. PLL test_issuer clk_sel_i accidentally only 1...
2021-05-26 Luke Kenneth Casso... remove err feature from sram4k wb
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway)
2021-05-26 Luke Kenneth Casso... rename PLL signals
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop
2021-05-25 Tobias Platenwait_ldok: add debug output count
2021-05-24 Luke Kenneth Casso... whoops sort out name of SPBlock RAM
2021-05-24 Luke Kenneth Casso... change name of submodule to real_pll
2021-05-24 Luke Kenneth Casso... match up PLL names
2021-05-22 Cesar StraussMove the reset code outside of the sub-test
2021-05-22 Luke Kenneth Casso... update submodule
2021-05-22 Luke Kenneth Casso... update PLL to use Instance
2021-05-15 Tobias Platentest_ldst_pi.py: add dcache regression and random test...
2021-05-14 Luke Kenneth Casso... add radix MMU "miss" test
2021-05-14 Luke Kenneth Casso... clear out request data on return to idle
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-14 Luke Kenneth Casso... remove minerva units previously missed in cleanout
2021-05-14 Luke Kenneth Casso... add misaligned load through MMU (which is incorrectly...
2021-05-13 Luke Kenneth Casso... minor rework of wb_get, make generic
2021-05-13 Luke Kenneth Casso... added STORE test in test_ldst_pi.py, and it worked...
2021-05-13 Luke Kenneth Casso... update comments in issuer.py regarding a 4th FSM
2021-05-13 Luke Kenneth Casso... yet more debug log stuff for DCache, this time on Cache...
2021-05-13 Luke Kenneth Casso... fix wb_get error where data was being corrupted
2021-05-13 Luke Kenneth Casso... add read at different locations in test_ldst_pi.py
2021-05-13 Luke Kenneth Casso... add some data for MMU to actually look up
2021-05-13 Luke Kenneth Casso... ha, hilarious: swapped TLBUpdate output sizes db_out...
2021-05-13 Luke Kenneth Casso... whoops TLBIE must *clear* the valid bit not set it...
2021-05-13 Luke Kenneth Casso... more debug Display in dcache.py
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache...
2021-05-12 Luke Kenneth Casso... add dcache tlb / pte test
2021-05-12 Luke Kenneth Casso... set m_out.load from ldst_r(egister) in LoadStore1
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-12 Luke Kenneth Casso... whoops missing default zero (no idea how)
2021-05-12 Luke Kenneth Casso... addcomments for MMU PortInterface test (how it, um...
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational.
2021-05-12 Luke Kenneth Casso... whitespace
2021-05-12 Luke Kenneth Casso... no need for sel0
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... connect MSR.PR to PortInterface in LDSTCompUnit
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface
2021-05-11 Luke Kenneth Casso... add MSR to LD/ST Input Record
2021-05-11 Luke Kenneth Casso... comment tidyup
2021-05-11 Luke Kenneth Casso... must also pass through instruction fault exception...
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM
2021-05-11 Luke Kenneth Casso... tidyup comments and remove LoadStore COMPLETE state
2021-05-11 Luke Kenneth Casso... cleanup on exception setting
2021-05-11 Luke Kenneth Casso... rename LoadStore1 data structures back to microwatt...
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1
2021-05-10 Luke Kenneth Casso... move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport
2021-05-09 Luke Kenneth Casso... add comments on translation of MMU_LOOKUP
2021-05-09 Luke Kenneth Casso... install MMU_LOOKUP vhdl to be translated to nmigen
2021-05-09 Luke Kenneth Casso... move (unused) ACK_WAIT code into FSM
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1
2021-05-09 Luke Kenneth Casso... remove invalid setting of d_in.valid from self.mmureq
2021-05-09 Luke Kenneth Casso... no SECOND_REQ
2021-05-09 Luke Kenneth Casso... remove SECOND_REQ
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid
2021-05-09 Tobias Platenmove skeleton to elaborate
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm
2021-05-09 Luke Kenneth Casso... add comment about LD/ST exception needs copying into...
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link
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