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Add operand producers to the parallel LDST Compunit test case
2021-07-10
Cesar Strauss
Add operand producers to the parallel LDST Compunit...
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2021-07-10
Cesar Strauss
Detect unexpected operand fetches and produced results
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2021-07-07
Cesar Strauss
Start of a GTKWave document for the LDST CompUnit parallel...
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2021-07-04
Cesar Strauss
Beginning of a class to make a parallel test case for...
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2021-06-06
Cesar Strauss
Start a new self-contained test suite for LDSTCompUnit
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2021-05-22
Cesar Strauss
Remove redundant build step
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2021-05-22
Cesar Strauss
Include missing step in automated build
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2021-05-22
Cesar Strauss
Move the reset code outside of the sub-test
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2021-05-01
Cesar Strauss
Add GTKWave documents to each DCache unit test
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2021-04-25
Cesar Strauss
Shift-out skipped mask bits for both crpred and intpred
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2021-04-22
Cesar Strauss
Implement CR predication
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2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
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2021-04-21
Cesar Strauss
Add CR predication test case for TestIssuer
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2021-04-21
Cesar Strauss
Fix comment in CR predication test case
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2021-04-21
Cesar Strauss
Fix sense of "invert" signal
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2021-04-17
Cesar Strauss
Implement 1<<r3 directly by a shift
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2021-04-10
Cesar Strauss
Implement 1<<r3 predicate mode
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2021-04-10
Cesar Strauss
Add 1<<r3 test cases to TestIssuer
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2021-04-10
Cesar Strauss
Add test cases for 1<<r3 predication
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2021-04-06
Cesar Strauss
Make the VL loop reentrant in HDL
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2021-04-06
Cesar Strauss
Add a HDL test case, where we start at the middle of...
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2021-04-06
Cesar Strauss
Start the test case from a point where the predicate...
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2021-04-04
Cesar Strauss
Add test case for reentrant VL loop
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2021-04-03
Cesar Strauss
Reminder for a possible hardware optimization
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2021-04-03
Cesar Strauss
Be more precise when using a one-bit constant
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2021-04-03
Cesar Strauss
Fix typo
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2021-04-03
Cesar Strauss
Add test case with all mask bits equal to zero
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2021-04-03
Cesar Strauss
Add a test case for integer single predication
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2021-04-03
Cesar Strauss
Disallow unknown encmodes in SVP64 Assembly
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2021-04-03
Cesar Strauss
Enable remaining disabled test cases
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2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
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2021-04-03
Cesar Strauss
Signal the simulator when completing a VL loop
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2021-04-03
Cesar Strauss
Fix typo
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2021-04-03
Cesar Strauss
Add twin predication test
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2021-04-02
Cesar Strauss
End VL loop as soon as either src/dst step reaches VL
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2021-04-02
Cesar Strauss
Fix typo
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2021-04-02
Cesar Strauss
Add VEXPAND test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Add VCOMPRESS test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Put sanity check inside the existing '2Pred' case,...
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2021-04-02
Cesar Strauss
Enforce explicit src/dest masks on CR twin-predication
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2021-04-02
Cesar Strauss
Disallow mixing of sm=xx and/or dm=xx with m=xx on...
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2021-04-02
Cesar Strauss
Disallow dm=xx on single predication
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2021-04-02
Cesar Strauss
Fix typo
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2021-04-02
Cesar Strauss
Really enforce sm=xx not being allowed on single-pred
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2021-04-02
Cesar Strauss
Keep mask mode flags separate
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2021-03-30
Cesar Strauss
Enable VCOMPRESS test case
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2021-03-30
Cesar Strauss
Add new twin predication case
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2021-03-30
Cesar Strauss
Adjust twin predication cases for the new syntax
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2021-03-30
Cesar Strauss
Skip leading zero bits on predicate masks
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2021-03-30
Cesar Strauss
Memory port seems to have been renamed
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2021-03-28
Cesar Strauss
Move DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE
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2021-03-28
Cesar Strauss
Move instruction decoding to after predication
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2021-03-28
Cesar Strauss
Prepare to advance src/dst step after getting the predicate...
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2021-03-22
Cesar Strauss
Add test cases for integer VCOMPRESS and VEXPAND
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2021-03-22
Cesar Strauss
Skip fetching integer predicate mask when register...
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2021-03-22
Cesar Strauss
Add traces for the new FSM and integer predicate decoding
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2021-03-22
Cesar Strauss
Decode and fetch integer predicate registers
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2021-03-21
Cesar Strauss
Fix typo
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2021-03-21
Cesar Strauss
Add unique name to decoded predication signals
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2021-03-21
Cesar Strauss
Revert removal of *.value from Enums
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2021-03-21
Cesar Strauss
Fix syntax
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2021-03-21
Cesar Strauss
Start work on the predicate fetch FSM
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2021-03-21
Cesar Strauss
Add predication test case, initially disabled
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2021-03-16
Cesar Strauss
Use symbolic values for subfields and bits
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2021-03-16
Cesar Strauss
Add subfield and bit definitions for the SVP64 RM mode...
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2021-03-16
Cesar Strauss
Define and initialise the mode variable, to be used...
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2021-03-16
Cesar Strauss
Rename class so it does not clash with the enum
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2021-03-15
Cesar Strauss
Fix import
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2021-03-14
Cesar Strauss
Activate the VL==0 loop with any SVP64 prefix whatsoever
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2021-03-11
Cesar Strauss
Bring a few test cases from test_caller_64.py
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2021-03-11
Cesar Strauss
Test case for two successive SV instructions
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2021-03-09
Cesar Strauss
Enable VL==0 vector instruction skip test case
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2021-03-09
Cesar Strauss
Add some extra debug traces to the GTKWave document
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2021-03-09
Cesar Strauss
Create a new signal for the Simulator to wait on
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2021-03-08
Cesar Strauss
Remove the unused internal insn_done signal
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2021-03-08
Cesar Strauss
Fix argument order to match function declaration
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2021-03-07
Cesar Strauss
Fix missing NIA update on ISACaller
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2021-03-07
Cesar Strauss
Merge WAIT_RESET into INSN_FETCH on the Issue FSM
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2021-03-07
Cesar Strauss
Implement the VL==0 loop
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2021-03-06
Cesar Strauss
Allow updating the PC and SVSTATE registers while stopped
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2021-03-06
Cesar Strauss
Enable the Simple-V loop test case
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2021-03-06
Cesar Strauss
Begin to implement the Simple-V loop
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2021-03-06
Cesar Strauss
Do not reset pc_changed and sv_changed at instruction end
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2021-03-06
Cesar Strauss
Make the raw opcode input port of the decoder stay...
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2021-03-05
Cesar Strauss
Move writing of the PC state register to the issue FSM
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2021-03-05
Cesar Strauss
Move the wait on "core stop" out of fetch, and into...
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2021-02-27
Cesar Strauss
Add traces for the new FSM
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2021-02-26
Cesar Strauss
Add a vector case with VL == 0
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2021-02-26
Cesar Strauss
Implement a decode/issue FSM between fetch and execute
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2021-02-22
Cesar Strauss
Fix typo when calculating PowerDecoder2.no_out_vec
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2021-02-21
Cesar Strauss
The field selection function was moved to nmutil.util
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2021-02-21
Cesar Strauss
Hide the register augmentation traces by default
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2021-02-21
Cesar Strauss
The new version of "sel" is smart enough to find a...
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2021-02-21
Cesar Strauss
Use the new selection field function from nmutil
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2021-02-21
Cesar Strauss
Use symbolic values as field sizes
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2021-02-21
Cesar Strauss
Replace all hardcoded shifts into RM by usage of SVP64RMFields
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2021-02-20
Cesar Strauss
Actually forward the field width to field_slice()
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2021-02-20
Cesar Strauss
Assemble the SV64 prefix from its subfields using SVP64Prefi...
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2021-02-20
Cesar Strauss
Fix more MSB0 issues in comments
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2021-02-20
Cesar Strauss
Replace more hardcoded constants with symbolic field...
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