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Handle newer nMigen adding a "bench" hierarchy root in VCD files
2023-01-01
Cesar Strauss
Handle newer nMigen adding a "bench" hierarchy root...
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2022-11-15
Cesar Strauss
Keep the valid signal from the formal engine ALU stable...
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2022-10-28
Cesar Strauss
Check that exactly one ALU write is made, per instruction
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2022-10-28
Cesar Strauss
Check cover and bmc in separate sub-tests
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2022-10-26
Cesar Strauss
Reset req_l latch on system reset
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2022-10-26
Cesar Strauss
Reset src_l latch on issue_i
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2022-10-16
Cesar Strauss
Move test to expose bug in MultiCompUnit
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2022-10-12
Cesar Strauss
Check invariant for instruction operands
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2022-10-12
Cesar Strauss
If the ALU is idle, do not assert valid
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2022-10-09
Cesar Strauss
Count zero_a and imm_data.ok as masked read transactions
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2022-10-09
Cesar Strauss
Don't issue while busy
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2022-10-08
Cesar Strauss
Add count of masked reads
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2022-10-08
Cesar Strauss
Add ALU read transaction counter
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2022-10-08
Cesar Strauss
Add ALU write transaction counter
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2022-10-08
Cesar Strauss
Add write transaction counter
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2022-10-05
Cesar Strauss
Fix duplicate line (copy & paste error)
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2022-10-01
Cesar Strauss
Add counter for operand reads
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2022-10-01
Cesar Strauss
Avoid toggling go_i when rel_o is low
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2022-10-01
Cesar Strauss
Leave shadow / die proof for last
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2022-10-01
Cesar Strauss
Start of formal proof of MultiCompUnit
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2022-04-30
Cesar Strauss
Implement transparent read port option on the XOR wrapper...
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2022-04-28
Cesar Strauss
Test simultaneous transparent reads and partial writes
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2022-04-17
Cesar Strauss
Implement a 1W/1R register file, XOR style
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2022-04-17
Cesar Strauss
Formal proof of pseudo 1W/2R SRAM
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2022-04-17
Cesar Strauss
Add transparent option for the full read port
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2022-04-17
Cesar Strauss
Implement a pseudo 1W/2R memory
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2022-04-16
Cesar Strauss
Check non-transparent 1W/1R SRAM wrapper
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2022-04-16
Cesar Strauss
Enable read port for non-transparent memories
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2022-04-16
Cesar Strauss
Add port declarations to the SRAM wrappers
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2022-04-16
Cesar Strauss
Change write lane signal from one-hot to binary
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2022-04-16
Cesar Strauss
Synchronize LVT state, completing the induction proof
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2022-04-16
Cesar Strauss
Sync proof state with downstream memories
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2022-04-15
Cesar Strauss
Complete moving the induction support into the DUT
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2022-04-15
Cesar Strauss
Fix incorrect signal widths
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2022-04-15
Cesar Strauss
Move part of formal proof to the implementation
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2022-04-10
Cesar Strauss
Begin a formal proof of the LVT-based 1W/1R wrapper
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2022-04-10
Cesar Strauss
Implement 1W/1R with a transparent (or not) read port.
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2022-04-10
Cesar Strauss
Implement a true 1W/1R memory from 1RW blocks
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2022-04-03
Cesar Strauss
Extend the proof to a non-transparent port
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2022-04-03
Cesar Strauss
Run formal proof on both types (even/odd) of phased...
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2022-04-03
Cesar Strauss
Complete the formal proof of the pseudo dual port SRAM
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2022-04-03
Cesar Strauss
Implement a debug port on the pseudo 1W/1R SRAM
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2022-04-03
Cesar Strauss
Formal proof of the phased write dual port memory wrapper
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2022-04-02
Cesar Strauss
Implement transparent read ports on the phased write...
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2022-04-02
Cesar Strauss
Implement and test a "phased write port" memory
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2022-03-27
Cesar Strauss
Finish the SRAM formal proof by implementing induction
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2022-03-26
Cesar Strauss
Add formal verification of the single port memory block
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2022-03-13
Cesar Strauss
Simulate some read/write/modify operations on the SRAM...
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2022-03-13
Cesar Strauss
Add a Single R/W Port SRAM model
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2022-03-06
Cesar Strauss
Copy the startup delay from issuer.py to inorder.py
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2022-01-03
Cesar Strauss
On inorder.py, after Execute, update the PC and go...
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2021-12-28
Cesar Strauss
Add an --inorder option to test_issuer.py
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2021-12-27
Cesar Strauss
Fix indentation
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2021-12-23
Cesar Strauss
Remove extra wait on core_stop_o at end of Execute.
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2021-12-23
Cesar Strauss
Re-enable core stopped signal when stopped.
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2021-09-19
Cesar Strauss
Fix rel_o/go_i signal names
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2021-09-19
Cesar Strauss
Replace "Display" with "print" on simulation process
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2021-09-19
Cesar Strauss
Fix import
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2021-09-18
Cesar Strauss
Use a pre-compiled version of maturin
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2021-09-13
Cesar Strauss
Save Gitlab runner cache, even on a failed test
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2021-09-08
Cesar Strauss
Monitor exceptions, re-decoding the instruction in...
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2021-09-08
Cesar Strauss
Monitor the exception input to PowerDecoder2
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2021-09-08
Cesar Strauss
Remove default argument for dict.get()
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2021-09-07
Cesar Strauss
Fix typo.
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2021-08-17
Cesar Strauss
Enable LD/ST exception test case
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2021-08-17
Cesar Strauss
Clear operand latch on a terminating condition
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2021-08-17
Cesar Strauss
Add exc_o.happened to the conditions for terminating...
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2021-08-17
Cesar Strauss
Fix activation of cancel signal
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2021-08-16
Cesar Strauss
Adjust PortInterface traces according to MMU option
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2021-07-10
Cesar Strauss
Show some usage of PortInterface in action
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2021-07-10
Cesar Strauss
Add new traces to the GTKWave document
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2021-07-10
Cesar Strauss
Add operand producers to the parallel LDST Compunit...
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2021-07-10
Cesar Strauss
Detect unexpected operand fetches and produced results
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2021-07-07
Cesar Strauss
Start of a GTKWave document for the LDST CompUnit parallel...
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2021-07-04
Cesar Strauss
Beginning of a class to make a parallel test case for...
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2021-06-06
Cesar Strauss
Start a new self-contained test suite for LDSTCompUnit
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2021-05-22
Cesar Strauss
Remove redundant build step
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2021-05-22
Cesar Strauss
Include missing step in automated build
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2021-05-22
Cesar Strauss
Move the reset code outside of the sub-test
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2021-05-01
Cesar Strauss
Add GTKWave documents to each DCache unit test
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2021-04-25
Cesar Strauss
Shift-out skipped mask bits for both crpred and intpred
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2021-04-22
Cesar Strauss
Implement CR predication
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2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
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2021-04-21
Cesar Strauss
Add CR predication test case for TestIssuer
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2021-04-21
Cesar Strauss
Fix comment in CR predication test case
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2021-04-21
Cesar Strauss
Fix sense of "invert" signal
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2021-04-17
Cesar Strauss
Implement 1<<r3 directly by a shift
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2021-04-10
Cesar Strauss
Implement 1<<r3 predicate mode
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2021-04-10
Cesar Strauss
Add 1<<r3 test cases to TestIssuer
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2021-04-10
Cesar Strauss
Add test cases for 1<<r3 predication
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2021-04-06
Cesar Strauss
Make the VL loop reentrant in HDL
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2021-04-06
Cesar Strauss
Add a HDL test case, where we start at the middle of...
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2021-04-06
Cesar Strauss
Start the test case from a point where the predicate...
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2021-04-04
Cesar Strauss
Add test case for reentrant VL loop
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2021-04-03
Cesar Strauss
Reminder for a possible hardware optimization
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2021-04-03
Cesar Strauss
Be more precise when using a one-bit constant
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2021-04-03
Cesar Strauss
Fix typo
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2021-04-03
Cesar Strauss
Add test case with all mask bits equal to zero
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2021-04-03
Cesar Strauss
Add a test case for integer single predication
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2021-04-03
Cesar Strauss
Disallow unknown encmodes in SVP64 Assembly
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