2020-09-08 |
Luke Kenneth... | give Decode2Execute1Type in core a name |
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2020-09-08 |
Luke Kenneth... | argh, somehow EINT check got moved out of if/elif block |
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2020-09-08 |
Luke Kenneth... | capture trap / irq conditions in flags for debug purposes |
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2020-09-08 |
Luke Kenneth... | pass in CoreState to PowerDecoder rather than eq a... |
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2020-09-08 |
Luke Kenneth... | whoops trap address being set in wrong Decode2ExecuteTy... |
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2020-09-08 |
Luke Kenneth... | add cxxsim option |
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2020-09-07 |
Luke Kenneth... | use PowerDecoderSubsets for FUs, except for TRAP which... |
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2020-09-07 |
Luke Kenneth... | add per-FU PowerDecoders. should now be subsettable |
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2020-09-07 |
Luke Kenneth... | create eq_from function based on eq_from_execute1 |
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2020-09-07 |
Luke Kenneth... | debug print statement in eq_from_execute |
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2020-09-07 |
Luke Kenneth... | oe_ok renamed to oe, needed in regspec_decode_read |
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2020-09-07 |
Luke Kenneth... | add insn and fn_unit to CompLDSTOpSubset |
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2020-09-07 |
Luke Kenneth... | add pspec and opsubsetkls to CompUnits |
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2020-09-07 |
Cole Poirier | icache.py commit translation progress, about one third... |
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2020-09-07 |
Luke Kenneth... | make immediate decoding optional on-demand |
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2020-09-07 |
Luke Kenneth... | whoops spelling mistake outOut_carry not outPut_carry |
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2020-09-07 |
Luke Kenneth... | convert mul test to use Power Decode subset |
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2020-09-07 |
Luke Kenneth... | convert shift_rot to subset decoder |
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2020-09-07 |
Luke Kenneth... | convert branch test to PowerDecodeSubset form |
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2020-09-07 |
Luke Kenneth... | convert CR to PowerDecodeSubset format |
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2020-09-07 |
Luke Kenneth... | bit of a big reorg of data structures |
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2020-09-07 |
Luke Kenneth... | split out PowerDecode2 into PowerDecodeSubset |
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2020-09-07 |
Luke Kenneth... | large stack of moving stuff around in dcache |
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2020-09-07 |
Luke Kenneth... | adjust indentation of dcache_slow |
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2020-09-07 |
Luke Kenneth... | more dcache translation |
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2020-09-07 |
Luke Kenneth... | add start on cache_ram.vhdl to nmigen conversion |
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2020-09-07 |
Luke Kenneth... | more dcache translation |
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2020-09-07 |
Luke Kenneth... | allow Decode2ToExecute1Type to take an opkls argument |
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2020-09-07 |
Luke Kenneth... | whoops truncated the mb and me fields |
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2020-09-07 |
Luke Kenneth... | minor reorg on PowerDecoder |
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2020-09-06 |
Luke Kenneth... | comment, nothing unusual when Trap Type is DEC |
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2020-09-06 |
Luke Kenneth... | decoder immediate b split out to DecodeBImm |
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2020-09-06 |
Luke Kenneth... | decoder immediate a split out to DecodeAImm |
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2020-09-06 |
Luke Kenneth... | add row subset selector for PowerDecode. |
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2020-09-06 |
Luke Kenneth... | add row_subset (doesnt do anything yet) |
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2020-09-06 |
Luke Kenneth... | pass col_subset throughout PowerDecoder |
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2020-09-06 |
Luke Kenneth... | reorganise PowerOp to be dynamic |
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2020-09-06 |
Luke Kenneth... | reorg of PowerOp to be able to dynamically subset it |
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2020-09-06 |
Luke Kenneth... | grr, autopep8 messing up |
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2020-09-06 |
Luke Kenneth... | copy dec SPR into decoder cur_state |
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2020-09-06 |
Luke Kenneth... | add reset option to Register |
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2020-09-06 |
Luke Kenneth... | wark-wark, fast regs is binary-addressed |
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2020-09-06 |
Luke Kenneth... | add unit test for slow SPRs (SPRG0/1) |
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2020-09-06 |
Luke Kenneth... | minor code-munge on SPR-to-FAST mapping |
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2020-09-06 |
Luke Kenneth... | use with subTest in spr unit test |
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2020-09-06 |
Luke Kenneth... | redo generation of microwatt.v from litex |
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2020-09-06 |
Luke Kenneth... | add comments for DEC / TB |
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2020-09-06 |
Luke Kenneth... | add a DEC/TB FSM to TestIssuer |
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2020-09-06 |
Luke Kenneth... | move DEC and TB from StateRegs to FastRegs for several... |
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2020-09-06 |
Luke Kenneth... | add DEC SPR to CoreState and PowerDecoder, activate... |
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2020-09-06 |
Luke Kenneth... | add DEC and TB to State regfile |
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2020-09-06 |
Luke Kenneth... | add DEC/TB SPRs to spr pipeline |
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2020-09-05 |
Luke Kenneth... | add comments on MSR read |
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2020-09-05 |
Luke Kenneth... | move GPIO IRQ to 15 to match microwatt modifications |
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2020-09-05 |
Luke Kenneth... | hmmm XICS data being asserted on wb bus for too long |
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2020-09-05 |
Luke Kenneth... | argh missed a VHDL "&" translating to Cat |
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2020-09-05 |
Luke Kenneth... | reduce XICS address lookup by 2 bits |
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2020-09-05 |
Luke Kenneth... | MSR read in INSN_READ only occurs for 1 cycle |
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2020-09-05 |
Luke Kenneth... | sync on ICP eint |
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2020-09-05 |
Luke Kenneth... | connect XICS core irq to Decode2 eint |
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2020-09-05 |
Luke Kenneth... | whoops, combinatorial loop on pending_priority |
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2020-09-05 |
Luke Kenneth... | use stbcix in test |
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2020-09-05 |
Luke Kenneth... | XICS addresses in words: divide by 4 |
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2020-09-05 |
Luke Kenneth... | whoops, ICS in litex sim needs to be 0x1000 size region |
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2020-09-05 |
Luke Kenneth... | add lwzcix unit test |
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2020-09-05 |
Luke Kenneth... | increase wishbone address width to 29 for xics and... |
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2020-09-05 |
Luke Kenneth... | submodule update |
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2020-09-05 |
Luke Kenneth... | add simple GPIO wishbone bus to litex sim.py |
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2020-09-05 |
Luke Kenneth... | add stbcix and lwzcix to power_enum list |
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2020-09-05 |
Luke Kenneth... | add simple GPIO peripheral to verilog TestIssuer |
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2020-09-05 |
Luke Kenneth... | move wb read/write to separate util test library and... |
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2020-09-05 |
Luke Kenneth... | add simple wishbone GPIO peripheral |
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2020-09-05 |
Samuel A. Falvo II | Add unit test replicating failing proof case |
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2020-09-04 |
Luke Kenneth... | add sld test with RB=64 to see what happens |
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2020-09-04 |
Luke Kenneth... | reduce CSR data width to 8 as an experiment |
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2020-09-04 |
Luke Kenneth... | add UART reserved IRQ @ 0 |
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2020-09-04 |
Luke Kenneth... | add XICS memory regions, shrink litex CSR memmap size... |
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2020-09-04 |
Luke Kenneth... | adding XICS wb slave devices to litex sim |
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2020-09-04 |
Luke Kenneth... | bring out XICS ICS interrupt levels so that they can... |
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2020-09-04 |
Luke Kenneth... | adding option to include XICS external interrupts. |
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2020-09-04 |
Luke Kenneth... | add means to run hello_world.bin under simulation |
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2020-09-04 |
Jacob Lifshay | update to match refactored power-instruction-analyzer API |
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2020-09-03 |
Samuel A. Falvo II | Provide full name and email in copyright notice. |
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2020-09-03 |
Luke Kenneth... | do more on dcache conversion |
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2020-09-03 |
Luke Kenneth... | testing microwatt 3.bin (2.bin ok) |
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2020-09-02 |
Luke Kenneth... | when mtocrf FXM is 0, the CR has to be set to CR7 |
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2020-09-02 |
Luke Kenneth... | fix bug in cmpli (and cmplw) |
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2020-09-02 |
Luke Kenneth... | sign-extend lhax needs 16-64, separate from lwax which... |
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2020-09-02 |
Luke Kenneth... | add bc ctr regression test when CTR=0 and CTR=1 |
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2020-09-02 |
Luke Kenneth... | update submodule |
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2020-09-02 |
Luke Kenneth... | bug in carry32 handling in OP_CMP |
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2020-09-02 |
Luke Kenneth... | add cmpl regression test (one binary, one assembly) |
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2020-09-02 |
Luke Kenneth... | add cmpl microwatt 1.bin test, cmpl |
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2020-09-02 |
Luke Kenneth... | series of extensive modifications to fix long-standing... |
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2020-08-31 |
Luke Kenneth... | add XER to fastregs and "construct" it in mfspr/mtspr |
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2020-08-30 |
Luke Kenneth... | redo OP_CMP based on microwatt. L=1 had been ignored |
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2020-08-30 |
Luke Kenneth... | reversal of FXM mask for one-hot selection in OP_MTCR... |
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2020-08-30 |
Luke Kenneth... | working on dcache.py |
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2020-08-30 |
Luke Kenneth... | tidyup on mul proof |
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2020-08-30 |
Luke Kenneth... | set mul post_stage o.ok only when needed, and fix xer_s... |
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