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soc.git
2021-04-15
Luke Kenneth...
add icachemmu option to ISACaller
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2021-04-14
Luke Kenneth...
submodule update
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2021-04-14
Luke Kenneth...
whitespace
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2021-04-14
Luke Kenneth...
submodule update
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2021-04-14
Tobias Platen
update test_caller_radix.py
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2021-04-14
Tobias Platen
radixmmu: handle badtree
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2021-04-14
Tobias Platen
update test case for radix mmu
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2021-04-14
Tobias Platen
radixmmu: error handling
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2021-04-13
Tobias Platen
more fixes for radixmmu.py
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2021-04-13
Tobias Platen
fix AttributeError in radixmmu testcase
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2021-04-12
Tobias Platen
radixmmu.py: cleanup
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2021-04-11
Tobias Platen
fix bug in radixmmu.py
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2021-04-11
Tobias Platen
radixmmu: more work on segment check
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2021-04-10
Cesar Strauss
Implement 1<<r3 predicate mode
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2021-04-10
Cesar Strauss
Add 1<<r3 test cases to TestIssuer
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2021-04-10
Cesar Strauss
Add test cases for 1<<r3 predication
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2021-04-09
Luke Kenneth...
add blinken lights assembly (not used yet)
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2021-04-09
Luke Kenneth...
test firmware upload program needed to branch back...
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2021-04-08
Luke Kenneth...
sort out pc reset when DMI interface requests reset
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2021-04-08
Luke Kenneth...
submodule update
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2021-04-08
Luke Kenneth...
argh, wb jtag stall probably is not working
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2021-04-08
Luke Kenneth...
upload over 32-bit JTAG Wishbone
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2021-04-08
Luke Kenneth...
shrink JTAG master bus to 32-bit (match with litex)
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2021-04-07
Luke Kenneth...
submodule update
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2021-04-07
Tobias Platen
WIP: calculate address of first page table entry
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2021-04-07
Tobias Platen
radixmmu: fix segment_check function and its caller
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2021-04-06
Luke Kenneth...
4k SRAM Instance needs write-enable @ 8-bit width
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2021-04-06
Luke Kenneth...
8-bit granularity on JTAG wishbone
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2021-04-06
Luke Kenneth...
remove unneeded code
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2021-04-06
Staf Verhaegen
soc-cocotb-sim submodule update
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2021-04-06
Tobias Platen
add mmu_states.dia
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2021-04-06
Luke Kenneth...
git submodule update
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2021-04-06
Cesar Strauss
Make the VL loop reentrant in HDL
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2021-04-06
Cesar Strauss
Add a HDL test case, where we start at the middle of...
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2021-04-06
Cesar Strauss
Start the test case from a point where the predicate...
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2021-04-05
Luke Kenneth...
litex submodule update
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2021-04-05
Luke Kenneth...
submodule update
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2021-04-04
Staf Verhaegen
soc-cocotb-sim submodule update
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2021-04-04
Cesar Strauss
Add test case for reentrant VL loop
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2021-04-03
Cesar Strauss
Reminder for a possible hardware optimization
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2021-04-03
Cesar Strauss
Be more precise when using a one-bit constant
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2021-04-03
Cesar Strauss
Fix typo
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2021-04-03
Cesar Strauss
Add test case with all mask bits equal to zero
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2021-04-03
Cesar Strauss
Add a test case for integer single predication
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2021-04-03
Cesar Strauss
Disallow unknown encmodes in SVP64 Assembly
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2021-04-03
Cesar Strauss
Enable remaining disabled test cases
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2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
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2021-04-03
Cesar Strauss
Signal the simulator when completing a VL loop
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2021-04-03
Cesar Strauss
Fix typo
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2021-04-03
Cesar Strauss
Add twin predication test
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2021-04-02
Cesar Strauss
End VL loop as soon as either src/dst step reaches VL
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2021-04-02
Cesar Strauss
Fix typo
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2021-04-02
Cesar Strauss
Add VEXPAND test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Add VCOMPRESS test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Put sanity check inside the existing '2Pred' case,...
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2021-04-02
Cesar Strauss
Enforce explicit src/dest masks on CR twin-predication
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2021-04-02
Cesar Strauss
Disallow mixing of sm=xx and/or dm=xx with m=xx on...
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2021-04-02
Cesar Strauss
Disallow dm=xx on single predication
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2021-04-02
Cesar Strauss
Fix typo
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2021-04-02
Cesar Strauss
Really enforce sm=xx not being allowed on single-pred
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2021-04-02
Cesar Strauss
Keep mask mode flags separate
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2021-04-01
Luke Kenneth...
git submodule update
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2021-04-01
Luke Kenneth...
TWI enabled in JTAG boundary scan
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2021-04-01
Luke Kenneth...
git submodule update
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2021-04-01
Luke Kenneth...
reduce subset of functions to be created in JTAG bounda...
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2021-04-01
Luke Kenneth...
use OrderedDict to restore exact order from JSON file
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2021-04-01
Luke Kenneth...
add soc-cocotb-sim submodule
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2021-04-01
Luke Kenneth...
submodule update
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2021-04-01
Staf Verhaegen
libresoc-litex submodule update
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2021-04-01
Luke Kenneth...
bug in iverilog, segfaults due to empty case statement
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2021-04-01
Luke Kenneth...
add no pll ls180 build
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2021-04-01
Staf Verhaegen
libresoc-litex submodule update
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2021-03-31
Tobias Platen
_new_lookup: remove unused argument mbits
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2021-03-31
Tobias Platen
radixmmu: read prtable entry
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2021-03-31
Tobias Platen
radixmmu.py: remove redunant code
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2021-03-31
Luke Kenneth...
submodule update
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2021-03-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-03-30
Tobias Platen
more work on _prtable_lookup and testcase
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2021-03-30
Luke Kenneth...
add comments
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2021-03-30
Luke Kenneth...
use PRTBL SPR in RADIXMMU
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2021-03-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-03-30
Tobias Platen
comment about microwatt implementation details
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2021-03-30
Luke Kenneth...
submodule update
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2021-03-30
Luke Kenneth...
add comments, correct load addresses
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2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
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2021-03-30
Alain D D Williams
Allow comments
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2021-03-30
Tobias Platen
add function _prtable_lookup and unit test
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2021-03-30
Luke Kenneth...
submodule update
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2021-03-30
Luke Kenneth...
might have RADIXMMU at least semi-working... maybe
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2021-03-30
Luke Kenneth...
use assertEqual in RADIXMMU unit test
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2021-03-30
Luke Kenneth...
skip 1-pred check if m= used in SVP64Asm
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2021-03-30
Cesar Strauss
Enable VCOMPRESS test case
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2021-03-30
Luke Kenneth...
submodule update
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2021-03-30
Cesar Strauss
Add new twin predication case
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2021-03-30
Cesar Strauss
Adjust twin predication cases for the new syntax
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2021-03-30
Cesar Strauss
Skip leading zero bits on predicate masks
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2021-03-30
Luke Kenneth...
use port name for INT regfile to match up with test_run...
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2021-03-30
Luke Kenneth...
corrections to Makefile for building / not-building...
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2021-03-30
Cesar Strauss
Memory port seems to have been renamed
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2021-03-30
Luke Kenneth...
bit of munging of Makefile, new targets
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