format code
authorJacob Lifshay <programmerjake@gmail.com>
Wed, 22 Jul 2020 22:18:03 +0000 (15:18 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Wed, 22 Jul 2020 22:18:03 +0000 (15:18 -0700)
commit575802fa56d7175ebbdc16bb5c493b556dab9c74
tree4b415a7e158fed33f8c532da81d8d605505ae8f7
parent3cd49ba3ba82391f6586495fc0e429828bb7c149
format code
61 files changed:
src/soc/bus/test/test_minerva.py
src/soc/config/test/test_fetch.py
src/soc/config/test/test_loadstore.py
src/soc/decoder/helpers.py
src/soc/decoder/isa/caller.py
src/soc/decoder/power_decoder.py
src/soc/decoder/power_decoder2.py
src/soc/decoder/power_enums.py
src/soc/decoder/power_fields.py
src/soc/decoder/power_pseudo.py
src/soc/decoder/pseudo/lexer.py
src/soc/decoder/pseudo/pagereader.py
src/soc/decoder/pseudo/parser.py
src/soc/decoder/pseudo/pywriter.py
src/soc/decoder/selectable_int.py
src/soc/decoder/test/test_power_decoder.py
src/soc/experiment/alu_hier.py
src/soc/experiment/compalu_multi.py
src/soc/experiment/compldst_multi.py
src/soc/experiment/imem.py
src/soc/experiment/pi2ls.py
src/soc/experiment/pimem.py
src/soc/experiment/score6600.py
src/soc/experiment/score6600_multi.py
src/soc/experiment/sim.py
src/soc/experiment/test/test_compalu_multi.py
src/soc/experiment/testmem.py
src/soc/fu/alu/test/test_pipe_caller.py
src/soc/fu/branch/test/test_pipe_caller.py
src/soc/fu/compunits/test/test_alu_compunit.py
src/soc/fu/compunits/test/test_branch_compunit.py
src/soc/fu/compunits/test/test_compunit.py
src/soc/fu/compunits/test/test_cr_compunit.py
src/soc/fu/compunits/test/test_ldst_compunit.py
src/soc/fu/compunits/test/test_logical_compunit.py
src/soc/fu/compunits/test/test_shiftrot_compunit.py
src/soc/fu/compunits/test/test_spr_compunit.py
src/soc/fu/compunits/test/test_trap_compunit.py
src/soc/fu/cr/test/test_pipe_caller.py
src/soc/fu/logical/test/test_pipe_caller.py
src/soc/fu/mul/test/test_pipe_caller.py
src/soc/fu/regspec.py
src/soc/fu/shift_rot/rotator.py
src/soc/fu/shift_rot/test/test_pipe_caller.py
src/soc/fu/spr/test/test_pipe_caller.py
src/soc/fu/test/common.py
src/soc/fu/trap/test/test_pipe_caller.py
src/soc/minerva/units/loadstore.py
src/soc/regfile/regfile.py
src/soc/regfile/virtual_port.py
src/soc/scoreboard/addr_match.py
src/soc/scoreboard/addr_split.py
src/soc/scoreboard/instruction_q.py
src/soc/simple/core.py
src/soc/simple/test/test_core.py
src/soc/simple/test/test_issuer.py
src/soc/simple/test/test_microwatt.py
src/soc/simulator/program.py
src/soc/simulator/qemu.py
src/soc/simulator/test_sim.py
src/unused/TLB/ariane/plru.py