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add ldst PortInterface misalign unit test (underway)
[soc.git] / src /
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway) tree | commitdiff
2021-05-26 Luke Kenneth Casso... rename PLL signals tree | commitdiff
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop tree | commitdiff
2021-05-25 Tobias Platenwait_ldok: add debug output count tree | commitdiff
2021-05-24 Luke Kenneth Casso... whoops sort out name of SPBlock RAM tree | commitdiff
2021-05-24 Luke Kenneth Casso... change name of submodule to real_pll tree | commitdiff
2021-05-24 Luke Kenneth Casso... match up PLL names tree | commitdiff
2021-05-22 Cesar StraussMove the reset code outside of the sub-test tree | commitdiff
2021-05-22 Luke Kenneth Casso... update submodule tree | commitdiff
2021-05-22 Luke Kenneth Casso... update PLL to use Instance tree | commitdiff
2021-05-15 Tobias Platentest_ldst_pi.py: add dcache regression and random test... tree | commitdiff
2021-05-14 Luke Kenneth Casso... add radix MMU "miss" test tree | commitdiff
2021-05-14 Luke Kenneth Casso... clear out request data on return to idle tree | commitdiff
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required... tree | commitdiff
2021-05-14 Luke Kenneth Casso... remove minerva units previously missed in cleanout tree | commitdiff
2021-05-14 Luke Kenneth Casso... add misaligned load through MMU (which is incorrectly... tree | commitdiff
2021-05-13 Luke Kenneth Casso... minor rework of wb_get, make generic tree | commitdiff
2021-05-13 Luke Kenneth Casso... added STORE test in test_ldst_pi.py, and it worked... tree | commitdiff
2021-05-13 Luke Kenneth Casso... update comments in issuer.py regarding a 4th FSM tree | commitdiff
2021-05-13 Luke Kenneth Casso... yet more debug log stuff for DCache, this time on Cache... tree | commitdiff
2021-05-13 Luke Kenneth Casso... fix wb_get error where data was being corrupted tree | commitdiff
2021-05-13 Luke Kenneth Casso... add read at different locations in test_ldst_pi.py tree | commitdiff
2021-05-13 Luke Kenneth Casso... add some data for MMU to actually look up tree | commitdiff
2021-05-13 Luke Kenneth Casso... ha, hilarious: swapped TLBUpdate output sizes db_out... tree | commitdiff
2021-05-13 Luke Kenneth Casso... whoops TLBIE must *clear* the valid bit not set it... tree | commitdiff
2021-05-13 Luke Kenneth Casso... more debug Display in dcache.py tree | commitdiff
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache... tree | commitdiff
2021-05-12 Luke Kenneth Casso... add dcache tlb / pte test tree | commitdiff
2021-05-12 Luke Kenneth Casso... set m_out.load from ldst_r(egister) in LoadStore1 tree | commitdiff
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py tree | commitdiff
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through... tree | commitdiff
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in... tree | commitdiff
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface... tree | commitdiff
2021-05-12 Luke Kenneth Casso... whoops missing default zero (no idea how) tree | commitdiff
2021-05-12 Luke Kenneth Casso... addcomments for MMU PortInterface test (how it, um... tree | commitdiff
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational. tree | commitdiff
2021-05-12 Luke Kenneth Casso... whitespace tree | commitdiff
2021-05-12 Luke Kenneth Casso... no need for sel0 tree | commitdiff
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1 tree | commitdiff
2021-05-11 Luke Kenneth Casso... connect MSR.PR to PortInterface in LDSTCompUnit tree | commitdiff
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface tree | commitdiff
2021-05-11 Luke Kenneth Casso... add MSR to LD/ST Input Record tree | commitdiff
2021-05-11 Luke Kenneth Casso... comment tidyup tree | commitdiff
2021-05-11 Luke Kenneth Casso... must also pass through instruction fault exception... tree | commitdiff
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM tree | commitdiff
2021-05-11 Luke Kenneth Casso... tidyup comments and remove LoadStore COMPLETE state tree | commitdiff
2021-05-11 Luke Kenneth Casso... cleanup on exception setting tree | commitdiff
2021-05-11 Luke Kenneth Casso... rename LoadStore1 data structures back to microwatt... tree | commitdiff
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1 tree | commitdiff
2021-05-10 Luke Kenneth Casso... move LoadStore1 d_validblip setting, and get MMU_LOOKUP... tree | commitdiff
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py tree | commitdiff
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0 tree | commitdiff
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP tree | commitdiff
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments on translation of MMU_LOOKUP tree | commitdiff
2021-05-09 Luke Kenneth Casso... install MMU_LOOKUP vhdl to be translated to nmigen tree | commitdiff
2021-05-09 Luke Kenneth Casso... move (unused) ACK_WAIT code into FSM tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... remove invalid setting of d_in.valid from self.mmureq tree | commitdiff
2021-05-09 Luke Kenneth Casso... no SECOND_REQ tree | commitdiff
2021-05-09 Luke Kenneth Casso... remove SECOND_REQ tree | commitdiff
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid tree | commitdiff
2021-05-09 Tobias Platenmove skeleton to elaborate tree | commitdiff
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comment about LD/ST exception needs copying into... tree | commitdiff
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU tree | commitdiff
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link tree | commitdiff
2021-05-09 Luke Kenneth Casso... git submodule update tree | commitdiff
2021-05-09 Luke Kenneth Casso... update code-comments tree | commitdiff
2021-05-09 Luke Kenneth Casso... add in alignment exception capture/reporting in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... preference is to create a temp variable for comb and... tree | commitdiff
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase tree | commitdiff
2021-05-08 Luke Kenneth Casso... LoadStore1 tidyup tree | commitdiff
2021-05-08 Luke Kenneth Casso... transferring more over to LoadStore FSM tree | commitdiff
2021-05-08 Luke Kenneth Casso... start putting state info into LoadStore1, slowly puttin... tree | commitdiff
2021-05-08 Luke Kenneth Casso... add LoadStore State enum tree | commitdiff
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu tree | commitdiff
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc... tree | commitdiff
2021-05-07 Luke Kenneth Casso... start setting DSISR bits but commented out tree | commitdiff
2021-05-07 Luke Kenneth Casso... update comments and docstrings tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops, import error tree | commitdiff
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops was still copying output over in CommonOutputStage tree | commitdiff
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that... tree | commitdiff
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1 tree | commitdiff
2021-05-07 Luke Kenneth Casso... move zero-dest-pred in Common Output Stage to not copy... tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops setup of core.sv_pred_sm/dm not indented and... tree | commitdiff
2021-05-06 Luke Kenneth Casso... whoops disabled tests agaaaaain tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass relevant predicate mask bits through to Decoders... tree | commitdiff
2021-05-06 Luke Kenneth Casso... add in predicate mask bit detection when zeroing is... tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass SVP64 ReMap field through to core and then on... tree | commitdiff
2021-05-06 Luke Kenneth Casso... moved exts* SVP64 unit tests to a different location tree | commitdiff
2021-05-06 Luke Kenneth Casso... if zeroing is set, put zero into input or output as... tree | commitdiff
2021-05-05 Tobias Platenfix bug in mmu/fsm.py tree | commitdiff
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all tree | commitdiff
2021-05-05 Luke Kenneth Casso... whoops wrong signal name, set exc_happened tree | commitdiff
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record tree | commitdiff
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py tree | commitdiff
2021-05-04 Luke Kenneth Casso... remove minerva debug unit (not needed) tree | commitdiff
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