Add a HDL test case, where we start at the middle of the VL loop
[soc.git] / src /
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of...
2021-04-06 Cesar StraussStart the test case from a point where the predicate...
2021-04-05 Luke Kenneth Casso... litex submodule update
2021-04-05 Luke Kenneth Casso... submodule update
2021-04-04 Staf Verhaegensoc-cocotb-sim submodule update
2021-04-04 Cesar StraussAdd test case for reentrant VL loop
2021-04-03 Cesar StraussReminder for a possible hardware optimization
2021-04-03 Cesar StraussBe more precise when using a one-bit constant
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero
2021-04-03 Cesar StraussAdd a test case for integer single predication
2021-04-03 Cesar StraussDisallow unknown encmodes in SVP64 Assembly
2021-04-03 Cesar StraussEnable remaining disabled test cases
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-04-03 Cesar StraussSignal the simulator when completing a VL loop
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd twin predication test
2021-04-02 Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussAdd VEXPAND test case for the ISA Simulator
2021-04-02 Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
2021-04-02 Cesar StraussPut sanity check inside the existing '2Pred' case,...
2021-04-02 Cesar StraussEnforce explicit src/dest masks on CR twin-predication
2021-04-02 Cesar StraussDisallow mixing of sm=xx and/or dm=xx with m=xx on...
2021-04-02 Cesar StraussDisallow dm=xx on single predication
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussReally enforce sm=xx not being allowed on single-pred
2021-04-02 Cesar StraussKeep mask mode flags separate
2021-04-01 Luke Kenneth Casso... git submodule update
2021-04-01 Luke Kenneth Casso... TWI enabled in JTAG boundary scan
2021-04-01 Luke Kenneth Casso... git submodule update
2021-04-01 Luke Kenneth Casso... reduce subset of functions to be created in JTAG bounda...
2021-04-01 Luke Kenneth Casso... use OrderedDict to restore exact order from JSON file
2021-04-01 Luke Kenneth Casso... add soc-cocotb-sim submodule
2021-04-01 Luke Kenneth Casso... submodule update
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-04-01 Luke Kenneth Casso... bug in iverilog, segfaults due to empty case statement
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-03-31 Tobias Platen_new_lookup: remove unused argument mbits
2021-03-31 Tobias Platenradixmmu: read prtable entry
2021-03-31 Tobias Platenradixmmu.py: remove redunant code
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platenmore work on _prtable_lookup and testcase
2021-03-30 Luke Kenneth Casso... add comments
2021-03-30 Luke Kenneth Casso... use PRTBL SPR in RADIXMMU
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platencomment about microwatt implementation details
2021-03-30 Luke Kenneth Casso... add comments, correct load addresses
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Alain D D WilliamsAllow comments
2021-03-30 Tobias Platenadd function _prtable_lookup and unit test
2021-03-30 Luke Kenneth Casso... might have RADIXMMU at least semi-working... maybe
2021-03-30 Luke Kenneth Casso... use assertEqual in RADIXMMU unit test
2021-03-30 Luke Kenneth Casso... skip 1-pred check if m= used in SVP64Asm
2021-03-30 Cesar StraussEnable VCOMPRESS test case
2021-03-30 Cesar StraussAdd new twin predication case
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax
2021-03-30 Cesar StraussSkip leading zero bits on predicate masks
2021-03-30 Luke Kenneth Casso... use port name for INT regfile to match up with test_run...
2021-03-30 Luke Kenneth Casso... corrections to Makefile for building / not-building...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-29 Luke Kenneth Casso... correct segment check (off by one in LE/BE convert
2021-03-29 Luke Kenneth Casso... update submodule
2021-03-29 Luke Kenneth Casso... sort out pywriter.py when run with no args
2021-03-28 Luke Kenneth Casso... svp64-enable passed through to PowerDecoderSubsets...
2021-03-28 Luke Kenneth Casso... whoops spelling mistake in SPRreduced Enums
2021-03-28 Cesar StraussMove DECODE_SV to its place between MASK_WAIT and INSN_...
2021-03-28 Cesar StraussMove instruction decoding to after predication
2021-03-28 Cesar StraussPrepare to advance src/dst step after getting the predi...
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-28 Luke Kenneth Casso... add option to reduce number of regfile ports (get DFFs...
2021-03-28 Luke Kenneth Casso... reduce number of regfile ports
2021-03-28 Luke Kenneth Casso... reduce regfile port usage on non-svp64
2021-03-25 Tobias Platenradixmmu.py: cleanup, documentation
2021-03-25 Tobias Platenfix _get_prtable_addr, cleanup
2021-03-24 Luke Kenneth Casso... comment about using PriorityEncoder
2021-03-24 Luke Kenneth Casso... debug output
2021-03-24 Luke Kenneth Casso... add comment skipping in pagereader.py
2021-03-24 Luke Kenneth Casso... make svp64 isa caller unit tests more obvious
2021-03-24 Luke Kenneth Casso... add option to stop writing isa all.py in pseudocode...
2021-03-24 Luke Kenneth Casso... fix nonzero test in ISACaller RADIXMMU
2021-03-23 Tobias Platenmake addrshift human readable
2021-03-23 Tobias Platenadd addrshift function (based on microwatt)
2021-03-22 Luke Kenneth Casso... do not set sv_changed
2021-03-22 Tobias Platentestcase for _get_pgtable_addr
2021-03-22 Luke Kenneth Casso... read predicate mask from correct point in SVP64Asm
2021-03-22 Luke Kenneth Casso... add SVP64Asm option for "m=" to set both src and dest...
2021-03-22 Luke Kenneth Casso... add very small dff sram variant (no 4k SRAMs)
2021-03-22 Cesar StraussAdd test cases for integer VCOMPRESS and VEXPAND
2021-03-22 Luke Kenneth Casso... make sure non-svp64-mode works
2021-03-22 Luke Kenneth Casso... have get_predint return indicator that mask is all 1s
2021-03-22 Cesar StraussSkip fetching integer predicate mask when register...
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding
2021-03-22 Cesar StraussDecode and fetch integer predicate registers
2021-03-21 Cesar StraussFix typo
2021-03-21 Cesar StraussAdd unique name to decoded predication signals
2021-03-21 Cesar StraussRevert removal of *.value from Enums
2021-03-21 Cesar StraussFix syntax
2021-03-21 Luke Kenneth Casso... more TODO comments
2021-03-21 Luke Kenneth Casso... add for-loop pseudocode for CR predicate mask reading
next