+++ /dev/null
-[root]
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-
-[system]
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-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
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-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
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-
-[system.bridge]
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-
-[system.cf0]
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-
-[system.cf0.image]
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-
-[system.cf0.image.child]
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-
-[system.clk_domain]
-type=SrcClockDomain
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-
-[system.cpu0]
-type=MinorCPU
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-
-[system.cpu0.branchPred]
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-
-[system.cpu0.dcache]
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-size=32768
-system=system
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-
-[system.cpu0.dcache.tags]
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-
-[system.cpu0.dstage2_mmu]
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-
-[system.cpu0.dstage2_mmu.stage2_tlb]
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-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
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-
-[system.cpu0.dtb]
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-[system.cpu0.dtb.walker]
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-
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-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMemRead
-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMemWrite
-
-[system.cpu0.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu0.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=system.cpu1.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu1.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
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-executeSetTraceTimeOnCommit=true
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-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
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-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
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-p_state_clk_gate_min=1000
-power_model=Null
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-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
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-useIndirect=true
-
-[system.cpu1.dcache]
-type=Cache
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-assoc=2
-clk_domain=system.cpu_clk_domain
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-default_p_state=UNDEFINED
-demand_mshr_reserve=1
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-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
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-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
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-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
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-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
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-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
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-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6
-
-[system.cpu1.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu1.executeFuncUnits.funcUnits0.timings
-
-[system.cpu1.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu1.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu1.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu1.executeFuncUnits.funcUnits1.timings
-
-[system.cpu1.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu1.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
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-description=Int
-eventq_index=0
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-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu1.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu1.executeFuncUnits.funcUnits2.timings
-
-[system.cpu1.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
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-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu1.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
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-mask=0
-match=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu1.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu1.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu1.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu1.executeFuncUnits.funcUnits4.timings
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMisc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMultAcc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu1.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu1.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu1.executeFuncUnits.funcUnits5.timings
-
-[system.cpu1.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1 opClasses2 opClasses3
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3
-
-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMemRead
-
-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMemWrite
-
-[system.cpu1.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu1.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu1.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tag_latency=20
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-tag_latency=20
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
-warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: instruction 'mcr bpiall' unimplemented
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 19:38:26
-gem5 started Mar 29 2017 19:38:42
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83600
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2848623849000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.848624
-sim_ticks 2848623849000
-final_tick 2848623849000
-sim_freq 1000000000000
-host_inst_rate 254983
-host_op_rate 308756
-host_tick_rate 5710154970
-host_mem_usage 634664
-host_seconds 498.87
-sim_insts 127203067
-sim_ops 154028798
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2848623849000
-system.physmem.bytes_read::cpu0.dtb.walker 9536
-system.physmem.bytes_read::cpu0.itb.walker 64
-system.physmem.bytes_read::cpu0.inst 1667584
-system.physmem.bytes_read::cpu0.data 1358648
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8591232
-system.physmem.bytes_read::cpu1.dtb.walker 1280
-system.physmem.bytes_read::cpu1.inst 234816
-system.physmem.bytes_read::cpu1.data 662164
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 335296
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 12861580
-system.physmem.bytes_inst_read::cpu0.inst 1667584
-system.physmem.bytes_inst_read::cpu1.inst 234816
-system.physmem.bytes_inst_read::total 1902400
-system.physmem.bytes_written::writebacks 8982016
-system.physmem.bytes_written::cpu0.data 17524
-system.physmem.bytes_written::cpu1.data 40
-system.physmem.bytes_written::total 8999580
-system.physmem.num_reads::cpu0.dtb.walker 149
-system.physmem.num_reads::cpu0.itb.walker 1
-system.physmem.num_reads::cpu0.inst 26056
-system.physmem.num_reads::cpu0.data 21753
-system.physmem.num_reads::cpu0.l2cache.prefetcher 134238
-system.physmem.num_reads::cpu1.dtb.walker 20
-system.physmem.num_reads::cpu1.inst 3669
-system.physmem.num_reads::cpu1.data 10367
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5239
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 201507
-system.physmem.num_writes::writebacks 140344
-system.physmem.num_writes::cpu0.data 4381
-system.physmem.num_writes::cpu1.data 10
-system.physmem.num_writes::total 144735
-system.physmem.bw_read::cpu0.dtb.walker 3348
-system.physmem.bw_read::cpu0.itb.walker 22
-system.physmem.bw_read::cpu0.inst 585400
-system.physmem.bw_read::cpu0.data 476949
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3015924
-system.physmem.bw_read::cpu1.dtb.walker 449
-system.physmem.bw_read::cpu1.inst 82431
-system.physmem.bw_read::cpu1.data 232450
-system.physmem.bw_read::cpu1.l2cache.prefetcher 117705
-system.physmem.bw_read::realview.ide 337
-system.physmem.bw_read::total 4515015
-system.physmem.bw_inst_read::cpu0.inst 585400
-system.physmem.bw_inst_read::cpu1.inst 82431
-system.physmem.bw_inst_read::total 667831
-system.physmem.bw_write::writebacks 3153107
-system.physmem.bw_write::cpu0.data 6152
-system.physmem.bw_write::cpu1.data 14
-system.physmem.bw_write::total 3159273
-system.physmem.bw_total::writebacks 3153107
-system.physmem.bw_total::cpu0.dtb.walker 3348
-system.physmem.bw_total::cpu0.itb.walker 22
-system.physmem.bw_total::cpu0.inst 585400
-system.physmem.bw_total::cpu0.data 483101
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3015924
-system.physmem.bw_total::cpu1.dtb.walker 449
-system.physmem.bw_total::cpu1.inst 82431
-system.physmem.bw_total::cpu1.data 232465
-system.physmem.bw_total::cpu1.l2cache.prefetcher 117705
-system.physmem.bw_total::realview.ide 337
-system.physmem.bw_total::total 7674288
-system.physmem.readReqs 201507
-system.physmem.writeReqs 144735
-system.physmem.readBursts 201507
-system.physmem.writeBursts 144735
-system.physmem.bytesReadDRAM 12886784
-system.physmem.bytesReadWrQ 9664
-system.physmem.bytesWritten 9012160
-system.physmem.bytesReadSys 12861580
-system.physmem.bytesWrittenSys 8999580
-system.physmem.servicedByWrQ 151
-system.physmem.mergedWrBursts 3896
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 12371
-system.physmem.perBankRdBursts::1 12729
-system.physmem.perBankRdBursts::2 13637
-system.physmem.perBankRdBursts::3 13176
-system.physmem.perBankRdBursts::4 15206
-system.physmem.perBankRdBursts::5 12912
-system.physmem.perBankRdBursts::6 12737
-system.physmem.perBankRdBursts::7 12939
-system.physmem.perBankRdBursts::8 12121
-system.physmem.perBankRdBursts::9 12358
-system.physmem.perBankRdBursts::10 11582
-system.physmem.perBankRdBursts::11 10807
-system.physmem.perBankRdBursts::12 12020
-system.physmem.perBankRdBursts::13 12909
-system.physmem.perBankRdBursts::14 12059
-system.physmem.perBankRdBursts::15 11793
-system.physmem.perBankWrBursts::0 8805
-system.physmem.perBankWrBursts::1 9304
-system.physmem.perBankWrBursts::2 9936
-system.physmem.perBankWrBursts::3 9418
-system.physmem.perBankWrBursts::4 8548
-system.physmem.perBankWrBursts::5 9131
-system.physmem.perBankWrBursts::6 8974
-system.physmem.perBankWrBursts::7 9071
-system.physmem.perBankWrBursts::8 8560
-system.physmem.perBankWrBursts::9 8780
-system.physmem.perBankWrBursts::10 8271
-system.physmem.perBankWrBursts::11 7900
-system.physmem.perBankWrBursts::12 8752
-system.physmem.perBankWrBursts::13 8928
-system.physmem.perBankWrBursts::14 8529
-system.physmem.perBankWrBursts::15 7908
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 81
-system.physmem.totGap 2848623293000
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 555
-system.physmem.readPktSize::3 28
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 200924
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 4391
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 140344
-system.physmem.rdQLenPdf::0 85231
-system.physmem.rdQLenPdf::1 63458
-system.physmem.rdQLenPdf::2 11762
-system.physmem.rdQLenPdf::3 9672
-system.physmem.rdQLenPdf::4 8125
-system.physmem.rdQLenPdf::5 6741
-system.physmem.rdQLenPdf::6 5582
-system.physmem.rdQLenPdf::7 4883
-system.physmem.rdQLenPdf::8 4010
-system.physmem.rdQLenPdf::9 1041
-system.physmem.rdQLenPdf::10 301
-system.physmem.rdQLenPdf::11 244
-system.physmem.rdQLenPdf::12 163
-system.physmem.rdQLenPdf::13 133
-system.physmem.rdQLenPdf::14 4
-system.physmem.rdQLenPdf::15 2
-system.physmem.rdQLenPdf::16 1
-system.physmem.rdQLenPdf::17 1
-system.physmem.rdQLenPdf::18 1
-system.physmem.rdQLenPdf::19 1
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 2579
-system.physmem.wrQLenPdf::16 3466
-system.physmem.wrQLenPdf::17 4465
-system.physmem.wrQLenPdf::18 5100
-system.physmem.wrQLenPdf::19 6081
-system.physmem.wrQLenPdf::20 6495
-system.physmem.wrQLenPdf::21 7105
-system.physmem.wrQLenPdf::22 7482
-system.physmem.wrQLenPdf::23 8550
-system.physmem.wrQLenPdf::24 8454
-system.physmem.wrQLenPdf::25 9694
-system.physmem.wrQLenPdf::26 10241
-system.physmem.wrQLenPdf::27 8890
-system.physmem.wrQLenPdf::28 8481
-system.physmem.wrQLenPdf::29 8847
-system.physmem.wrQLenPdf::30 9999
-system.physmem.wrQLenPdf::31 8358
-system.physmem.wrQLenPdf::32 8021
-system.physmem.wrQLenPdf::33 878
-system.physmem.wrQLenPdf::34 529
-system.physmem.wrQLenPdf::35 472
-system.physmem.wrQLenPdf::36 388
-system.physmem.wrQLenPdf::37 315
-system.physmem.wrQLenPdf::38 296
-system.physmem.wrQLenPdf::39 291
-system.physmem.wrQLenPdf::40 294
-system.physmem.wrQLenPdf::41 261
-system.physmem.wrQLenPdf::42 323
-system.physmem.wrQLenPdf::43 287
-system.physmem.wrQLenPdf::44 247
-system.physmem.wrQLenPdf::45 264
-system.physmem.wrQLenPdf::46 292
-system.physmem.wrQLenPdf::47 229
-system.physmem.wrQLenPdf::48 187
-system.physmem.wrQLenPdf::49 201
-system.physmem.wrQLenPdf::50 190
-system.physmem.wrQLenPdf::51 167
-system.physmem.wrQLenPdf::52 232
-system.physmem.wrQLenPdf::53 203
-system.physmem.wrQLenPdf::54 172
-system.physmem.wrQLenPdf::55 242
-system.physmem.wrQLenPdf::56 262
-system.physmem.wrQLenPdf::57 203
-system.physmem.wrQLenPdf::58 150
-system.physmem.wrQLenPdf::59 219
-system.physmem.wrQLenPdf::60 213
-system.physmem.wrQLenPdf::61 193
-system.physmem.wrQLenPdf::62 95
-system.physmem.wrQLenPdf::63 221
-system.physmem.bytesPerActivate::samples 88702
-system.physmem.bytesPerActivate::mean 246.880025
-system.physmem.bytesPerActivate::gmean 141.304455
-system.physmem.bytesPerActivate::stdev 302.553851
-system.physmem.bytesPerActivate::0-127 44832 50.54% 50.54%
-system.physmem.bytesPerActivate::128-255 18757 21.15% 71.69%
-system.physmem.bytesPerActivate::256-383 6580 7.42% 79.11%
-system.physmem.bytesPerActivate::384-511 3817 4.30% 83.41%
-system.physmem.bytesPerActivate::512-639 2913 3.28% 86.69%
-system.physmem.bytesPerActivate::640-767 1571 1.77% 88.46%
-system.physmem.bytesPerActivate::768-895 958 1.08% 89.54%
-system.physmem.bytesPerActivate::896-1023 1010 1.14% 90.68%
-system.physmem.bytesPerActivate::1024-1151 8264 9.32% 100.00%
-system.physmem.bytesPerActivate::total 88702
-system.physmem.rdPerTurnAround::samples 6978
-system.physmem.rdPerTurnAround::mean 28.854256
-system.physmem.rdPerTurnAround::stdev 558.300170
-system.physmem.rdPerTurnAround::0-2047 6976 99.97% 99.97%
-system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99%
-system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00%
-system.physmem.rdPerTurnAround::total 6978
-system.physmem.wrPerTurnAround::samples 6978
-system.physmem.wrPerTurnAround::mean 20.179851
-system.physmem.wrPerTurnAround::gmean 18.509497
-system.physmem.wrPerTurnAround::stdev 14.198077
-system.physmem.wrPerTurnAround::16-19 5875 84.19% 84.19%
-system.physmem.wrPerTurnAround::20-23 429 6.15% 90.34%
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-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 [0] 1 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\r/cpus/cpu@1 missing clock-frequency property\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rCPU1: Booted secondary processor\r
-\rCPU1: thread -1, cpu 1, socket 0, mpidr 80000001\r
-\rBrought up 2 CPUs\r
-\rSMP: Total of 2 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: CPU 1 failed to disable vector catch\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 680, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
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-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
-warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: instruction 'mcr bpiall' unimplemented
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 19:38:26
-gem5 started Mar 29 2017 19:38:42
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83599
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2854927627500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.854928
-sim_ticks 2854927627500
-final_tick 2854927627500
-sim_freq 1000000000000
-host_inst_rate 259896
-host_op_rate 314233
-host_tick_rate 6638397944
-host_mem_usage 597276
-host_seconds 430.06
-sim_insts 111771703
-sim_ops 135139786
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2854927627500
-system.physmem.bytes_read::cpu.dtb.walker 6976
-system.physmem.bytes_read::cpu.itb.walker 128
-system.physmem.bytes_read::cpu.inst 1665856
-system.physmem.bytes_read::cpu.data 9168876
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 10842796
-system.physmem.bytes_inst_read::cpu.inst 1665856
-system.physmem.bytes_inst_read::total 1665856
-system.physmem.bytes_written::writebacks 7956992
-system.physmem.bytes_written::cpu.data 17524
-system.physmem.bytes_written::total 7974516
-system.physmem.num_reads::cpu.dtb.walker 109
-system.physmem.num_reads::cpu.itb.walker 2
-system.physmem.num_reads::cpu.inst 26029
-system.physmem.num_reads::cpu.data 143785
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 169940
-system.physmem.num_writes::writebacks 124328
-system.physmem.num_writes::cpu.data 4381
-system.physmem.num_writes::total 128709
-system.physmem.bw_read::cpu.dtb.walker 2443
-system.physmem.bw_read::cpu.itb.walker 45
-system.physmem.bw_read::cpu.inst 583502
-system.physmem.bw_read::cpu.data 3211597
-system.physmem.bw_read::realview.ide 336
-system.physmem.bw_read::total 3797923
-system.physmem.bw_inst_read::cpu.inst 583502
-system.physmem.bw_inst_read::total 583502
-system.physmem.bw_write::writebacks 2787108
-system.physmem.bw_write::cpu.data 6138
-system.physmem.bw_write::total 2793246
-system.physmem.bw_total::writebacks 2787108
-system.physmem.bw_total::cpu.dtb.walker 2443
-system.physmem.bw_total::cpu.itb.walker 45
-system.physmem.bw_total::cpu.inst 583502
-system.physmem.bw_total::cpu.data 3217735
-system.physmem.bw_total::realview.ide 336
-system.physmem.bw_total::total 6591170
-system.physmem.readReqs 169940
-system.physmem.writeReqs 128709
-system.physmem.readBursts 169940
-system.physmem.writeBursts 128709
-system.physmem.bytesReadDRAM 10867392
-system.physmem.bytesReadWrQ 8768
-system.physmem.bytesWritten 7987136
-system.physmem.bytesReadSys 10842796
-system.physmem.bytesWrittenSys 7974516
-system.physmem.servicedByWrQ 137
-system.physmem.mergedWrBursts 3888
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 10681
-system.physmem.perBankRdBursts::1 10442
-system.physmem.perBankRdBursts::2 10751
-system.physmem.perBankRdBursts::3 10388
-system.physmem.perBankRdBursts::4 13039
-system.physmem.perBankRdBursts::5 10185
-system.physmem.perBankRdBursts::6 10269
-system.physmem.perBankRdBursts::7 10713
-system.physmem.perBankRdBursts::8 10427
-system.physmem.perBankRdBursts::9 10646
-system.physmem.perBankRdBursts::10 10209
-system.physmem.perBankRdBursts::11 9539
-system.physmem.perBankRdBursts::12 10748
-system.physmem.perBankRdBursts::13 11527
-system.physmem.perBankRdBursts::14 10187
-system.physmem.perBankRdBursts::15 10052
-system.physmem.perBankWrBursts::0 7942
-system.physmem.perBankWrBursts::1 7866
-system.physmem.perBankWrBursts::2 8424
-system.physmem.perBankWrBursts::3 7907
-system.physmem.perBankWrBursts::4 7304
-system.physmem.perBankWrBursts::5 7363
-system.physmem.perBankWrBursts::6 7424
-system.physmem.perBankWrBursts::7 7906
-system.physmem.perBankWrBursts::8 7951
-system.physmem.perBankWrBursts::9 8140
-system.physmem.perBankWrBursts::10 7603
-system.physmem.perBankWrBursts::11 7336
-system.physmem.perBankWrBursts::12 8128
-system.physmem.perBankWrBursts::13 8674
-system.physmem.perBankWrBursts::14 7494
-system.physmem.perBankWrBursts::15 7337
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 63
-system.physmem.totGap 2854927178000
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 543
-system.physmem.readPktSize::3 14
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 169383
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 4381
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 124328
-system.physmem.rdQLenPdf::0 159867
-system.physmem.rdQLenPdf::1 9622
-system.physmem.rdQLenPdf::2 302
-system.physmem.rdQLenPdf::3 1
-system.physmem.rdQLenPdf::4 1
-system.physmem.rdQLenPdf::5 1
-system.physmem.rdQLenPdf::6 1
-system.physmem.rdQLenPdf::7 1
-system.physmem.rdQLenPdf::8 1
-system.physmem.rdQLenPdf::9 1
-system.physmem.rdQLenPdf::10 1
-system.physmem.rdQLenPdf::11 1
-system.physmem.rdQLenPdf::12 1
-system.physmem.rdQLenPdf::13 1
-system.physmem.rdQLenPdf::14 1
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 1807
-system.physmem.wrQLenPdf::16 2634
-system.physmem.wrQLenPdf::17 5993
-system.physmem.wrQLenPdf::18 6240
-system.physmem.wrQLenPdf::19 6528
-system.physmem.wrQLenPdf::20 6224
-system.physmem.wrQLenPdf::21 6599
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-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854927627500
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rBrought up 1 CPUs\r
-\rSMP: Total of 1 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: CPU 0 failed to disable vector catch\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu0.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu0.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu0.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
-eventq_index=0
-
-[system.cpu0.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList0.opList
-
-[system.cpu0.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2
-
-[system.cpu0.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu0.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
-
-[system.cpu0.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
-
-[system.cpu0.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
-
-[system.cpu0.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu0.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu0.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu1.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=1
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu1.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu1.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
-eventq_index=0
-
-[system.cpu1.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList0.opList
-
-[system.cpu1.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
-
-[system.cpu1.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu1.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
-
-[system.cpu1.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
-
-[system.cpu1.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
-
-[system.cpu1.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu1.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu1.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tag_latency=20
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-tag_latency=20
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: instruction 'mcr bpiall' unimplemented
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
-warn: allocating bonus target for snoop
-warn: allocating bonus target for snoop
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: instruction 'mcr dcisw' unimplemented
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 19:38:26
-gem5 started Mar 29 2017 19:38:42
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83601
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2826661822500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.826662
-sim_ticks 2826661822500
-final_tick 2826661822500
-sim_freq 1000000000000
-host_inst_rate 165299
-host_op_rate 200549
-host_tick_rate 3891148832
-host_mem_usage 635692
-host_seconds 726.43
-sim_insts 120078679
-sim_ops 145685700
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2826661822500
-system.physmem.bytes_read::cpu0.dtb.walker 1920
-system.physmem.bytes_read::cpu0.itb.walker 192
-system.physmem.bytes_read::cpu0.inst 1308752
-system.physmem.bytes_read::cpu0.data 1307816
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8391040
-system.physmem.bytes_read::cpu1.dtb.walker 320
-system.physmem.bytes_read::cpu1.itb.walker 64
-system.physmem.bytes_read::cpu1.inst 194400
-system.physmem.bytes_read::cpu1.data 594836
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 432000
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 12232300
-system.physmem.bytes_inst_read::cpu0.inst 1308752
-system.physmem.bytes_inst_read::cpu1.inst 194400
-system.physmem.bytes_inst_read::total 1503152
-system.physmem.bytes_written::writebacks 8791616
-system.physmem.bytes_written::cpu0.data 17524
-system.physmem.bytes_written::cpu1.data 40
-system.physmem.bytes_written::total 8809180
-system.physmem.num_reads::cpu0.dtb.walker 30
-system.physmem.num_reads::cpu0.itb.walker 3
-system.physmem.num_reads::cpu0.inst 22700
-system.physmem.num_reads::cpu0.data 20955
-system.physmem.num_reads::cpu0.l2cache.prefetcher 131110
-system.physmem.num_reads::cpu1.dtb.walker 5
-system.physmem.num_reads::cpu1.itb.walker 1
-system.physmem.num_reads::cpu1.inst 3105
-system.physmem.num_reads::cpu1.data 9315
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6750
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 193989
-system.physmem.num_writes::writebacks 137369
-system.physmem.num_writes::cpu0.data 4381
-system.physmem.num_writes::cpu1.data 10
-system.physmem.num_writes::total 141760
-system.physmem.bw_read::cpu0.dtb.walker 679
-system.physmem.bw_read::cpu0.itb.walker 68
-system.physmem.bw_read::cpu0.inst 463003
-system.physmem.bw_read::cpu0.data 462672
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2968533
-system.physmem.bw_read::cpu1.dtb.walker 113
-system.physmem.bw_read::cpu1.itb.walker 23
-system.physmem.bw_read::cpu1.inst 68774
-system.physmem.bw_read::cpu1.data 210438
-system.physmem.bw_read::cpu1.l2cache.prefetcher 152830
-system.physmem.bw_read::realview.ide 340
-system.physmem.bw_read::total 4327472
-system.physmem.bw_inst_read::cpu0.inst 463003
-system.physmem.bw_inst_read::cpu1.inst 68774
-system.physmem.bw_inst_read::total 531776
-system.physmem.bw_write::writebacks 3110247
-system.physmem.bw_write::cpu0.data 6200
-system.physmem.bw_write::cpu1.data 14
-system.physmem.bw_write::total 3116461
-system.physmem.bw_total::writebacks 3110247
-system.physmem.bw_total::cpu0.dtb.walker 679
-system.physmem.bw_total::cpu0.itb.walker 68
-system.physmem.bw_total::cpu0.inst 463003
-system.physmem.bw_total::cpu0.data 468871
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2968533
-system.physmem.bw_total::cpu1.dtb.walker 113
-system.physmem.bw_total::cpu1.itb.walker 23
-system.physmem.bw_total::cpu1.inst 68774
-system.physmem.bw_total::cpu1.data 210452
-system.physmem.bw_total::cpu1.l2cache.prefetcher 152830
-system.physmem.bw_total::realview.ide 340
-system.physmem.bw_total::total 7443933
-system.physmem.readReqs 193990
-system.physmem.writeReqs 141760
-system.physmem.readBursts 193990
-system.physmem.writeBursts 141760
-system.physmem.bytesReadDRAM 12404352
-system.physmem.bytesReadWrQ 10944
-system.physmem.bytesWritten 8822208
-system.physmem.bytesReadSys 12232364
-system.physmem.bytesWrittenSys 8809180
-system.physmem.servicedByWrQ 171
-system.physmem.mergedWrBursts 3896
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 11914
-system.physmem.perBankRdBursts::1 11892
-system.physmem.perBankRdBursts::2 12334
-system.physmem.perBankRdBursts::3 12168
-system.physmem.perBankRdBursts::4 14940
-system.physmem.perBankRdBursts::5 12679
-system.physmem.perBankRdBursts::6 12580
-system.physmem.perBankRdBursts::7 12786
-system.physmem.perBankRdBursts::8 12011
-system.physmem.perBankRdBursts::9 12103
-system.physmem.perBankRdBursts::10 11235
-system.physmem.perBankRdBursts::11 10159
-system.physmem.perBankRdBursts::12 11352
-system.physmem.perBankRdBursts::13 11878
-system.physmem.perBankRdBursts::14 11948
-system.physmem.perBankRdBursts::15 11839
-system.physmem.perBankWrBursts::0 8668
-system.physmem.perBankWrBursts::1 8756
-system.physmem.perBankWrBursts::2 9041
-system.physmem.perBankWrBursts::3 8790
-system.physmem.perBankWrBursts::4 8750
-system.physmem.perBankWrBursts::5 9282
-system.physmem.perBankWrBursts::6 9153
-system.physmem.perBankWrBursts::7 9187
-system.physmem.perBankWrBursts::8 8579
-system.physmem.perBankWrBursts::9 8637
-system.physmem.perBankWrBursts::10 8170
-system.physmem.perBankWrBursts::11 7474
-system.physmem.perBankWrBursts::12 8401
-system.physmem.perBankWrBursts::13 8247
-system.physmem.perBankWrBursts::14 8495
-system.physmem.perBankWrBursts::15 8217
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 62
-system.physmem.totGap 2826661535500
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 551
-system.physmem.readPktSize::3 28
-system.physmem.readPktSize::4 3091
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 190320
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 4391
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 137369
-system.physmem.rdQLenPdf::0 58346
-system.physmem.rdQLenPdf::1 70372
-system.physmem.rdQLenPdf::2 15665
-system.physmem.rdQLenPdf::3 12814
-system.physmem.rdQLenPdf::4 8399
-system.physmem.rdQLenPdf::5 7609
-system.physmem.rdQLenPdf::6 6485
-system.physmem.rdQLenPdf::7 5441
-system.physmem.rdQLenPdf::8 4697
-system.physmem.rdQLenPdf::9 1516
-system.physmem.rdQLenPdf::10 1147
-system.physmem.rdQLenPdf::11 744
-system.physmem.rdQLenPdf::12 307
-system.physmem.rdQLenPdf::13 271
-system.physmem.rdQLenPdf::14 6
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 2452
-system.physmem.wrQLenPdf::16 3359
-system.physmem.wrQLenPdf::17 3947
-system.physmem.wrQLenPdf::18 4490
-system.physmem.wrQLenPdf::19 5358
-system.physmem.wrQLenPdf::20 5708
-system.physmem.wrQLenPdf::21 6610
-system.physmem.wrQLenPdf::22 7231
-system.physmem.wrQLenPdf::23 8280
-system.physmem.wrQLenPdf::24 8230
-system.physmem.wrQLenPdf::25 9615
-system.physmem.wrQLenPdf::26 10123
-system.physmem.wrQLenPdf::27 8884
-system.physmem.wrQLenPdf::28 8655
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-system.physmem.wrQLenPdf::31 8635
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-system.physmem.wrQLenPdf::33 1065
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-system.physmem.wrQLenPdf::39 278
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-system.physmem.wrQLenPdf::41 222
-system.physmem.wrQLenPdf::42 229
-system.physmem.wrQLenPdf::43 228
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-system.physmem.wrQLenPdf::45 190
-system.physmem.wrQLenPdf::46 255
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-system.physmem.wrQLenPdf::48 184
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-system.physmem.wrQLenPdf::50 192
-system.physmem.wrQLenPdf::51 157
-system.physmem.wrQLenPdf::52 157
-system.physmem.wrQLenPdf::53 142
-system.physmem.wrQLenPdf::54 137
-system.physmem.wrQLenPdf::55 210
-system.physmem.wrQLenPdf::56 217
-system.physmem.wrQLenPdf::57 229
-system.physmem.wrQLenPdf::58 130
-system.physmem.wrQLenPdf::59 177
-system.physmem.wrQLenPdf::60 223
-system.physmem.wrQLenPdf::61 177
-system.physmem.wrQLenPdf::62 87
-system.physmem.wrQLenPdf::63 138
-system.physmem.bytesPerActivate::samples 84524
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-system.physmem.bytesPerActivate::128-255 17636 20.87% 71.31%
-system.physmem.bytesPerActivate::256-383 6205 7.34% 78.65%
-system.physmem.bytesPerActivate::384-511 3459 4.09% 82.74%
-system.physmem.bytesPerActivate::512-639 2826 3.34% 86.09%
-system.physmem.bytesPerActivate::640-767 1563 1.85% 87.94%
-system.physmem.bytesPerActivate::768-895 974 1.15% 89.09%
-system.physmem.bytesPerActivate::896-1023 1000 1.18% 90.27%
-system.physmem.bytesPerActivate::1024-1151 8223 9.73% 100.00%
-system.physmem.bytesPerActivate::total 84524
-system.physmem.rdPerTurnAround::samples 6835
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-system.physmem.rdPerTurnAround::stdev 562.818995
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-system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99%
-system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00%
-system.physmem.rdPerTurnAround::total 6835
-system.physmem.wrPerTurnAround::samples 6835
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-system.physmem.wrPerTurnAround::stdev 13.688369
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-system.physmem.wrPerTurnAround::20-23 371 5.43% 89.52%
-system.physmem.wrPerTurnAround::24-27 97 1.42% 90.94%
-system.physmem.wrPerTurnAround::28-31 47 0.69% 91.63%
-system.physmem.wrPerTurnAround::32-35 263 3.85% 95.48%
-system.physmem.wrPerTurnAround::36-39 24 0.35% 95.83%
-system.physmem.wrPerTurnAround::40-43 21 0.31% 96.14%
-system.physmem.wrPerTurnAround::44-47 10 0.15% 96.28%
-system.physmem.wrPerTurnAround::48-51 9 0.13% 96.42%
-system.physmem.wrPerTurnAround::52-55 6 0.09% 96.50%
-system.physmem.wrPerTurnAround::56-59 3 0.04% 96.55%
-system.physmem.wrPerTurnAround::60-63 8 0.12% 96.66%
-system.physmem.wrPerTurnAround::64-67 142 2.08% 98.74%
-system.physmem.wrPerTurnAround::68-71 10 0.15% 98.89%
-system.physmem.wrPerTurnAround::72-75 7 0.10% 98.99%
-system.physmem.wrPerTurnAround::76-79 3 0.04% 99.03%
-system.physmem.wrPerTurnAround::80-83 8 0.12% 99.15%
-system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18%
-system.physmem.wrPerTurnAround::88-91 3 0.04% 99.22%
-system.physmem.wrPerTurnAround::96-99 3 0.04% 99.27%
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.28%
-system.physmem.wrPerTurnAround::108-111 7 0.10% 99.39%
-system.physmem.wrPerTurnAround::112-115 4 0.06% 99.44%
-system.physmem.wrPerTurnAround::116-119 3 0.04% 99.49%
-system.physmem.wrPerTurnAround::128-131 14 0.20% 99.69%
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.71%
-system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72%
-system.physmem.wrPerTurnAround::140-143 5 0.07% 99.80%
-system.physmem.wrPerTurnAround::144-147 1 0.01% 99.81%
-system.physmem.wrPerTurnAround::156-159 4 0.06% 99.87%
-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90%
-system.physmem.wrPerTurnAround::168-171 1 0.01% 99.91%
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.94%
-system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97%
-system.physmem.wrPerTurnAround::192-195 1 0.01% 99.99%
-system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00%
-system.physmem.wrPerTurnAround::total 6835
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-system.physmem_0.actPowerDownEnergy 9126143460
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-system.physmem_0.selfRefreshEnergy 667515620400
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-system.physmem_0.averagePower 245.665627
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-system.physmem_1.actEnergy 286970880
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-system.physmem_1.writeEnergy 345668400
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-system.physmem_1.actBackEnergy 4789448370
-system.physmem_1.preBackEnergy 246990720
-system.physmem_1.actPowerDownEnergy 8737527720
-system.physmem_1.prePowerDownEnergy 6775449120
-system.physmem_1.selfRefreshEnergy 667645471770
-system.physmem_1.totalEnergy 694209041370
-system.physmem_1.averagePower 245.593242
-system.physmem_1.totalIdleTime 2815511892167
-system.physmem_1.memoryStateTime::IDLE 431458200
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-system.physmem_1.memoryStateTime::PRE_PDN 17644479066
-system.physmem_1.memoryStateTime::ACT 8778278133
-system.physmem_1.memoryStateTime::ACT_PDN 19161122851
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826661822500
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-system.realview.nvmem.bytes_read::cpu1.inst 176
-system.realview.nvmem.bytes_read::total 288
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-system.realview.nvmem.bytes_inst_read::cpu1.inst 176
-system.realview.nvmem.bytes_inst_read::total 288
-system.realview.nvmem.num_reads::cpu0.inst 7
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-system.realview.nvmem.bw_read::cpu0.inst 40
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-system.realview.nvmem.bw_read::total 102
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-system.realview.nvmem.bw_inst_read::total 102
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-system.toL2Bus.trans_dist::WritebackDirty 362520
-system.toL2Bus.trans_dist::CleanEvict 130460
-system.toL2Bus.trans_dist::UpgradeReq 111507
-system.toL2Bus.trans_dist::SCUpgradeReq 43885
-system.toL2Bus.trans_dist::UpgradeResp 155392
-system.toL2Bus.trans_dist::SCUpgradeFailReq 23
-system.toL2Bus.trans_dist::UpgradeFailResp 23
-system.toL2Bus.trans_dist::ReadExReq 50602
-system.toL2Bus.trans_dist::ReadExResp 50602
-system.toL2Bus.trans_dist::ReadSharedReq 485601
-system.toL2Bus.trans_dist::InvalidateReq 4649
-system.toL2Bus.trans_dist::InvalidateResp 3450
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1262886
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366763
-system.toL2Bus.pkt_count::total 1629649
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36014414
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5893094
-system.toL2Bus.pkt_size::total 41907508
-system.toL2Bus.snoops 396124
-system.toL2Bus.snoopTraffic 15887052
-system.toL2Bus.snoop_fanout::samples 902717
-system.toL2Bus.snoop_fanout::mean 0.407309
-system.toL2Bus.snoop_fanout::stdev 0.494119
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.toL2Bus.snoop_fanout::0 536271 59.41% 59.41%
-system.toL2Bus.snoop_fanout::1 365207 40.46% 99.86%
-system.toL2Bus.snoop_fanout::2 1239 0.14% 100.00%
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.toL2Bus.snoop_fanout::min_value 0
-system.toL2Bus.snoop_fanout::max_value 2
-system.toL2Bus.snoop_fanout::total 902717
-system.toL2Bus.reqLayer0.occupancy 897869135
-system.toL2Bus.reqLayer0.utilization 0.0
-system.toL2Bus.snoopLayer0.occupancy 2163785
-system.toL2Bus.snoopLayer0.utilization 0.0
-system.toL2Bus.respLayer0.occupancy 676148084
-system.toL2Bus.respLayer0.utilization 0.0
-system.toL2Bus.respLayer1.occupancy 261623426
-system.toL2Bus.respLayer1.utilization 0.0
-system.cpu0.kern.inst.arm 0
-system.cpu0.kern.inst.quiesce 1835
-system.cpu1.kern.inst.arm 0
-system.cpu1.kern.inst.quiesce 2780
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 [0] 1 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\r/cpus/cpu@1 missing clock-frequency property\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rCPU1: Booted secondary processor\r
-\rCPU1: thread -1, cpu 1, socket 0, mpidr 80000001\r
-\rBrought up 2 CPUs\r
-\rSMP: Total of 2 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: CPU 1 failed to disable vector catch\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 680, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
-warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
-warn: instruction 'mcr dcisw' unimplemented
-warn: instruction 'mcr bpiall' unimplemented
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 19:38:26
-gem5 started Mar 29 2017 19:38:42
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83598
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2829109393000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.829109
-sim_ticks 2829109393000
-final_tick 2829109393000
-sim_freq 1000000000000
-host_inst_rate 156850
-host_op_rate 190249
-host_tick_rate 3922204627
-host_mem_usage 597276
-host_seconds 721.31
-sim_insts 113136633
-sim_ops 137227543
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.physmem.bytes_read::cpu.dtb.walker 960
-system.physmem.bytes_read::cpu.itb.walker 384
-system.physmem.bytes_read::cpu.inst 1316768
-system.physmem.bytes_read::cpu.data 9473512
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 10792584
-system.physmem.bytes_inst_read::cpu.inst 1316768
-system.physmem.bytes_inst_read::total 1316768
-system.physmem.bytes_written::writebacks 8092288
-system.physmem.bytes_written::cpu.data 17524
-system.physmem.bytes_written::total 8109812
-system.physmem.num_reads::cpu.dtb.walker 15
-system.physmem.num_reads::cpu.itb.walker 6
-system.physmem.num_reads::cpu.inst 22826
-system.physmem.num_reads::cpu.data 148544
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 171406
-system.physmem.num_writes::writebacks 126442
-system.physmem.num_writes::cpu.data 4381
-system.physmem.num_writes::total 130823
-system.physmem.bw_read::cpu.dtb.walker 339
-system.physmem.bw_read::cpu.itb.walker 136
-system.physmem.bw_read::cpu.inst 465436
-system.physmem.bw_read::cpu.data 3348585
-system.physmem.bw_read::realview.ide 339
-system.physmem.bw_read::total 3814834
-system.physmem.bw_inst_read::cpu.inst 465436
-system.physmem.bw_inst_read::total 465436
-system.physmem.bw_write::writebacks 2860366
-system.physmem.bw_write::cpu.data 6194
-system.physmem.bw_write::total 2866560
-system.physmem.bw_total::writebacks 2860366
-system.physmem.bw_total::cpu.dtb.walker 339
-system.physmem.bw_total::cpu.itb.walker 136
-system.physmem.bw_total::cpu.inst 465436
-system.physmem.bw_total::cpu.data 3354779
-system.physmem.bw_total::realview.ide 339
-system.physmem.bw_total::total 6681395
-system.physmem.readReqs 171407
-system.physmem.writeReqs 130823
-system.physmem.readBursts 171407
-system.physmem.writeBursts 130823
-system.physmem.bytesReadDRAM 10960384
-system.physmem.bytesReadWrQ 9600
-system.physmem.bytesWritten 8122304
-system.physmem.bytesReadSys 10792648
-system.physmem.bytesWrittenSys 8109812
-system.physmem.servicedByWrQ 150
-system.physmem.mergedWrBursts 3888
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 10684
-system.physmem.perBankRdBursts::1 10049
-system.physmem.perBankRdBursts::2 10840
-system.physmem.perBankRdBursts::3 10900
-system.physmem.perBankRdBursts::4 13724
-system.physmem.perBankRdBursts::5 10682
-system.physmem.perBankRdBursts::6 11440
-system.physmem.perBankRdBursts::7 11401
-system.physmem.perBankRdBursts::8 10108
-system.physmem.perBankRdBursts::9 10401
-system.physmem.perBankRdBursts::10 10362
-system.physmem.perBankRdBursts::11 9483
-system.physmem.perBankRdBursts::12 10229
-system.physmem.perBankRdBursts::13 11049
-system.physmem.perBankRdBursts::14 10017
-system.physmem.perBankRdBursts::15 9887
-system.physmem.perBankWrBursts::0 8065
-system.physmem.perBankWrBursts::1 7697
-system.physmem.perBankWrBursts::2 8367
-system.physmem.perBankWrBursts::3 8156
-system.physmem.perBankWrBursts::4 8125
-system.physmem.perBankWrBursts::5 8041
-system.physmem.perBankWrBursts::6 8547
-system.physmem.perBankWrBursts::7 8476
-system.physmem.perBankWrBursts::8 7686
-system.physmem.perBankWrBursts::9 7979
-system.physmem.perBankWrBursts::10 7776
-system.physmem.perBankWrBursts::11 7088
-system.physmem.perBankWrBursts::12 7779
-system.physmem.perBankWrBursts::13 8427
-system.physmem.perBankWrBursts::14 7463
-system.physmem.perBankWrBursts::15 7239
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 69
-system.physmem.totGap 2829109158000
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 542
-system.physmem.readPktSize::3 14
-system.physmem.readPktSize::4 3002
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 167849
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 4381
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 126442
-system.physmem.rdQLenPdf::0 150080
-system.physmem.rdQLenPdf::1 14981
-system.physmem.rdQLenPdf::2 5321
-system.physmem.rdQLenPdf::3 857
-system.physmem.rdQLenPdf::4 8
-system.physmem.rdQLenPdf::5 1
-system.physmem.rdQLenPdf::6 1
-system.physmem.rdQLenPdf::7 1
-system.physmem.rdQLenPdf::8 1
-system.physmem.rdQLenPdf::9 1
-system.physmem.rdQLenPdf::10 1
-system.physmem.rdQLenPdf::11 1
-system.physmem.rdQLenPdf::12 1
-system.physmem.rdQLenPdf::13 1
-system.physmem.rdQLenPdf::14 1
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 1803
-system.physmem.wrQLenPdf::16 2658
-system.physmem.wrQLenPdf::17 5613
-system.physmem.wrQLenPdf::18 5988
-system.physmem.wrQLenPdf::19 6569
-system.physmem.wrQLenPdf::20 6381
-system.physmem.wrQLenPdf::21 6737
-system.physmem.wrQLenPdf::22 7035
-system.physmem.wrQLenPdf::23 7852
-system.physmem.wrQLenPdf::24 7599
-system.physmem.wrQLenPdf::25 8624
-system.physmem.wrQLenPdf::26 9219
-system.physmem.wrQLenPdf::27 7734
-system.physmem.wrQLenPdf::28 7242
-system.physmem.wrQLenPdf::29 7370
-system.physmem.wrQLenPdf::30 7208
-system.physmem.wrQLenPdf::31 6701
-system.physmem.wrQLenPdf::32 6786
-system.physmem.wrQLenPdf::33 501
-system.physmem.wrQLenPdf::34 459
-system.physmem.wrQLenPdf::35 378
-system.physmem.wrQLenPdf::36 383
-system.physmem.wrQLenPdf::37 289
-system.physmem.wrQLenPdf::38 265
-system.physmem.wrQLenPdf::39 270
-system.physmem.wrQLenPdf::40 276
-system.physmem.wrQLenPdf::41 266
-system.physmem.wrQLenPdf::42 282
-system.physmem.wrQLenPdf::43 261
-system.physmem.wrQLenPdf::44 314
-system.physmem.wrQLenPdf::45 244
-system.physmem.wrQLenPdf::46 267
-system.physmem.wrQLenPdf::47 237
-system.physmem.wrQLenPdf::48 219
-system.physmem.wrQLenPdf::49 245
-system.physmem.wrQLenPdf::50 257
-system.physmem.wrQLenPdf::51 167
-system.physmem.wrQLenPdf::52 195
-system.physmem.wrQLenPdf::53 254
-system.physmem.wrQLenPdf::54 199
-system.physmem.wrQLenPdf::55 174
-system.physmem.wrQLenPdf::56 193
-system.physmem.wrQLenPdf::57 192
-system.physmem.wrQLenPdf::58 143
-system.physmem.wrQLenPdf::59 217
-system.physmem.wrQLenPdf::60 164
-system.physmem.wrQLenPdf::61 198
-system.physmem.wrQLenPdf::62 91
-system.physmem.wrQLenPdf::63 201
-system.physmem.bytesPerActivate::samples 61301
-system.physmem.bytesPerActivate::mean 311.294889
-system.physmem.bytesPerActivate::gmean 183.533809
-system.physmem.bytesPerActivate::stdev 329.850338
-system.physmem.bytesPerActivate::0-127 22597 36.86% 36.86%
-system.physmem.bytesPerActivate::128-255 14681 23.95% 60.81%
-system.physmem.bytesPerActivate::256-383 6414 10.46% 71.27%
-system.physmem.bytesPerActivate::384-511 3628 5.92% 77.19%
-system.physmem.bytesPerActivate::512-639 2616 4.27% 81.46%
-system.physmem.bytesPerActivate::640-767 1714 2.80% 84.26%
-system.physmem.bytesPerActivate::768-895 1083 1.77% 86.02%
-system.physmem.bytesPerActivate::896-1023 1015 1.66% 87.68%
-system.physmem.bytesPerActivate::1024-1151 7553 12.32% 100.00%
-system.physmem.bytesPerActivate::total 61301
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-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
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-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
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-system.iobus.reqLayer10.occupancy 20000
-system.iobus.reqLayer10.utilization 0.0
-system.iobus.reqLayer13.occupancy 9500
-system.iobus.reqLayer13.utilization 0.0
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-system.iobus.reqLayer16.occupancy 47500
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-system.iobus.reqLayer17.occupancy 8500
-system.iobus.reqLayer17.utilization 0.0
-system.iobus.reqLayer18.occupancy 9500
-system.iobus.reqLayer18.utilization 0.0
-system.iobus.reqLayer19.occupancy 3000
-system.iobus.reqLayer19.utilization 0.0
-system.iobus.reqLayer20.occupancy 9000
-system.iobus.reqLayer20.utilization 0.0
-system.iobus.reqLayer21.occupancy 8500
-system.iobus.reqLayer21.utilization 0.0
-system.iobus.reqLayer23.occupancy 6162500
-system.iobus.reqLayer23.utilization 0.0
-system.iobus.reqLayer24.occupancy 33869500
-system.iobus.reqLayer24.utilization 0.0
-system.iobus.reqLayer25.occupancy 187590638
-system.iobus.reqLayer25.utilization 0.0
-system.iobus.respLayer0.occupancy 82668000
-system.iobus.respLayer0.utilization 0.0
-system.iobus.respLayer3.occupancy 36712000
-system.iobus.respLayer3.utilization 0.0
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-system.iocache.tags.replacements 36410
-system.iocache.tags.tagsinuse 1.001806
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-system.iocache.tags.avg_refs 0
-system.iocache.tags.warmup_cycle 253685816000
-system.iocache.tags.occ_blocks::realview.ide 1.001806
-system.iocache.tags.occ_percent::realview.ide 0.062613
-system.iocache.tags.occ_percent::total 0.062613
-system.iocache.tags.occ_task_id_blocks::1023 16
-system.iocache.tags.age_task_id_blocks_1023::3 16
-system.iocache.tags.occ_task_id_percent::1023 1
-system.iocache.tags.tag_accesses 327996
-system.iocache.tags.data_accesses 327996
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-system.iocache.ReadReq_misses::total 220
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-system.iocache.WriteLineReq_misses::total 36224
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-system.iocache.demand_misses::total 36444
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-system.iocache.overall_misses::total 36444
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-system.iocache.ReadReq_miss_latency::total 35734875
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-system.iocache.WriteLineReq_miss_latency::total 4371242763
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-system.iocache.demand_miss_latency::total 4406977638
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-system.iocache.ReadReq_accesses::total 220
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-system.iocache.overall_accesses::total 36444
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-system.iocache.blocked::no_mshrs 2
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-system.iocache.avg_blocked_cycles::no_targets nan
-system.iocache.writebacks::writebacks 36190
-system.iocache.writebacks::total 36190
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-system.iocache.ReadReq_mshr_misses::total 220
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-system.iocache.overall_mshr_misses::total 36444
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-system.iocache.demand_mshr_miss_latency::total 2582992856
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-system.iocache.overall_avg_mshr_miss_latency::total 70875.668313
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-system.membus.snoop_filter.hit_single_requests 139323
-system.membus.snoop_filter.hit_multi_requests 511
-system.membus.snoop_filter.tot_snoops 0
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-system.membus.trans_dist::WriteResp 27574
-system.membus.trans_dist::WritebackDirty 126442
-system.membus.trans_dist::CleanEvict 8078
-system.membus.trans_dist::UpgradeReq 126
-system.membus.trans_dist::SCUpgradeReq 2
-system.membus.trans_dist::UpgradeResp 2
-system.membus.trans_dist::ReadExReq 134980
-system.membus.trans_dist::ReadExResp 134980
-system.membus.trans_dist::ReadSharedReq 33351
-system.membus.trans_dist::InvalidateReq 36224
-system.membus.trans_dist::InvalidateResp 4572
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2030
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450060
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557562
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869
-system.membus.pkt_count_system.iocache.mem_side::total 72869
-system.membus.pkt_count::total 630431
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4060
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16585276
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16748563
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
-system.membus.pkt_size_system.iocache.mem_side::total 2317120
-system.membus.pkt_size::total 19065683
-system.membus.snoops 5056
-system.membus.snoopTraffic 30848
-system.membus.snoop_fanout::samples 266373
-system.membus.snoop_fanout::mean 0.019150
-system.membus.snoop_fanout::stdev 0.137052
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 261272 98.09% 98.09%
-system.membus.snoop_fanout::1 5101 1.91% 100.00%
-system.membus.snoop_fanout::2 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 1
-system.membus.snoop_fanout::total 266373
-system.membus.reqLayer0.occupancy 84445500
-system.membus.reqLayer0.utilization 0.0
-system.membus.reqLayer1.occupancy 9000
-system.membus.reqLayer1.utilization 0.0
-system.membus.reqLayer2.occupancy 1696499
-system.membus.reqLayer2.utilization 0.0
-system.membus.reqLayer5.occupancy 877138444
-system.membus.reqLayer5.utilization 0.0
-system.membus.respLayer2.occupancy 984755250
-system.membus.respLayer2.utilization 0.0
-system.membus.respLayer3.occupancy 5968652
-system.membus.respLayer3.utilization 0.0
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.dcc.osc_cpu.clock 16667
-system.realview.dcc.osc_ddr.clock 25000
-system.realview.dcc.osc_hsbm.clock 25000
-system.realview.dcc.osc_pxl.clock 42105
-system.realview.dcc.osc_smb.clock 20000
-system.realview.dcc.osc_sys.clock 16667
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.ethernet.descDMAReads 0
-system.realview.ethernet.descDMAWrites 0
-system.realview.ethernet.descDmaReadBytes 0
-system.realview.ethernet.descDmaWriteBytes 0
-system.realview.ethernet.postedSwi 0
-system.realview.ethernet.coalescedSwi nan
-system.realview.ethernet.totalSwi 0
-system.realview.ethernet.postedRxIdle 0
-system.realview.ethernet.coalescedRxIdle nan
-system.realview.ethernet.totalRxIdle 0
-system.realview.ethernet.postedRxOk 0
-system.realview.ethernet.coalescedRxOk nan
-system.realview.ethernet.totalRxOk 0
-system.realview.ethernet.postedRxDesc 0
-system.realview.ethernet.coalescedRxDesc nan
-system.realview.ethernet.totalRxDesc 0
-system.realview.ethernet.postedTxOk 0
-system.realview.ethernet.coalescedTxOk nan
-system.realview.ethernet.totalTxOk 0
-system.realview.ethernet.postedTxIdle 0
-system.realview.ethernet.coalescedTxIdle nan
-system.realview.ethernet.totalTxIdle 0
-system.realview.ethernet.postedTxDesc 0
-system.realview.ethernet.coalescedTxDesc nan
-system.realview.ethernet.totalTxDesc 0
-system.realview.ethernet.postedRxOrn 0
-system.realview.ethernet.coalescedRxOrn nan
-system.realview.ethernet.totalRxOrn 0
-system.realview.ethernet.coalescedTotal nan
-system.realview.ethernet.postedInterrupts 0
-system.realview.ethernet.droppedPackets 0
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.mcc.osc_clcd.clock 42105
-system.realview.mcc.osc_mcc.clock 20000
-system.realview.mcc.osc_peripheral.clock 41667
-system.realview.mcc.osc_system_bus.clock 41667
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
-system.cpu.kern.inst.arm 0
-system.cpu.kern.inst.quiesce 3039
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rBrought up 1 CPUs\r
-\rSMP: Total of 1 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: CPU 0 failed to disable vector catch\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.894518
-sim_ticks 2894518015000
-final_tick 2894518015000
-sim_freq 1000000000000
-host_inst_rate 160490
-host_op_rate 193630
-host_tick_rate 3969302938
-host_mem_usage 829632
-host_seconds 729.23
-sim_insts 117033526
-sim_ops 141199810
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 2894518015000
-system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 6066368
-system.mem_ctrls0.bytes_read::total 6066368
-system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 4470144
-system.mem_ctrls0.bytes_written::total 4470144
-system.mem_ctrls0.num_reads::ruby.dir_cntrl0 94787
-system.mem_ctrls0.num_reads::total 94787
-system.mem_ctrls0.num_writes::ruby.dir_cntrl0 69846
-system.mem_ctrls0.num_writes::total 69846
-system.mem_ctrls0.bw_read::ruby.dir_cntrl0 2095813
-system.mem_ctrls0.bw_read::total 2095813
-system.mem_ctrls0.bw_write::ruby.dir_cntrl0 1544348
-system.mem_ctrls0.bw_write::total 1544348
-system.mem_ctrls0.bw_total::ruby.dir_cntrl0 3640161
-system.mem_ctrls0.bw_total::total 3640161
-system.mem_ctrls0.readReqs 94787
-system.mem_ctrls0.writeReqs 69846
-system.mem_ctrls0.readBursts 94787
-system.mem_ctrls0.writeBursts 69846
-system.mem_ctrls0.bytesReadDRAM 6052864
-system.mem_ctrls0.bytesReadWrQ 13504
-system.mem_ctrls0.bytesWritten 4468608
-system.mem_ctrls0.bytesReadSys 6066368
-system.mem_ctrls0.bytesWrittenSys 4470144
-system.mem_ctrls0.servicedByWrQ 211
-system.mem_ctrls0.mergedWrBursts 0
-system.mem_ctrls0.neitherReadNorWriteReqs 0
-system.mem_ctrls0.perBankRdBursts::0 6950
-system.mem_ctrls0.perBankRdBursts::1 6637
-system.mem_ctrls0.perBankRdBursts::2 5437
-system.mem_ctrls0.perBankRdBursts::3 6196
-system.mem_ctrls0.perBankRdBursts::4 5957
-system.mem_ctrls0.perBankRdBursts::5 5597
-system.mem_ctrls0.perBankRdBursts::6 5359
-system.mem_ctrls0.perBankRdBursts::7 5164
-system.mem_ctrls0.perBankRdBursts::8 5289
-system.mem_ctrls0.perBankRdBursts::9 5131
-system.mem_ctrls0.perBankRdBursts::10 6244
-system.mem_ctrls0.perBankRdBursts::11 6522
-system.mem_ctrls0.perBankRdBursts::12 5710
-system.mem_ctrls0.perBankRdBursts::13 6158
-system.mem_ctrls0.perBankRdBursts::14 6261
-system.mem_ctrls0.perBankRdBursts::15 5964
-system.mem_ctrls0.perBankWrBursts::0 4983
-system.mem_ctrls0.perBankWrBursts::1 4822
-system.mem_ctrls0.perBankWrBursts::2 3964
-system.mem_ctrls0.perBankWrBursts::3 4511
-system.mem_ctrls0.perBankWrBursts::4 4495
-system.mem_ctrls0.perBankWrBursts::5 4284
-system.mem_ctrls0.perBankWrBursts::6 3997
-system.mem_ctrls0.perBankWrBursts::7 3931
-system.mem_ctrls0.perBankWrBursts::8 4159
-system.mem_ctrls0.perBankWrBursts::9 4052
-system.mem_ctrls0.perBankWrBursts::10 4645
-system.mem_ctrls0.perBankWrBursts::11 4640
-system.mem_ctrls0.perBankWrBursts::12 4126
-system.mem_ctrls0.perBankWrBursts::13 4592
-system.mem_ctrls0.perBankWrBursts::14 4476
-system.mem_ctrls0.perBankWrBursts::15 4145
-system.mem_ctrls0.numRdRetry 0
-system.mem_ctrls0.numWrRetry 0
-system.mem_ctrls0.totGap 2894517214500
-system.mem_ctrls0.readPktSize::0 0
-system.mem_ctrls0.readPktSize::1 0
-system.mem_ctrls0.readPktSize::2 0
-system.mem_ctrls0.readPktSize::3 0
-system.mem_ctrls0.readPktSize::4 0
-system.mem_ctrls0.readPktSize::5 0
-system.mem_ctrls0.readPktSize::6 94787
-system.mem_ctrls0.writePktSize::0 0
-system.mem_ctrls0.writePktSize::1 0
-system.mem_ctrls0.writePktSize::2 0
-system.mem_ctrls0.writePktSize::3 0
-system.mem_ctrls0.writePktSize::4 0
-system.mem_ctrls0.writePktSize::5 0
-system.mem_ctrls0.writePktSize::6 69846
-system.mem_ctrls0.rdQLenPdf::0 94478
-system.mem_ctrls0.rdQLenPdf::1 98
-system.mem_ctrls0.rdQLenPdf::2 0
-system.mem_ctrls0.rdQLenPdf::3 0
-system.mem_ctrls0.rdQLenPdf::4 0
-system.mem_ctrls0.rdQLenPdf::5 0
-system.mem_ctrls0.rdQLenPdf::6 0
-system.mem_ctrls0.rdQLenPdf::7 0
-system.mem_ctrls0.rdQLenPdf::8 0
-system.mem_ctrls0.rdQLenPdf::9 0
-system.mem_ctrls0.rdQLenPdf::10 0
-system.mem_ctrls0.rdQLenPdf::11 0
-system.mem_ctrls0.rdQLenPdf::12 0
-system.mem_ctrls0.rdQLenPdf::13 0
-system.mem_ctrls0.rdQLenPdf::14 0
-system.mem_ctrls0.rdQLenPdf::15 0
-system.mem_ctrls0.rdQLenPdf::16 0
-system.mem_ctrls0.rdQLenPdf::17 0
-system.mem_ctrls0.rdQLenPdf::18 0
-system.mem_ctrls0.rdQLenPdf::19 0
-system.mem_ctrls0.rdQLenPdf::20 0
-system.mem_ctrls0.rdQLenPdf::21 0
-system.mem_ctrls0.rdQLenPdf::22 0
-system.mem_ctrls0.rdQLenPdf::23 0
-system.mem_ctrls0.rdQLenPdf::24 0
-system.mem_ctrls0.rdQLenPdf::25 0
-system.mem_ctrls0.rdQLenPdf::26 0
-system.mem_ctrls0.rdQLenPdf::27 0
-system.mem_ctrls0.rdQLenPdf::28 0
-system.mem_ctrls0.rdQLenPdf::29 0
-system.mem_ctrls0.rdQLenPdf::30 0
-system.mem_ctrls0.rdQLenPdf::31 0
-system.mem_ctrls0.wrQLenPdf::0 1
-system.mem_ctrls0.wrQLenPdf::1 1
-system.mem_ctrls0.wrQLenPdf::2 1
-system.mem_ctrls0.wrQLenPdf::3 1
-system.mem_ctrls0.wrQLenPdf::4 1
-system.mem_ctrls0.wrQLenPdf::5 1
-system.mem_ctrls0.wrQLenPdf::6 1
-system.mem_ctrls0.wrQLenPdf::7 1
-system.mem_ctrls0.wrQLenPdf::8 1
-system.mem_ctrls0.wrQLenPdf::9 1
-system.mem_ctrls0.wrQLenPdf::10 1
-system.mem_ctrls0.wrQLenPdf::11 1
-system.mem_ctrls0.wrQLenPdf::12 1
-system.mem_ctrls0.wrQLenPdf::13 1
-system.mem_ctrls0.wrQLenPdf::14 1
-system.mem_ctrls0.wrQLenPdf::15 3114
-system.mem_ctrls0.wrQLenPdf::16 3407
-system.mem_ctrls0.wrQLenPdf::17 3868
-system.mem_ctrls0.wrQLenPdf::18 3904
-system.mem_ctrls0.wrQLenPdf::19 4126
-system.mem_ctrls0.wrQLenPdf::20 3879
-system.mem_ctrls0.wrQLenPdf::21 4037
-system.mem_ctrls0.wrQLenPdf::22 3896
-system.mem_ctrls0.wrQLenPdf::23 4139
-system.mem_ctrls0.wrQLenPdf::24 3850
-system.mem_ctrls0.wrQLenPdf::25 3840
-system.mem_ctrls0.wrQLenPdf::26 3796
-system.mem_ctrls0.wrQLenPdf::27 3809
-system.mem_ctrls0.wrQLenPdf::28 3886
-system.mem_ctrls0.wrQLenPdf::29 3792
-system.mem_ctrls0.wrQLenPdf::30 3737
-system.mem_ctrls0.wrQLenPdf::31 3726
-system.mem_ctrls0.wrQLenPdf::32 3713
-system.mem_ctrls0.wrQLenPdf::33 234
-system.mem_ctrls0.wrQLenPdf::34 161
-system.mem_ctrls0.wrQLenPdf::35 115
-system.mem_ctrls0.wrQLenPdf::36 92
-system.mem_ctrls0.wrQLenPdf::37 68
-system.mem_ctrls0.wrQLenPdf::38 69
-system.mem_ctrls0.wrQLenPdf::39 70
-system.mem_ctrls0.wrQLenPdf::40 56
-system.mem_ctrls0.wrQLenPdf::41 54
-system.mem_ctrls0.wrQLenPdf::42 45
-system.mem_ctrls0.wrQLenPdf::43 54
-system.mem_ctrls0.wrQLenPdf::44 39
-system.mem_ctrls0.wrQLenPdf::45 37
-system.mem_ctrls0.wrQLenPdf::46 34
-system.mem_ctrls0.wrQLenPdf::47 46
-system.mem_ctrls0.wrQLenPdf::48 43
-system.mem_ctrls0.wrQLenPdf::49 35
-system.mem_ctrls0.wrQLenPdf::50 36
-system.mem_ctrls0.wrQLenPdf::51 11
-system.mem_ctrls0.wrQLenPdf::52 4
-system.mem_ctrls0.wrQLenPdf::53 2
-system.mem_ctrls0.wrQLenPdf::54 3
-system.mem_ctrls0.wrQLenPdf::55 1
-system.mem_ctrls0.wrQLenPdf::56 1
-system.mem_ctrls0.wrQLenPdf::57 1
-system.mem_ctrls0.wrQLenPdf::58 1
-system.mem_ctrls0.wrQLenPdf::59 0
-system.mem_ctrls0.wrQLenPdf::60 0
-system.mem_ctrls0.wrQLenPdf::61 0
-system.mem_ctrls0.wrQLenPdf::62 0
-system.mem_ctrls0.wrQLenPdf::63 0
-system.mem_ctrls0.bytesPerActivate::samples 52634
-system.mem_ctrls0.bytesPerActivate::mean 199.897557
-system.mem_ctrls0.bytesPerActivate::gmean 121.831244
-system.mem_ctrls0.bytesPerActivate::stdev 260.506759
-system.mem_ctrls0.bytesPerActivate::0-127 28874 54.86% 54.86%
-system.mem_ctrls0.bytesPerActivate::128-255 12469 23.69% 78.55%
-system.mem_ctrls0.bytesPerActivate::256-383 4077 7.75% 86.29%
-system.mem_ctrls0.bytesPerActivate::384-511 1631 3.10% 89.39%
-system.mem_ctrls0.bytesPerActivate::512-639 681 1.29% 90.69%
-system.mem_ctrls0.bytesPerActivate::640-767 800 1.52% 92.21%
-system.mem_ctrls0.bytesPerActivate::768-895 428 0.81% 93.02%
-system.mem_ctrls0.bytesPerActivate::896-1023 244 0.46% 93.48%
-system.mem_ctrls0.bytesPerActivate::1024-1151 3430 6.52% 100.00%
-system.mem_ctrls0.bytesPerActivate::total 52634
-system.mem_ctrls0.rdPerTurnAround::samples 3678
-system.mem_ctrls0.rdPerTurnAround::mean 25.713431
-system.mem_ctrls0.rdPerTurnAround::stdev 393.302284
-system.mem_ctrls0.rdPerTurnAround::0-1023 3676 99.95% 99.95%
-system.mem_ctrls0.rdPerTurnAround::1024-2047 1 0.03% 99.97%
-system.mem_ctrls0.rdPerTurnAround::23552-24575 1 0.03% 100.00%
-system.mem_ctrls0.rdPerTurnAround::total 3678
-system.mem_ctrls0.wrPerTurnAround::samples 3678
-system.mem_ctrls0.wrPerTurnAround::mean 18.983687
-system.mem_ctrls0.wrPerTurnAround::gmean 18.771121
-system.mem_ctrls0.wrPerTurnAround::stdev 3.420293
-system.mem_ctrls0.wrPerTurnAround::16-17 542 14.74% 14.74%
-system.mem_ctrls0.wrPerTurnAround::18-19 2260 61.45% 76.18%
-system.mem_ctrls0.wrPerTurnAround::20-21 371 10.09% 86.27%
-system.mem_ctrls0.wrPerTurnAround::22-23 328 8.92% 95.19%
-system.mem_ctrls0.wrPerTurnAround::24-25 103 2.80% 97.99%
-system.mem_ctrls0.wrPerTurnAround::26-27 9 0.24% 98.23%
-system.mem_ctrls0.wrPerTurnAround::28-29 5 0.14% 98.37%
-system.mem_ctrls0.wrPerTurnAround::30-31 7 0.19% 98.56%
-system.mem_ctrls0.wrPerTurnAround::32-33 9 0.24% 98.80%
-system.mem_ctrls0.wrPerTurnAround::34-35 7 0.19% 98.99%
-system.mem_ctrls0.wrPerTurnAround::36-37 3 0.08% 99.08%
-system.mem_ctrls0.wrPerTurnAround::38-39 4 0.11% 99.18%
-system.mem_ctrls0.wrPerTurnAround::40-41 5 0.14% 99.32%
-system.mem_ctrls0.wrPerTurnAround::42-43 3 0.08% 99.40%
-system.mem_ctrls0.wrPerTurnAround::44-45 15 0.41% 99.81%
-system.mem_ctrls0.wrPerTurnAround::46-47 2 0.05% 99.86%
-system.mem_ctrls0.wrPerTurnAround::48-49 2 0.05% 99.92%
-system.mem_ctrls0.wrPerTurnAround::50-51 2 0.05% 99.97%
-system.mem_ctrls0.wrPerTurnAround::68-69 1 0.03% 100.00%
-system.mem_ctrls0.wrPerTurnAround::total 3678
-system.mem_ctrls0.totQLat 3199266249
-system.mem_ctrls0.totMemAccLat 4972566249
-system.mem_ctrls0.totBusLat 472880000
-system.mem_ctrls0.avgQLat 33827.46
-system.mem_ctrls0.avgBusLat 5000.00
-system.mem_ctrls0.avgMemAccLat 52577.46
-system.mem_ctrls0.avgRdBW 2.09
-system.mem_ctrls0.avgWrBW 1.54
-system.mem_ctrls0.avgRdBWSys 2.10
-system.mem_ctrls0.avgWrBWSys 1.54
-system.mem_ctrls0.peakBW 12800.00
-system.mem_ctrls0.busUtil 0.03
-system.mem_ctrls0.busUtilRead 0.02
-system.mem_ctrls0.busUtilWrite 0.01
-system.mem_ctrls0.avgRdQLen 1.00
-system.mem_ctrls0.avgWrQLen 24.18
-system.mem_ctrls0.readRowHits 73849
-system.mem_ctrls0.writeRowHits 37914
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-system.cpu1.itb.walker.walkCompletionTime::8192-16383 60 7.29% 96.11%
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 30 3.65% 99.76%
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 1 0.12% 99.88%
-system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.12% 100.00%
-system.cpu1.itb.walker.walkCompletionTime::total 823
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-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.timer1.pio 20
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.kmi0.pio 78
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-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.uart2_fake.pio 16
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.uart3_fake.pio 16
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.sp810_fake.pio 76
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-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.ethernet.pio 592
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-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.uart.pio 12756
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.realview_io.pio 2
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-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.kmi0.pio 42
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.kmi1.pio 310
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-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.ide.pio 1184
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.realview.ethernet.pio 41676
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-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.timer0.pio 68
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.timer1.pio 40
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.kmi0.pio 63
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-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.uart3_fake.pio 32
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.sp810_fake.pio 152
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.watchdog_fake.pio 32
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-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.realview.ethernet.pio 1184
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-system.ruby.Directory_Controller.PUTX | 51734 50.13% 50.13% | 51466 49.87% 100.00%
-system.ruby.Directory_Controller.PUTX::total 103200
-system.ruby.Directory_Controller.Unblock | 16150 50.82% 50.82% | 15627 49.18% 100.00%
-system.ruby.Directory_Controller.Unblock::total 31777
-system.ruby.Directory_Controller.Last_Unblock | 1058 51.71% 51.71% | 988 48.29% 100.00%
-system.ruby.Directory_Controller.Last_Unblock::total 2046
-system.ruby.Directory_Controller.Exclusive_Unblock | 95685 50.08% 50.08% | 95382 49.92% 100.00%
-system.ruby.Directory_Controller.Exclusive_Unblock::total 191067
-system.ruby.Directory_Controller.Dirty_Writeback | 51734 50.13% 50.13% | 51466 49.87% 100.00%
-system.ruby.Directory_Controller.Dirty_Writeback::total 103200
-system.ruby.Directory_Controller.Memory_Data | 94787 50.24% 50.24% | 93892 49.76% 100.00%
-system.ruby.Directory_Controller.Memory_Data::total 188679
-system.ruby.Directory_Controller.Memory_Ack | 69846 50.10% 50.10% | 69578 49.90% 100.00%
-system.ruby.Directory_Controller.Memory_Ack::total 139424
-system.ruby.Directory_Controller.DMA_READ | 214 90.30% 90.30% | 23 9.70% 100.00%
-system.ruby.Directory_Controller.DMA_READ::total 237
-system.ruby.Directory_Controller.DMA_WRITE | 18112 50.00% 50.00% | 18112 50.00% 100.00%
-system.ruby.Directory_Controller.DMA_WRITE::total 36224
-system.ruby.Directory_Controller.DMA_ACK | 207 93.24% 93.24% | 15 6.76% 100.00%
-system.ruby.Directory_Controller.DMA_ACK::total 222
-system.ruby.Directory_Controller.Data | 2222 50.12% 50.12% | 2211 49.88% 100.00%
-system.ruby.Directory_Controller.Data::total 4433
-system.ruby.Directory_Controller.I.GETX | 73278 49.95% 49.95% | 73429 50.05% 100.00%
-system.ruby.Directory_Controller.I.GETX::total 146707
-system.ruby.Directory_Controller.I.GETS | 16150 50.82% 50.82% | 15627 49.18% 100.00%
-system.ruby.Directory_Controller.I.GETS::total 31777
-system.ruby.Directory_Controller.I.Memory_Ack | 51768 50.13% 50.13% | 51496 49.87% 100.00%
-system.ruby.Directory_Controller.I.Memory_Ack::total 103264
-system.ruby.Directory_Controller.I.DMA_READ | 6 46.15% 46.15% | 7 53.85% 100.00%
-system.ruby.Directory_Controller.I.DMA_READ::total 13
-system.ruby.Directory_Controller.I.DMA_WRITE | 15890 50.00% 50.00% | 15888 50.00% 100.00%
-system.ruby.Directory_Controller.I.DMA_WRITE::total 31778
-system.ruby.Directory_Controller.S.GETX | 4295 52.79% 52.79% | 3841 47.21% 100.00%
-system.ruby.Directory_Controller.S.GETX::total 8136
-system.ruby.Directory_Controller.S.GETS | 1058 51.71% 51.71% | 988 48.29% 100.00%
-system.ruby.Directory_Controller.S.GETS::total 2046
-system.ruby.Directory_Controller.S.DMA_READ | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.Directory_Controller.S.DMA_READ::total 2
-system.ruby.Directory_Controller.S.DMA_WRITE | 0 0.00% 0.00% | 13 100.00% 100.00%
-system.ruby.Directory_Controller.S.DMA_WRITE::total 13
-system.ruby.Directory_Controller.M.PUTX | 51734 50.13% 50.13% | 51466 49.87% 100.00%
-system.ruby.Directory_Controller.M.PUTX::total 103200
-system.ruby.Directory_Controller.M.DMA_READ | 207 93.24% 93.24% | 15 6.76% 100.00%
-system.ruby.Directory_Controller.M.DMA_READ::total 222
-system.ruby.Directory_Controller.M.DMA_WRITE | 2222 50.12% 50.12% | 2211 49.88% 100.00%
-system.ruby.Directory_Controller.M.DMA_WRITE::total 4433
-system.ruby.Directory_Controller.IS.Unblock | 16150 50.82% 50.82% | 15627 49.18% 100.00%
-system.ruby.Directory_Controller.IS.Unblock::total 31777
-system.ruby.Directory_Controller.IS.Memory_Data | 16150 50.82% 50.82% | 15627 49.18% 100.00%
-system.ruby.Directory_Controller.IS.Memory_Data::total 31777
-system.ruby.Directory_Controller.SS.Last_Unblock | 1058 51.71% 51.71% | 988 48.29% 100.00%
-system.ruby.Directory_Controller.SS.Last_Unblock::total 2046
-system.ruby.Directory_Controller.SS.Memory_Data | 1058 51.71% 51.71% | 988 48.29% 100.00%
-system.ruby.Directory_Controller.SS.Memory_Data::total 2046
-system.ruby.Directory_Controller.MM.Exclusive_Unblock | 77573 50.10% 50.10% | 77270 49.90% 100.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 154843
-system.ruby.Directory_Controller.MM.Memory_Data | 77573 50.10% 50.10% | 77270 49.90% 100.00%
-system.ruby.Directory_Controller.MM.Memory_Data::total 154843
-system.ruby.Directory_Controller.MI.Dirty_Writeback | 51734 50.13% 50.13% | 51466 49.87% 100.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback::total 103200
-system.ruby.Directory_Controller.XI_M.Memory_Data | 6 46.15% 46.15% | 7 53.85% 100.00%
-system.ruby.Directory_Controller.XI_M.Memory_Data::total 13
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 18112 50.00% 50.00% | 18112 50.00% 100.00%
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 36224
-system.ruby.Directory_Controller.XI_U.Memory_Ack | 18078 49.99% 49.99% | 18082 50.01% 100.00%
-system.ruby.Directory_Controller.XI_U.Memory_Ack::total 36160
-system.ruby.Directory_Controller.OI_D.Data | 2222 50.12% 50.12% | 2211 49.88% 100.00%
-system.ruby.Directory_Controller.OI_D.Data::total 4433
-system.ruby.Directory_Controller.MD.DMA_ACK | 207 93.24% 93.24% | 15 6.76% 100.00%
-system.ruby.Directory_Controller.MD.DMA_ACK::total 222
-system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 357 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 357
-system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1082306 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.WriteRequest::total 1082306
-system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 237
-system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.DMA_Ack::total 36224
-system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Inv_Ack::total 13
-system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.All_Acks::total 36224
-system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 237
-system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.WriteRequest::total 36224
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 120
-system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 237
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1046082 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 1046082
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 36224
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 13
-system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 36224
-system.ruby.L1Cache_Controller.Load | 15750482 62.13% 62.13% | 9601529 37.87% 100.00%
-system.ruby.L1Cache_Controller.Load::total 25352011
-system.ruby.L1Cache_Controller.Ifetch | 77708274 64.55% 64.55% | 42681625 35.45% 100.00%
-system.ruby.L1Cache_Controller.Ifetch::total 120389899
-system.ruby.L1Cache_Controller.Store | 14489283 69.01% 69.01% | 6507230 30.99% 100.00%
-system.ruby.L1Cache_Controller.Store::total 20996513
-system.ruby.L1Cache_Controller.L1_Replacement | 1909267 71.36% 71.36% | 766226 28.64% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 2675493
-system.ruby.L1Cache_Controller.Own_GETX | 103 39.16% 39.16% | 160 60.84% 100.00%
-system.ruby.L1Cache_Controller.Own_GETX::total 263
-system.ruby.L1Cache_Controller.Fwd_GETX | 24384 55.63% 55.63% | 19449 44.37% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 43833
-system.ruby.L1Cache_Controller.Fwd_GETS | 54169 49.45% 49.45% | 55369 50.55% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 109538
-system.ruby.L1Cache_Controller.Fwd_DMA | 212 95.50% 95.50% | 10 4.50% 100.00%
-system.ruby.L1Cache_Controller.Fwd_DMA::total 222
-system.ruby.L1Cache_Controller.Inv | 225 40.61% 40.61% | 329 59.39% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 554
-system.ruby.L1Cache_Controller.Ack | 19744 44.67% 44.67% | 24458 55.33% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 44202
-system.ruby.L1Cache_Controller.Data | 1376641 68.96% 68.96% | 619533 31.04% 100.00%
-system.ruby.L1Cache_Controller.Data::total 1996174
-system.ruby.L1Cache_Controller.Exclusive_Data | 569619 75.54% 75.54% | 184462 24.46% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 754081
-system.ruby.L1Cache_Controller.Writeback_Ack | 1344380 68.92% 68.92% | 606151 31.08% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 1950531
-system.ruby.L1Cache_Controller.Writeback_Ack_Data | 523751 79.38% 79.38% | 136083 20.62% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 659834
-system.ruby.L1Cache_Controller.Writeback_Nack | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total 2
-system.ruby.L1Cache_Controller.All_acks | 274290 79.48% 79.48% | 70836 20.52% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 345126
-system.ruby.L1Cache_Controller.Use_Timeout | 569722 75.53% 75.53% | 184622 24.47% 100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total 754344
-system.ruby.L1Cache_Controller.I.Load | 514985 74.87% 74.87% | 172889 25.13% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 687874
-system.ruby.L1Cache_Controller.I.Ifetch | 1157088 67.37% 67.37% | 560430 32.63% 100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total 1717518
-system.ruby.L1Cache_Controller.I.Store | 266266 80.42% 80.42% | 64827 19.58% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 331093
-system.ruby.L1Cache_Controller.I.L1_Replacement | 38771 65.97% 65.97% | 19998 34.03% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 58769
-system.ruby.L1Cache_Controller.S.Load | 2866458 38.59% 38.59% | 4561263 61.41% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 7427721
-system.ruby.L1Cache_Controller.S.Ifetch | 76171671 64.50% 64.50% | 41920338 35.50% 100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total 118092009
-system.ruby.L1Cache_Controller.S.Store | 7920 57.57% 57.57% | 5837 42.43% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 13757
-system.ruby.L1Cache_Controller.S.L1_Replacement | 1367798 69.06% 69.06% | 612731 30.94% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 1980529
-system.ruby.L1Cache_Controller.S.Fwd_GETS | 133 37.46% 37.46% | 222 62.54% 100.00%
-system.ruby.L1Cache_Controller.S.Fwd_GETS::total 355
-system.ruby.L1Cache_Controller.S.Inv | 224 40.58% 40.58% | 328 59.42% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 552
-system.ruby.L1Cache_Controller.O.Load | 48917 49.62% 49.62% | 49676 50.38% 100.00%
-system.ruby.L1Cache_Controller.O.Load::total 98593
-system.ruby.L1Cache_Controller.O.Ifetch | 14060 46.51% 46.51% | 16170 53.49% 100.00%
-system.ruby.L1Cache_Controller.O.Ifetch::total 30230
-system.ruby.L1Cache_Controller.O.Store | 104 37.68% 37.68% | 172 62.32% 100.00%
-system.ruby.L1Cache_Controller.O.Store::total 276
-system.ruby.L1Cache_Controller.O.L1_Replacement | 2740 40.21% 40.21% | 4075 59.79% 100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total 6815
-system.ruby.L1Cache_Controller.O.Fwd_GETX | 4291 46.72% 46.72% | 4893 53.28% 100.00%
-system.ruby.L1Cache_Controller.O.Fwd_GETX::total 9184
-system.ruby.L1Cache_Controller.O.Fwd_GETS | 1552 13.87% 13.87% | 9638 86.13% 100.00%
-system.ruby.L1Cache_Controller.O.Fwd_GETS::total 11190
-system.ruby.L1Cache_Controller.M.Load | 2422898 80.34% 80.34% | 592917 19.66% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 3015815
-system.ruby.L1Cache_Controller.M.Ifetch | 187929 63.25% 63.25% | 109203 36.75% 100.00%
-system.ruby.L1Cache_Controller.M.Ifetch::total 297132
-system.ruby.L1Cache_Controller.M.Store | 79674 63.83% 63.83% | 45141 36.17% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 124815
-system.ruby.L1Cache_Controller.M.L1_Replacement | 107902 75.06% 75.06% | 35849 24.94% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 143751
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 352 21.27% 21.27% | 1303 78.73% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 1655
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 7135 43.68% 43.68% | 9201 56.32% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 16336
-system.ruby.L1Cache_Controller.M_W.Load | 158966 79.18% 79.18% | 41801 20.82% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 200767
-system.ruby.L1Cache_Controller.M_W.Ifetch | 30678 60.26% 60.26% | 20231 39.74% 100.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch::total 50909
-system.ruby.L1Cache_Controller.M_W.Store | 100281 81.84% 81.84% | 22250 18.16% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 122531
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 2364 37.18% 37.18% | 3994 62.82% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 6358
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 10 34.48% 34.48% | 19 65.52% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 29
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 210 47.84% 47.84% | 229 52.16% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 439
-system.ruby.L1Cache_Controller.M_W.Use_Timeout | 195151 68.07% 68.07% | 91536 31.93% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 286687
-system.ruby.L1Cache_Controller.MM.Load | 9556522 69.83% 69.83% | 4129486 30.17% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 13686008
-system.ruby.L1Cache_Controller.MM.Store | 11405889 65.83% 65.83% | 5919284 34.17% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 17325173
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 389692 81.31% 81.31% | 89579 18.69% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 479271
-system.ruby.L1Cache_Controller.MM.Fwd_GETX | 19455 59.75% 59.75% | 13106 40.25% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 32561
-system.ruby.L1Cache_Controller.MM.Fwd_GETS | 44877 55.89% 55.89% | 35420 44.11% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 80297
-system.ruby.L1Cache_Controller.MM.Fwd_DMA | 212 95.50% 95.50% | 10 4.50% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_DMA::total 222
-system.ruby.L1Cache_Controller.MM_W.Load | 45128 89.53% 89.53% | 5280 10.47% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 50408
-system.ruby.L1Cache_Controller.MM_W.Store | 2629131 85.39% 85.39% | 449719 14.61% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 3078850
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 275 70.33% 70.33% | 116 29.67% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 391
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 241 27.64% 27.64% | 631 72.36% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 872
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 374571 80.10% 80.10% | 93086 19.90% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 467657
-system.ruby.L1Cache_Controller.IM.Ack | 14493 42.21% 42.21% | 19839 57.79% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 34332
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 266268 80.42% 80.42% | 64840 19.58% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 331108
-system.ruby.L1Cache_Controller.SM.Inv | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Inv::total 2
-system.ruby.L1Cache_Controller.SM.Ack | 4819 53.23% 53.23% | 4234 46.77% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 9053
-system.ruby.L1Cache_Controller.SM.Exclusive_Data | 7919 57.57% 57.57% | 5836 42.43% 100.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 13755
-system.ruby.L1Cache_Controller.OM.Own_GETX | 103 39.16% 39.16% | 160 60.84% 100.00%
-system.ruby.L1Cache_Controller.OM.Own_GETX::total 263
-system.ruby.L1Cache_Controller.OM.Fwd_GETX | 1 7.69% 7.69% | 12 92.31% 100.00%
-system.ruby.L1Cache_Controller.OM.Fwd_GETX::total 13
-system.ruby.L1Cache_Controller.OM.Ack | 432 52.88% 52.88% | 385 47.12% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 817
-system.ruby.L1Cache_Controller.OM.All_acks | 274290 79.48% 79.48% | 70836 20.52% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total 345126
-system.ruby.L1Cache_Controller.IS.Data | 1376641 68.96% 68.96% | 619533 31.04% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 1996174
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 295432 72.19% 72.19% | 113786 27.81% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 409218
-system.ruby.L1Cache_Controller.SI.Load | 135958 74.45% 74.45% | 46670 25.55% 100.00%
-system.ruby.L1Cache_Controller.SI.Load::total 182628
-system.ruby.L1Cache_Controller.SI.Ifetch | 146215 73.13% 73.13% | 53735 26.87% 100.00%
-system.ruby.L1Cache_Controller.SI.Ifetch::total 199950
-system.ruby.L1Cache_Controller.SI.Store | 18 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SI.Store::total 18
-system.ruby.L1Cache_Controller.SI.Writeback_Ack | 1344380 68.92% 68.92% | 606151 31.08% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 1950531
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 23417 78.06% 78.06% | 6580 21.94% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 29997
-system.ruby.L1Cache_Controller.OI.Load | 184 12.23% 12.23% | 1320 87.77% 100.00%
-system.ruby.L1Cache_Controller.OI.Load::total 1504
-system.ruby.L1Cache_Controller.OI.Ifetch | 47 40.87% 40.87% | 68 59.13% 100.00%
-system.ruby.L1Cache_Controller.OI.Ifetch::total 115
-system.ruby.L1Cache_Controller.OI.Fwd_GETS | 8 44.44% 44.44% | 10 55.56% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 18
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 2753 40.21% 40.21% | 4093 59.79% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 6846
-system.ruby.L1Cache_Controller.OI.Writeback_Nack | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 2
-system.ruby.L1Cache_Controller.MI.Load | 466 67.24% 67.24% | 227 32.76% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 693
-system.ruby.L1Cache_Controller.MI.Ifetch | 586 28.78% 28.78% | 1450 71.22% 100.00%
-system.ruby.L1Cache_Controller.MI.Ifetch::total 2036
-system.ruby.L1Cache_Controller.MI.Fwd_GETS | 13 41.94% 41.94% | 18 58.06% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 31
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 497581 79.87% 79.87% | 125410 20.13% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 622991
-system.ruby.L2Cache_Controller.L1_GETS 2407512 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 345217 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTO 6889 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 623101 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 1475996 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS 505327 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_GETX 4433 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_DMA 222 0.00% 0.00%
-system.ruby.L2Cache_Controller.Inv 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 154843 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 188666 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 29997 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 629837 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 103200 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 3946704 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 754344 0.00% 0.00%
-system.ruby.L2Cache_Controller.DmaAck 222 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 112649 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 33820 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 148628 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS 355 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 3845 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 29644 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS 353 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS 96664 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX 34188 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 622991 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_GETX 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_DMA 222 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETS 11208 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETX 167 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO 3596 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETX 9293 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 3221 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 29 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 15016 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 1429468 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 2043 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Inv 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 9429 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETS 24410 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETX 610 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 2575 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS 24172 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETS 480543 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 327 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 1428342 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS 480427 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 20 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 328921 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 146025 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_GETX 4405 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 103200 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 3596 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.Unblock 15016 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 30 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 3250 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L1_GETS 378 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L1_PUTS 368 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.Unblock 480427 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 353 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 29644 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 658 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 1428341 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETS 21 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.Unblock 2575 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.Unblock 24172 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS 60 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETX 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 622991 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.Unblock 355 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 35 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Unblock 11208 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 610 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 117 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 41 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 61 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Unblock 16367 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 114652 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_GETS 53 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_GETX 45 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 9293 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETS 335 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 33823 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 33823 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 150671 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 4172 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 154843 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 154843 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 146025 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 449 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 1429467 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETS 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 328921 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 17 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.Unblock 24410 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 372 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L1_PUTS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.Unblock 480543 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 103200 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXD.DmaAck 222 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.877637
-sim_ticks 2877636763500
-final_tick 2877636763500
-sim_freq 1000000000000
-host_inst_rate 167948
-host_op_rate 202496
-host_tick_rate 4296410981
-host_mem_usage 819776
-host_seconds 669.78
-sim_insts 112487545
-sim_ops 135626969
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 2877636763500
-system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 5371712
-system.mem_ctrls0.bytes_read::total 5371712
-system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 3874880
-system.mem_ctrls0.bytes_written::total 3874880
-system.mem_ctrls0.num_reads::ruby.dir_cntrl0 83933
-system.mem_ctrls0.num_reads::total 83933
-system.mem_ctrls0.num_writes::ruby.dir_cntrl0 60545
-system.mem_ctrls0.num_writes::total 60545
-system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1866710
-system.mem_ctrls0.bw_read::total 1866710
-system.mem_ctrls0.bw_write::ruby.dir_cntrl0 1346549
-system.mem_ctrls0.bw_write::total 1346549
-system.mem_ctrls0.bw_total::ruby.dir_cntrl0 3213259
-system.mem_ctrls0.bw_total::total 3213259
-system.mem_ctrls0.readReqs 83933
-system.mem_ctrls0.writeReqs 60545
-system.mem_ctrls0.readBursts 83933
-system.mem_ctrls0.writeBursts 60545
-system.mem_ctrls0.bytesReadDRAM 5358464
-system.mem_ctrls0.bytesReadWrQ 13248
-system.mem_ctrls0.bytesWritten 3873728
-system.mem_ctrls0.bytesReadSys 5371712
-system.mem_ctrls0.bytesWrittenSys 3874880
-system.mem_ctrls0.servicedByWrQ 207
-system.mem_ctrls0.mergedWrBursts 0
-system.mem_ctrls0.neitherReadNorWriteReqs 0
-system.mem_ctrls0.perBankRdBursts::0 5395
-system.mem_ctrls0.perBankRdBursts::1 5846
-system.mem_ctrls0.perBankRdBursts::2 5271
-system.mem_ctrls0.perBankRdBursts::3 5511
-system.mem_ctrls0.perBankRdBursts::4 4812
-system.mem_ctrls0.perBankRdBursts::5 4358
-system.mem_ctrls0.perBankRdBursts::6 5016
-system.mem_ctrls0.perBankRdBursts::7 5037
-system.mem_ctrls0.perBankRdBursts::8 4968
-system.mem_ctrls0.perBankRdBursts::9 5212
-system.mem_ctrls0.perBankRdBursts::10 5289
-system.mem_ctrls0.perBankRdBursts::11 5876
-system.mem_ctrls0.perBankRdBursts::12 5376
-system.mem_ctrls0.perBankRdBursts::13 5195
-system.mem_ctrls0.perBankRdBursts::14 5352
-system.mem_ctrls0.perBankRdBursts::15 5212
-system.mem_ctrls0.perBankWrBursts::0 3724
-system.mem_ctrls0.perBankWrBursts::1 4296
-system.mem_ctrls0.perBankWrBursts::2 3785
-system.mem_ctrls0.perBankWrBursts::3 3788
-system.mem_ctrls0.perBankWrBursts::4 3579
-system.mem_ctrls0.perBankWrBursts::5 3191
-system.mem_ctrls0.perBankWrBursts::6 3631
-system.mem_ctrls0.perBankWrBursts::7 3790
-system.mem_ctrls0.perBankWrBursts::8 3772
-system.mem_ctrls0.perBankWrBursts::9 4024
-system.mem_ctrls0.perBankWrBursts::10 3639
-system.mem_ctrls0.perBankWrBursts::11 4212
-system.mem_ctrls0.perBankWrBursts::12 3867
-system.mem_ctrls0.perBankWrBursts::13 3819
-system.mem_ctrls0.perBankWrBursts::14 3821
-system.mem_ctrls0.perBankWrBursts::15 3589
-system.mem_ctrls0.numRdRetry 0
-system.mem_ctrls0.numWrRetry 0
-system.mem_ctrls0.totGap 2877635963000
-system.mem_ctrls0.readPktSize::0 0
-system.mem_ctrls0.readPktSize::1 0
-system.mem_ctrls0.readPktSize::2 0
-system.mem_ctrls0.readPktSize::3 0
-system.mem_ctrls0.readPktSize::4 0
-system.mem_ctrls0.readPktSize::5 0
-system.mem_ctrls0.readPktSize::6 83933
-system.mem_ctrls0.writePktSize::0 0
-system.mem_ctrls0.writePktSize::1 0
-system.mem_ctrls0.writePktSize::2 0
-system.mem_ctrls0.writePktSize::3 0
-system.mem_ctrls0.writePktSize::4 0
-system.mem_ctrls0.writePktSize::5 0
-system.mem_ctrls0.writePktSize::6 60545
-system.mem_ctrls0.rdQLenPdf::0 83726
-system.mem_ctrls0.rdQLenPdf::1 0
-system.mem_ctrls0.rdQLenPdf::2 0
-system.mem_ctrls0.rdQLenPdf::3 0
-system.mem_ctrls0.rdQLenPdf::4 0
-system.mem_ctrls0.rdQLenPdf::5 0
-system.mem_ctrls0.rdQLenPdf::6 0
-system.mem_ctrls0.rdQLenPdf::7 0
-system.mem_ctrls0.rdQLenPdf::8 0
-system.mem_ctrls0.rdQLenPdf::9 0
-system.mem_ctrls0.rdQLenPdf::10 0
-system.mem_ctrls0.rdQLenPdf::11 0
-system.mem_ctrls0.rdQLenPdf::12 0
-system.mem_ctrls0.rdQLenPdf::13 0
-system.mem_ctrls0.rdQLenPdf::14 0
-system.mem_ctrls0.rdQLenPdf::15 0
-system.mem_ctrls0.rdQLenPdf::16 0
-system.mem_ctrls0.rdQLenPdf::17 0
-system.mem_ctrls0.rdQLenPdf::18 0
-system.mem_ctrls0.rdQLenPdf::19 0
-system.mem_ctrls0.rdQLenPdf::20 0
-system.mem_ctrls0.rdQLenPdf::21 0
-system.mem_ctrls0.rdQLenPdf::22 0
-system.mem_ctrls0.rdQLenPdf::23 0
-system.mem_ctrls0.rdQLenPdf::24 0
-system.mem_ctrls0.rdQLenPdf::25 0
-system.mem_ctrls0.rdQLenPdf::26 0
-system.mem_ctrls0.rdQLenPdf::27 0
-system.mem_ctrls0.rdQLenPdf::28 0
-system.mem_ctrls0.rdQLenPdf::29 0
-system.mem_ctrls0.rdQLenPdf::30 0
-system.mem_ctrls0.rdQLenPdf::31 0
-system.mem_ctrls0.wrQLenPdf::0 1
-system.mem_ctrls0.wrQLenPdf::1 1
-system.mem_ctrls0.wrQLenPdf::2 1
-system.mem_ctrls0.wrQLenPdf::3 1
-system.mem_ctrls0.wrQLenPdf::4 1
-system.mem_ctrls0.wrQLenPdf::5 1
-system.mem_ctrls0.wrQLenPdf::6 1
-system.mem_ctrls0.wrQLenPdf::7 1
-system.mem_ctrls0.wrQLenPdf::8 1
-system.mem_ctrls0.wrQLenPdf::9 1
-system.mem_ctrls0.wrQLenPdf::10 1
-system.mem_ctrls0.wrQLenPdf::11 1
-system.mem_ctrls0.wrQLenPdf::12 1
-system.mem_ctrls0.wrQLenPdf::13 1
-system.mem_ctrls0.wrQLenPdf::14 1
-system.mem_ctrls0.wrQLenPdf::15 2729
-system.mem_ctrls0.wrQLenPdf::16 2985
-system.mem_ctrls0.wrQLenPdf::17 3350
-system.mem_ctrls0.wrQLenPdf::18 3401
-system.mem_ctrls0.wrQLenPdf::19 3631
-system.mem_ctrls0.wrQLenPdf::20 3341
-system.mem_ctrls0.wrQLenPdf::21 3506
-system.mem_ctrls0.wrQLenPdf::22 3351
-system.mem_ctrls0.wrQLenPdf::23 3585
-system.mem_ctrls0.wrQLenPdf::24 3320
-system.mem_ctrls0.wrQLenPdf::25 3302
-system.mem_ctrls0.wrQLenPdf::26 3261
-system.mem_ctrls0.wrQLenPdf::27 3279
-system.mem_ctrls0.wrQLenPdf::28 3360
-system.mem_ctrls0.wrQLenPdf::29 3257
-system.mem_ctrls0.wrQLenPdf::30 3218
-system.mem_ctrls0.wrQLenPdf::31 3196
-system.mem_ctrls0.wrQLenPdf::32 3192
-system.mem_ctrls0.wrQLenPdf::33 274
-system.mem_ctrls0.wrQLenPdf::34 150
-system.mem_ctrls0.wrQLenPdf::35 99
-system.mem_ctrls0.wrQLenPdf::36 78
-system.mem_ctrls0.wrQLenPdf::37 69
-system.mem_ctrls0.wrQLenPdf::38 70
-system.mem_ctrls0.wrQLenPdf::39 63
-system.mem_ctrls0.wrQLenPdf::40 51
-system.mem_ctrls0.wrQLenPdf::41 44
-system.mem_ctrls0.wrQLenPdf::42 46
-system.mem_ctrls0.wrQLenPdf::43 54
-system.mem_ctrls0.wrQLenPdf::44 42
-system.mem_ctrls0.wrQLenPdf::45 34
-system.mem_ctrls0.wrQLenPdf::46 34
-system.mem_ctrls0.wrQLenPdf::47 40
-system.mem_ctrls0.wrQLenPdf::48 42
-system.mem_ctrls0.wrQLenPdf::49 32
-system.mem_ctrls0.wrQLenPdf::50 27
-system.mem_ctrls0.wrQLenPdf::51 9
-system.mem_ctrls0.wrQLenPdf::52 1
-system.mem_ctrls0.wrQLenPdf::53 1
-system.mem_ctrls0.wrQLenPdf::54 1
-system.mem_ctrls0.wrQLenPdf::55 1
-system.mem_ctrls0.wrQLenPdf::56 1
-system.mem_ctrls0.wrQLenPdf::57 1
-system.mem_ctrls0.wrQLenPdf::58 1
-system.mem_ctrls0.wrQLenPdf::59 1
-system.mem_ctrls0.wrQLenPdf::60 0
-system.mem_ctrls0.wrQLenPdf::61 0
-system.mem_ctrls0.wrQLenPdf::62 0
-system.mem_ctrls0.wrQLenPdf::63 0
-system.mem_ctrls0.bytesPerActivate::samples 42257
-system.mem_ctrls0.bytesPerActivate::mean 218.475708
-system.mem_ctrls0.bytesPerActivate::gmean 130.171565
-system.mem_ctrls0.bytesPerActivate::stdev 277.776104
-system.mem_ctrls0.bytesPerActivate::0-127 21896 51.82% 51.82%
-system.mem_ctrls0.bytesPerActivate::128-255 10153 24.03% 75.84%
-system.mem_ctrls0.bytesPerActivate::256-383 3452 8.17% 84.01%
-system.mem_ctrls0.bytesPerActivate::384-511 1380 3.27% 87.28%
-system.mem_ctrls0.bytesPerActivate::512-639 704 1.67% 88.94%
-system.mem_ctrls0.bytesPerActivate::640-767 785 1.86% 90.80%
-system.mem_ctrls0.bytesPerActivate::768-895 411 0.97% 91.77%
-system.mem_ctrls0.bytesPerActivate::896-1023 250 0.59% 92.37%
-system.mem_ctrls0.bytesPerActivate::1024-1151 3226 7.63% 100.00%
-system.mem_ctrls0.bytesPerActivate::total 42257
-system.mem_ctrls0.rdPerTurnAround::samples 3152
-system.mem_ctrls0.rdPerTurnAround::mean 26.561231
-system.mem_ctrls0.rdPerTurnAround::stdev 419.368738
-system.mem_ctrls0.rdPerTurnAround::0-1023 3150 99.94% 99.94%
-system.mem_ctrls0.rdPerTurnAround::1024-2047 1 0.03% 99.97%
-system.mem_ctrls0.rdPerTurnAround::22528-23551 1 0.03% 100.00%
-system.mem_ctrls0.rdPerTurnAround::total 3152
-system.mem_ctrls0.wrPerTurnAround::samples 3152
-system.mem_ctrls0.wrPerTurnAround::mean 19.202728
-system.mem_ctrls0.wrPerTurnAround::gmean 18.961901
-system.mem_ctrls0.wrPerTurnAround::stdev 3.685315
-system.mem_ctrls0.wrPerTurnAround::16 344 10.91% 10.91%
-system.mem_ctrls0.wrPerTurnAround::17 56 1.78% 12.69%
-system.mem_ctrls0.wrPerTurnAround::18 1604 50.89% 63.58%
-system.mem_ctrls0.wrPerTurnAround::19 304 9.64% 73.22%
-system.mem_ctrls0.wrPerTurnAround::20 280 8.88% 82.11%
-system.mem_ctrls0.wrPerTurnAround::21 75 2.38% 84.49%
-system.mem_ctrls0.wrPerTurnAround::22 264 8.38% 92.86%
-system.mem_ctrls0.wrPerTurnAround::23 55 1.74% 94.61%
-system.mem_ctrls0.wrPerTurnAround::24 18 0.57% 95.18%
-system.mem_ctrls0.wrPerTurnAround::25 76 2.41% 97.59%
-system.mem_ctrls0.wrPerTurnAround::26 9 0.29% 97.87%
-system.mem_ctrls0.wrPerTurnAround::27 5 0.16% 98.03%
-system.mem_ctrls0.wrPerTurnAround::28 1 0.03% 98.06%
-system.mem_ctrls0.wrPerTurnAround::29 2 0.06% 98.13%
-system.mem_ctrls0.wrPerTurnAround::30 1 0.03% 98.16%
-system.mem_ctrls0.wrPerTurnAround::31 4 0.13% 98.29%
-system.mem_ctrls0.wrPerTurnAround::32 6 0.19% 98.48%
-system.mem_ctrls0.wrPerTurnAround::33 1 0.03% 98.51%
-system.mem_ctrls0.wrPerTurnAround::34 1 0.03% 98.54%
-system.mem_ctrls0.wrPerTurnAround::35 2 0.06% 98.60%
-system.mem_ctrls0.wrPerTurnAround::36 6 0.19% 98.79%
-system.mem_ctrls0.wrPerTurnAround::37 3 0.10% 98.89%
-system.mem_ctrls0.wrPerTurnAround::38 6 0.19% 99.08%
-system.mem_ctrls0.wrPerTurnAround::39 1 0.03% 99.11%
-system.mem_ctrls0.wrPerTurnAround::41 1 0.03% 99.14%
-system.mem_ctrls0.wrPerTurnAround::42 2 0.06% 99.21%
-system.mem_ctrls0.wrPerTurnAround::43 1 0.03% 99.24%
-system.mem_ctrls0.wrPerTurnAround::44 4 0.13% 99.37%
-system.mem_ctrls0.wrPerTurnAround::45 2 0.06% 99.43%
-system.mem_ctrls0.wrPerTurnAround::46 3 0.10% 99.52%
-system.mem_ctrls0.wrPerTurnAround::47 5 0.16% 99.68%
-system.mem_ctrls0.wrPerTurnAround::48 5 0.16% 99.84%
-system.mem_ctrls0.wrPerTurnAround::50 1 0.03% 99.87%
-system.mem_ctrls0.wrPerTurnAround::51 1 0.03% 99.90%
-system.mem_ctrls0.wrPerTurnAround::52 1 0.03% 99.94%
-system.mem_ctrls0.wrPerTurnAround::55 1 0.03% 99.97%
-system.mem_ctrls0.wrPerTurnAround::56 1 0.03% 100.00%
-system.mem_ctrls0.wrPerTurnAround::total 3152
-system.mem_ctrls0.totQLat 3018743999
-system.mem_ctrls0.totMemAccLat 4588606499
-system.mem_ctrls0.totBusLat 418630000
-system.mem_ctrls0.avgQLat 36055.04
-system.mem_ctrls0.avgBusLat 5000.00
-system.mem_ctrls0.avgMemAccLat 54805.04
-system.mem_ctrls0.avgRdBW 1.86
-system.mem_ctrls0.avgWrBW 1.35
-system.mem_ctrls0.avgRdBWSys 1.87
-system.mem_ctrls0.avgWrBWSys 1.35
-system.mem_ctrls0.peakBW 12800.00
-system.mem_ctrls0.busUtil 0.03
-system.mem_ctrls0.busUtilRead 0.01
-system.mem_ctrls0.busUtilWrite 0.01
-system.mem_ctrls0.avgRdQLen 1.00
-system.mem_ctrls0.avgWrQLen 21.69
-system.mem_ctrls0.readRowHits 66033
-system.mem_ctrls0.writeRowHits 35962
-system.mem_ctrls0.readRowHitRate 78.87
-system.mem_ctrls0.writeRowHitRate 59.40
-system.mem_ctrls0.avgGap 19917468.15
-system.mem_ctrls0.pageHitRate 70.70
-system.mem_ctrls0_0.actEnergy 148012200
-system.mem_ctrls0_0.preEnergy 78670350
-system.mem_ctrls0_0.readEnergy 294496440
-system.mem_ctrls0_0.writeEnergy 155472480
-system.mem_ctrls0_0.refreshEnergy 6512110800.000002
-system.mem_ctrls0_0.actBackEnergy 4791910770
-system.mem_ctrls0_0.preBackEnergy 395576640
-system.mem_ctrls0_0.actPowerDownEnergy 12051398850
-system.mem_ctrls0_0.prePowerDownEnergy 9740887200
-system.mem_ctrls0_0.selfRefreshEnergy 676892791275
-system.mem_ctrls0_0.totalEnergy 711064155915
-system.mem_ctrls0_0.averagePower 247.100039
-system.mem_ctrls0_0.totalIdleTime 2865330125500
-system.mem_ctrls0_0.memoryStateTime::IDLE 778390250
-system.mem_ctrls0_0.memoryStateTime::REF 2770792000
-system.mem_ctrls0_0.memoryStateTime::SREF 2814296339250
-system.mem_ctrls0_0.memoryStateTime::PRE_PDN 25366969500
-system.mem_ctrls0_0.memoryStateTime::ACT 7996080250
-system.mem_ctrls0_0.memoryStateTime::ACT_PDN 26428192250
-system.mem_ctrls0_1.actEnergy 153709920
-system.mem_ctrls0_1.preEnergy 81694965
-system.mem_ctrls0_1.readEnergy 303307200
-system.mem_ctrls0_1.writeEnergy 160478460
-system.mem_ctrls0_1.refreshEnergy 6659624400.000002
-system.mem_ctrls0_1.actBackEnergy 4887704400
-system.mem_ctrls0_1.preBackEnergy 399747360
-system.mem_ctrls0_1.actPowerDownEnergy 12334440330
-system.mem_ctrls0_1.prePowerDownEnergy 9988198080
-system.mem_ctrls0_1.selfRefreshEnergy 676565322465
-system.mem_ctrls0_1.totalEnergy 711536533050
-system.mem_ctrls0_1.averagePower 247.264193
-system.mem_ctrls0_1.totalIdleTime 2865871968249
-system.mem_ctrls0_1.memoryStateTime::IDLE 781353250
-system.mem_ctrls0_1.memoryStateTime::REF 2833504000
-system.mem_ctrls0_1.memoryStateTime::SREF 2812811827500
-system.mem_ctrls0_1.memoryStateTime::PRE_PDN 26010904500
-system.mem_ctrls0_1.memoryStateTime::ACT 8149889501
-system.mem_ctrls0_1.memoryStateTime::ACT_PDN 27049284749
-system.mem_ctrls1.pwrStateResidencyTicks::UNDEFINED 2877636763500
-system.mem_ctrls1.bytes_read::ruby.dir_cntrl1 5356864
-system.mem_ctrls1.bytes_read::total 5356864
-system.mem_ctrls1.bytes_written::ruby.dir_cntrl1 3877504
-system.mem_ctrls1.bytes_written::total 3877504
-system.mem_ctrls1.num_reads::ruby.dir_cntrl1 83701
-system.mem_ctrls1.num_reads::total 83701
-system.mem_ctrls1.num_writes::ruby.dir_cntrl1 60586
-system.mem_ctrls1.num_writes::total 60586
-system.mem_ctrls1.bw_read::ruby.dir_cntrl1 1861550
-system.mem_ctrls1.bw_read::total 1861550
-system.mem_ctrls1.bw_write::ruby.dir_cntrl1 1347461
-system.mem_ctrls1.bw_write::total 1347461
-system.mem_ctrls1.bw_total::ruby.dir_cntrl1 3209011
-system.mem_ctrls1.bw_total::total 3209011
-system.mem_ctrls1.readReqs 83701
-system.mem_ctrls1.writeReqs 60586
-system.mem_ctrls1.readBursts 83701
-system.mem_ctrls1.writeBursts 60586
-system.mem_ctrls1.bytesReadDRAM 5347776
-system.mem_ctrls1.bytesReadWrQ 9088
-system.mem_ctrls1.bytesWritten 3875840
-system.mem_ctrls1.bytesReadSys 5356864
-system.mem_ctrls1.bytesWrittenSys 3877504
-system.mem_ctrls1.servicedByWrQ 142
-system.mem_ctrls1.mergedWrBursts 0
-system.mem_ctrls1.neitherReadNorWriteReqs 0
-system.mem_ctrls1.perBankRdBursts::0 5400
-system.mem_ctrls1.perBankRdBursts::1 5815
-system.mem_ctrls1.perBankRdBursts::2 5276
-system.mem_ctrls1.perBankRdBursts::3 5426
-system.mem_ctrls1.perBankRdBursts::4 4839
-system.mem_ctrls1.perBankRdBursts::5 4300
-system.mem_ctrls1.perBankRdBursts::6 5043
-system.mem_ctrls1.perBankRdBursts::7 5018
-system.mem_ctrls1.perBankRdBursts::8 4946
-system.mem_ctrls1.perBankRdBursts::9 5249
-system.mem_ctrls1.perBankRdBursts::10 5246
-system.mem_ctrls1.perBankRdBursts::11 5942
-system.mem_ctrls1.perBankRdBursts::12 5386
-system.mem_ctrls1.perBankRdBursts::13 5191
-system.mem_ctrls1.perBankRdBursts::14 5276
-system.mem_ctrls1.perBankRdBursts::15 5206
-system.mem_ctrls1.perBankWrBursts::0 3705
-system.mem_ctrls1.perBankWrBursts::1 4296
-system.mem_ctrls1.perBankWrBursts::2 3783
-system.mem_ctrls1.perBankWrBursts::3 3773
-system.mem_ctrls1.perBankWrBursts::4 3604
-system.mem_ctrls1.perBankWrBursts::5 3159
-system.mem_ctrls1.perBankWrBursts::6 3653
-system.mem_ctrls1.perBankWrBursts::7 3758
-system.mem_ctrls1.perBankWrBursts::8 3765
-system.mem_ctrls1.perBankWrBursts::9 4055
-system.mem_ctrls1.perBankWrBursts::10 3645
-system.mem_ctrls1.perBankWrBursts::11 4256
-system.mem_ctrls1.perBankWrBursts::12 3895
-system.mem_ctrls1.perBankWrBursts::13 3822
-system.mem_ctrls1.perBankWrBursts::14 3790
-system.mem_ctrls1.perBankWrBursts::15 3601
-system.mem_ctrls1.numRdRetry 0
-system.mem_ctrls1.numWrRetry 0
-system.mem_ctrls1.totGap 2877613953000
-system.mem_ctrls1.readPktSize::0 0
-system.mem_ctrls1.readPktSize::1 0
-system.mem_ctrls1.readPktSize::2 0
-system.mem_ctrls1.readPktSize::3 0
-system.mem_ctrls1.readPktSize::4 0
-system.mem_ctrls1.readPktSize::5 0
-system.mem_ctrls1.readPktSize::6 83701
-system.mem_ctrls1.writePktSize::0 0
-system.mem_ctrls1.writePktSize::1 0
-system.mem_ctrls1.writePktSize::2 0
-system.mem_ctrls1.writePktSize::3 0
-system.mem_ctrls1.writePktSize::4 0
-system.mem_ctrls1.writePktSize::5 0
-system.mem_ctrls1.writePktSize::6 60586
-system.mem_ctrls1.rdQLenPdf::0 83559
-system.mem_ctrls1.rdQLenPdf::1 0
-system.mem_ctrls1.rdQLenPdf::2 0
-system.mem_ctrls1.rdQLenPdf::3 0
-system.mem_ctrls1.rdQLenPdf::4 0
-system.mem_ctrls1.rdQLenPdf::5 0
-system.mem_ctrls1.rdQLenPdf::6 0
-system.mem_ctrls1.rdQLenPdf::7 0
-system.mem_ctrls1.rdQLenPdf::8 0
-system.mem_ctrls1.rdQLenPdf::9 0
-system.mem_ctrls1.rdQLenPdf::10 0
-system.mem_ctrls1.rdQLenPdf::11 0
-system.mem_ctrls1.rdQLenPdf::12 0
-system.mem_ctrls1.rdQLenPdf::13 0
-system.mem_ctrls1.rdQLenPdf::14 0
-system.mem_ctrls1.rdQLenPdf::15 0
-system.mem_ctrls1.rdQLenPdf::16 0
-system.mem_ctrls1.rdQLenPdf::17 0
-system.mem_ctrls1.rdQLenPdf::18 0
-system.mem_ctrls1.rdQLenPdf::19 0
-system.mem_ctrls1.rdQLenPdf::20 0
-system.mem_ctrls1.rdQLenPdf::21 0
-system.mem_ctrls1.rdQLenPdf::22 0
-system.mem_ctrls1.rdQLenPdf::23 0
-system.mem_ctrls1.rdQLenPdf::24 0
-system.mem_ctrls1.rdQLenPdf::25 0
-system.mem_ctrls1.rdQLenPdf::26 0
-system.mem_ctrls1.rdQLenPdf::27 0
-system.mem_ctrls1.rdQLenPdf::28 0
-system.mem_ctrls1.rdQLenPdf::29 0
-system.mem_ctrls1.rdQLenPdf::30 0
-system.mem_ctrls1.rdQLenPdf::31 0
-system.mem_ctrls1.wrQLenPdf::0 1
-system.mem_ctrls1.wrQLenPdf::1 1
-system.mem_ctrls1.wrQLenPdf::2 1
-system.mem_ctrls1.wrQLenPdf::3 1
-system.mem_ctrls1.wrQLenPdf::4 1
-system.mem_ctrls1.wrQLenPdf::5 1
-system.mem_ctrls1.wrQLenPdf::6 1
-system.mem_ctrls1.wrQLenPdf::7 1
-system.mem_ctrls1.wrQLenPdf::8 1
-system.mem_ctrls1.wrQLenPdf::9 1
-system.mem_ctrls1.wrQLenPdf::10 1
-system.mem_ctrls1.wrQLenPdf::11 1
-system.mem_ctrls1.wrQLenPdf::12 1
-system.mem_ctrls1.wrQLenPdf::13 1
-system.mem_ctrls1.wrQLenPdf::14 1
-system.mem_ctrls1.wrQLenPdf::15 2769
-system.mem_ctrls1.wrQLenPdf::16 3003
-system.mem_ctrls1.wrQLenPdf::17 3356
-system.mem_ctrls1.wrQLenPdf::18 3378
-system.mem_ctrls1.wrQLenPdf::19 3617
-system.mem_ctrls1.wrQLenPdf::20 3304
-system.mem_ctrls1.wrQLenPdf::21 3499
-system.mem_ctrls1.wrQLenPdf::22 3328
-system.mem_ctrls1.wrQLenPdf::23 3583
-system.mem_ctrls1.wrQLenPdf::24 3328
-system.mem_ctrls1.wrQLenPdf::25 3307
-system.mem_ctrls1.wrQLenPdf::26 3238
-system.mem_ctrls1.wrQLenPdf::27 3270
-system.mem_ctrls1.wrQLenPdf::28 3357
-system.mem_ctrls1.wrQLenPdf::29 3257
-system.mem_ctrls1.wrQLenPdf::30 3218
-system.mem_ctrls1.wrQLenPdf::31 3208
-system.mem_ctrls1.wrQLenPdf::32 3182
-system.mem_ctrls1.wrQLenPdf::33 236
-system.mem_ctrls1.wrQLenPdf::34 147
-system.mem_ctrls1.wrQLenPdf::35 104
-system.mem_ctrls1.wrQLenPdf::36 96
-system.mem_ctrls1.wrQLenPdf::37 82
-system.mem_ctrls1.wrQLenPdf::38 85
-system.mem_ctrls1.wrQLenPdf::39 78
-system.mem_ctrls1.wrQLenPdf::40 60
-system.mem_ctrls1.wrQLenPdf::41 57
-system.mem_ctrls1.wrQLenPdf::42 54
-system.mem_ctrls1.wrQLenPdf::43 64
-system.mem_ctrls1.wrQLenPdf::44 48
-system.mem_ctrls1.wrQLenPdf::45 39
-system.mem_ctrls1.wrQLenPdf::46 37
-system.mem_ctrls1.wrQLenPdf::47 52
-system.mem_ctrls1.wrQLenPdf::48 47
-system.mem_ctrls1.wrQLenPdf::49 37
-system.mem_ctrls1.wrQLenPdf::50 36
-system.mem_ctrls1.wrQLenPdf::51 4
-system.mem_ctrls1.wrQLenPdf::52 3
-system.mem_ctrls1.wrQLenPdf::53 1
-system.mem_ctrls1.wrQLenPdf::54 1
-system.mem_ctrls1.wrQLenPdf::55 1
-system.mem_ctrls1.wrQLenPdf::56 0
-system.mem_ctrls1.wrQLenPdf::57 0
-system.mem_ctrls1.wrQLenPdf::58 0
-system.mem_ctrls1.wrQLenPdf::59 0
-system.mem_ctrls1.wrQLenPdf::60 0
-system.mem_ctrls1.wrQLenPdf::61 0
-system.mem_ctrls1.wrQLenPdf::62 0
-system.mem_ctrls1.wrQLenPdf::63 0
-system.mem_ctrls1.bytesPerActivate::samples 43454
-system.mem_ctrls1.bytesPerActivate::mean 212.261610
-system.mem_ctrls1.bytesPerActivate::gmean 128.615941
-system.mem_ctrls1.bytesPerActivate::stdev 269.315843
-system.mem_ctrls1.bytesPerActivate::0-127 22374 51.49% 51.49%
-system.mem_ctrls1.bytesPerActivate::128-255 10942 25.18% 76.67%
-system.mem_ctrls1.bytesPerActivate::256-383 3644 8.39% 85.06%
-system.mem_ctrls1.bytesPerActivate::384-511 1087 2.50% 87.56%
-system.mem_ctrls1.bytesPerActivate::512-639 965 2.22% 89.78%
-system.mem_ctrls1.bytesPerActivate::640-767 758 1.74% 91.52%
-system.mem_ctrls1.bytesPerActivate::768-895 397 0.91% 92.44%
-system.mem_ctrls1.bytesPerActivate::896-1023 239 0.55% 92.99%
-system.mem_ctrls1.bytesPerActivate::1024-1151 3048 7.01% 100.00%
-system.mem_ctrls1.bytesPerActivate::total 43454
-system.mem_ctrls1.rdPerTurnAround::samples 3156
-system.mem_ctrls1.rdPerTurnAround::mean 26.473067
-system.mem_ctrls1.rdPerTurnAround::stdev 420.930309
-system.mem_ctrls1.rdPerTurnAround::0-1023 3154 99.94% 99.94%
-system.mem_ctrls1.rdPerTurnAround::1024-2047 1 0.03% 99.97%
-system.mem_ctrls1.rdPerTurnAround::23552-24575 1 0.03% 100.00%
-system.mem_ctrls1.rdPerTurnAround::total 3156
-system.mem_ctrls1.wrPerTurnAround::samples 3156
-system.mem_ctrls1.wrPerTurnAround::mean 19.188847
-system.mem_ctrls1.wrPerTurnAround::gmean 18.952485
-system.mem_ctrls1.wrPerTurnAround::stdev 3.672722
-system.mem_ctrls1.wrPerTurnAround::16 315 9.98% 9.98%
-system.mem_ctrls1.wrPerTurnAround::17 47 1.49% 11.47%
-system.mem_ctrls1.wrPerTurnAround::18 1682 53.30% 64.77%
-system.mem_ctrls1.wrPerTurnAround::19 290 9.19% 73.95%
-system.mem_ctrls1.wrPerTurnAround::20 280 8.87% 82.83%
-system.mem_ctrls1.wrPerTurnAround::21 56 1.77% 84.60%
-system.mem_ctrls1.wrPerTurnAround::22 268 8.49% 93.09%
-system.mem_ctrls1.wrPerTurnAround::23 49 1.55% 94.65%
-system.mem_ctrls1.wrPerTurnAround::24 16 0.51% 95.15%
-system.mem_ctrls1.wrPerTurnAround::25 78 2.47% 97.62%
-system.mem_ctrls1.wrPerTurnAround::26 10 0.32% 97.94%
-system.mem_ctrls1.wrPerTurnAround::27 4 0.13% 98.07%
-system.mem_ctrls1.wrPerTurnAround::28 2 0.06% 98.13%
-system.mem_ctrls1.wrPerTurnAround::29 3 0.10% 98.23%
-system.mem_ctrls1.wrPerTurnAround::30 3 0.10% 98.32%
-system.mem_ctrls1.wrPerTurnAround::31 5 0.16% 98.48%
-system.mem_ctrls1.wrPerTurnAround::32 2 0.06% 98.54%
-system.mem_ctrls1.wrPerTurnAround::33 3 0.10% 98.64%
-system.mem_ctrls1.wrPerTurnAround::34 2 0.06% 98.70%
-system.mem_ctrls1.wrPerTurnAround::36 4 0.13% 98.83%
-system.mem_ctrls1.wrPerTurnAround::37 2 0.06% 98.89%
-system.mem_ctrls1.wrPerTurnAround::38 5 0.16% 99.05%
-system.mem_ctrls1.wrPerTurnAround::41 2 0.06% 99.11%
-system.mem_ctrls1.wrPerTurnAround::42 1 0.03% 99.14%
-system.mem_ctrls1.wrPerTurnAround::43 1 0.03% 99.18%
-system.mem_ctrls1.wrPerTurnAround::44 1 0.03% 99.21%
-system.mem_ctrls1.wrPerTurnAround::45 8 0.25% 99.46%
-system.mem_ctrls1.wrPerTurnAround::46 2 0.06% 99.52%
-system.mem_ctrls1.wrPerTurnAround::47 3 0.10% 99.62%
-system.mem_ctrls1.wrPerTurnAround::48 6 0.19% 99.81%
-system.mem_ctrls1.wrPerTurnAround::49 2 0.06% 99.87%
-system.mem_ctrls1.wrPerTurnAround::50 1 0.03% 99.90%
-system.mem_ctrls1.wrPerTurnAround::52 1 0.03% 99.94%
-system.mem_ctrls1.wrPerTurnAround::56 1 0.03% 99.97%
-system.mem_ctrls1.wrPerTurnAround::59 1 0.03% 100.00%
-system.mem_ctrls1.wrPerTurnAround::total 3156
-system.mem_ctrls1.totQLat 3107256500
-system.mem_ctrls1.totMemAccLat 4673987750
-system.mem_ctrls1.totBusLat 417795000
-system.mem_ctrls1.avgQLat 37186.38
-system.mem_ctrls1.avgBusLat 5000.00
-system.mem_ctrls1.avgMemAccLat 55936.38
-system.mem_ctrls1.avgRdBW 1.86
-system.mem_ctrls1.avgWrBW 1.35
-system.mem_ctrls1.avgRdBWSys 1.86
-system.mem_ctrls1.avgWrBWSys 1.35
-system.mem_ctrls1.peakBW 12800.00
-system.mem_ctrls1.busUtil 0.03
-system.mem_ctrls1.busUtilRead 0.01
-system.mem_ctrls1.busUtilWrite 0.01
-system.mem_ctrls1.avgRdQLen 1.00
-system.mem_ctrls1.avgWrQLen 22.75
-system.mem_ctrls1.readRowHits 64839
-system.mem_ctrls1.writeRowHits 35826
-system.mem_ctrls1.readRowHitRate 77.60
-system.mem_ctrls1.writeRowHitRate 59.13
-system.mem_ctrls1.avgGap 19943681.36
-system.mem_ctrls1.pageHitRate 69.84
-system.mem_ctrls1_0.actEnergy 149911440
-system.mem_ctrls1_0.preEnergy 79679820
-system.mem_ctrls1_0.readEnergy 293575380
-system.mem_ctrls1_0.writeEnergy 155195820
-system.mem_ctrls1_0.refreshEnergy 6751820400.000002
-system.mem_ctrls1_0.actBackEnergy 4752918780
-system.mem_ctrls1_0.preBackEnergy 429536640
-system.mem_ctrls1_0.actPowerDownEnergy 12706825890
-system.mem_ctrls1_0.prePowerDownEnergy 10139704320
-system.mem_ctrls1_0.selfRefreshEnergy 676340330145
-system.mem_ctrls1_0.totalEnergy 711802127055
-system.mem_ctrls1_0.averagePower 247.356489
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-system.ruby.Directory_Controller.DMA_ACK::total 219
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-system.ruby.Directory_Controller.I.GETS::total 29360
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-system.ruby.Directory_Controller.I.Memory_Ack::total 84981
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-system.ruby.Directory_Controller.I.DMA_READ::total 13
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-system.ruby.Directory_Controller.S.GETX::total 6623
-system.ruby.Directory_Controller.S.GETS | 842 51.22% 51.22% | 802 48.78% 100.00%
-system.ruby.Directory_Controller.S.GETS::total 1644
-system.ruby.Directory_Controller.S.DMA_READ | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.Directory_Controller.S.DMA_READ::total 2
-system.ruby.Directory_Controller.S.DMA_WRITE | 19 50.00% 50.00% | 19 50.00% 100.00%
-system.ruby.Directory_Controller.S.DMA_WRITE::total 38
-system.ruby.Directory_Controller.M.PUTX | 42433 49.98% 49.98% | 42474 50.02% 100.00%
-system.ruby.Directory_Controller.M.PUTX::total 84907
-system.ruby.Directory_Controller.M.DMA_READ | 198 90.41% 90.41% | 21 9.59% 100.00%
-system.ruby.Directory_Controller.M.DMA_READ::total 219
-system.ruby.Directory_Controller.M.DMA_WRITE | 2192 50.00% 50.00% | 2192 50.00% 100.00%
-system.ruby.Directory_Controller.M.DMA_WRITE::total 4384
-system.ruby.Directory_Controller.IS.Unblock | 14793 50.38% 50.38% | 14567 49.62% 100.00%
-system.ruby.Directory_Controller.IS.Unblock::total 29360
-system.ruby.Directory_Controller.IS.Memory_Data | 14793 50.38% 50.38% | 14567 49.62% 100.00%
-system.ruby.Directory_Controller.IS.Memory_Data::total 29360
-system.ruby.Directory_Controller.SS.Last_Unblock | 842 51.22% 51.22% | 802 48.78% 100.00%
-system.ruby.Directory_Controller.SS.Last_Unblock::total 1644
-system.ruby.Directory_Controller.SS.Memory_Data | 842 51.22% 51.22% | 802 48.78% 100.00%
-system.ruby.Directory_Controller.SS.Memory_Data::total 1644
-system.ruby.Directory_Controller.MM.Exclusive_Unblock | 68292 49.99% 49.99% | 68325 50.01% 100.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 136617
-system.ruby.Directory_Controller.MM.Memory_Data | 68292 49.99% 49.99% | 68325 50.01% 100.00%
-system.ruby.Directory_Controller.MM.Memory_Data::total 136617
-system.ruby.Directory_Controller.MI.Dirty_Writeback | 42433 49.98% 49.98% | 42474 50.02% 100.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback::total 84907
-system.ruby.Directory_Controller.XI_M.Memory_Data | 6 46.15% 46.15% | 7 53.85% 100.00%
-system.ruby.Directory_Controller.XI_M.Memory_Data::total 13
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 18112 50.00% 50.00% | 18112 50.00% 100.00%
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 36224
-system.ruby.Directory_Controller.XI_U.Memory_Ack | 18074 50.00% 50.00% | 18076 50.00% 100.00%
-system.ruby.Directory_Controller.XI_U.Memory_Ack::total 36150
-system.ruby.Directory_Controller.OI_D.Data | 2192 50.00% 50.00% | 2192 50.00% 100.00%
-system.ruby.Directory_Controller.OI_D.Data::total 4384
-system.ruby.Directory_Controller.MD.DMA_ACK | 198 90.41% 90.41% | 21 9.59% 100.00%
-system.ruby.Directory_Controller.MD.DMA_ACK::total 219
-system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 354 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 354
-system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1082520 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.WriteRequest::total 1082520
-system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 234
-system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.DMA_Ack::total 36224
-system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 38 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Inv_Ack::total 38
-system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.All_Acks::total 36224
-system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 234
-system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.WriteRequest::total 36224
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 120
-system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 234
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1046296 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 1046296
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 36224
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 38 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 38
-system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 36224
-system.ruby.L1Cache_Controller.Load 24230106 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 115772647 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 20058528 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 2437124 0.00% 0.00%
-system.ruby.L1Cache_Controller.Fwd_GETX 13 0.00% 0.00%
-system.ruby.L1Cache_Controller.Fwd_DMA 170 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 1742675 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 695119 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 1710696 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 723019 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks 306547 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_Timeout 695119 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 599377 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 1531870 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 303505 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Load 2005001 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 113621133 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 3042 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 1738970 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 8042001 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 379575 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 92926 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 187860 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Load 202674 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch 61597 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Store 107662 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 3396 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout 280910 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 13163880 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 16598991 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 506886 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX 13 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Fwd_DMA 170 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 48742 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 2952384 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout 414209 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data 303505 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data 3042 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.All_acks 306547 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 1742675 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 388572 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Load 167673 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Ifetch 177752 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Store 18 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack 1710696 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 28273 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Load 758 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch 720 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 694746 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 2131540 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 306547 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 694746 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 1738970 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_GETX 4384 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_DMA 219 0.00% 0.00%
-system.ruby.L2Cache_Controller.Inv 38 0.00% 0.00%
-system.ruby.L2Cache_Controller.IntAck 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 136632 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 167621 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 28273 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 694746 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 84907 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 3453370 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 695119 0.00% 0.00%
-system.ruby.L2Cache_Controller.DmaAck 170 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 92511 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 30988 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 131317 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 16 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 2718 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 28273 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.Inv 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 694746 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_DMA 170 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 1711671 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 2258 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Inv 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 7601 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 324 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 1710697 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 388572 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 169930 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_GETX 4371 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_DMA 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 84907 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 28273 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 293 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 1710696 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 694746 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 31004 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 31004 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 133575 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 3042 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 136617 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 136617 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.IntAck 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.All_Acks 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 169930 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 1711670 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 388572 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 84907 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXD.DmaAck 170 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=system.cpu0.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu0.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
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-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
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-
-[system.cpu0.dcache.tags]
-type=LRU
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-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
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-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
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-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
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-
-[system.cpu0.dtb]
-type=ArmTLB
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-
-[system.cpu0.dtb.walker]
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-
-[system.cpu0.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
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-
-[system.cpu0.executeFuncUnits.funcUnits0]
-type=MinorFU
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-
-[system.cpu0.executeFuncUnits.funcUnits0.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits0.timings]
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-
-[system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses]
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-opClasses=
-
-[system.cpu0.executeFuncUnits.funcUnits1]
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-
-[system.cpu0.executeFuncUnits.funcUnits1.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits1.timings]
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-opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses
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-
-[system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits2]
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-
-[system.cpu0.executeFuncUnits.funcUnits2.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits2.timings]
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-
-[system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits3]
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-
-[system.cpu0.executeFuncUnits.funcUnits3.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits4]
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-opLat=6
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
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-opClass=FloatAdd
-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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-
-[system.cpu0.executeFuncUnits.funcUnits4.timings]
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-opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses
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-
-[system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
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-opClasses=
-
-[system.cpu0.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
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-issueLat=1
-opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu0.executeFuncUnits.funcUnits5.timings
-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
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-opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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-
-[system.cpu0.executeFuncUnits.funcUnits5.timings]
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-
-[system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits6]
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-issueLat=1
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-timings=
-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses]
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-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
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-
-[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1]
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-
-[system.cpu0.icache]
-type=Cache
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-mshrs=2
-p_state_clk_gate_bins=20
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-p_state_clk_gate_min=1000
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-size=32768
-system=system
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-
-[system.cpu0.icache.tags]
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-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
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-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
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-
-[system.cpu0.isa]
-type=ArmISA
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-fpsid=1090793632
-id_aa64afr0_el1=0
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-id_mmfr2=19070976
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-midr=1091551472
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-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
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-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
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-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
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-
-[system.cpu0.itb]
-type=ArmTLB
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-
-[system.cpu0.itb.walker]
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-
-[system.cpu0.l2cache]
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-
-[system.cpu0.l2cache.prefetcher]
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-
-[system.cpu0.l2cache.tags]
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-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
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-snoop_filter=system.cpu0.toL2Bus.snoop_filter
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-system=system
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-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
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-
-[system.cpu0.tracer]
-type=ExeTracer
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-
-[system.cpu1]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
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-interrupts=system.cpu1.interrupts
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-istage2_mmu=system.cpu1.istage2_mmu
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-simpoint_start_insts=
-socket_id=0
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-system=system
-threadPolicy=RoundRobin
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-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.branchPred]
-type=TournamentBP
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-choiceCtrBits=2
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-
-[system.cpu1.dcache]
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-size=32768
-system=system
-tags=system.cpu1.dcache.tags
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-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
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-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
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-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
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-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
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-
-[system.cpu1.dtb]
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-
-[system.cpu1.dtb.walker]
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-
-[system.cpu1.executeFuncUnits]
-type=MinorFUPool
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-
-[system.cpu1.executeFuncUnits.funcUnits0]
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-[system.cpu1.executeFuncUnits.funcUnits0.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits0.timings]
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-
-[system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits1]
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-[system.cpu1.executeFuncUnits.funcUnits1.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits1.timings]
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-
-[system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits2]
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-[system.cpu1.executeFuncUnits.funcUnits2.opClasses]
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-
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-[system.cpu1.executeFuncUnits.funcUnits2.timings]
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-
-[system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits3]
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-
-[system.cpu1.executeFuncUnits.funcUnits3.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits4]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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-
-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
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-[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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-[system.cpu1.executeFuncUnits.funcUnits4.timings]
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-[system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses]
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-
-[system.cpu1.executeFuncUnits.funcUnits5]
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-[system.cpu1.executeFuncUnits.funcUnits5.opClasses]
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-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
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-[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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-[system.cpu1.executeFuncUnits.funcUnits5.timings]
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-[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0]
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-[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1]
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-[system.cpu1.icache]
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-[system.cpu1.interrupts]
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-[system.cpu1.isa]
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-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:00
-gem5 executing on e108600-lin, pid 17333
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47554910274000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.310816 # Number of seconds simulated
-sim_ticks 47310816168000 # Number of ticks simulated
-final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 279196 # Simulator instruction rate (inst/s)
-host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
-host_mem_usage 770320 # Number of bytes of host memory used
-host_seconds 2980.95 # Real time elapsed on the host
-sim_insts 832269934 # Number of instructions simulated
-sim_ops 991180133 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
-system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1084146 # Number of read requests accepted
-system.physmem.writeReqs 1315173 # Number of write requests accepted
-system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
-system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 69238 # Per bank write bursts
-system.physmem.perBankRdBursts::1 72128 # Per bank write bursts
-system.physmem.perBankRdBursts::2 62859 # Per bank write bursts
-system.physmem.perBankRdBursts::3 64909 # Per bank write bursts
-system.physmem.perBankRdBursts::4 64833 # Per bank write bursts
-system.physmem.perBankRdBursts::5 74280 # Per bank write bursts
-system.physmem.perBankRdBursts::6 68552 # Per bank write bursts
-system.physmem.perBankRdBursts::7 74109 # Per bank write bursts
-system.physmem.perBankRdBursts::8 62269 # Per bank write bursts
-system.physmem.perBankRdBursts::9 70311 # Per bank write bursts
-system.physmem.perBankRdBursts::10 59842 # Per bank write bursts
-system.physmem.perBankRdBursts::11 70232 # Per bank write bursts
-system.physmem.perBankRdBursts::12 64744 # Per bank write bursts
-system.physmem.perBankRdBursts::13 72876 # Per bank write bursts
-system.physmem.perBankRdBursts::14 66012 # Per bank write bursts
-system.physmem.perBankRdBursts::15 66520 # Per bank write bursts
-system.physmem.perBankWrBursts::0 83559 # Per bank write bursts
-system.physmem.perBankWrBursts::1 83793 # Per bank write bursts
-system.physmem.perBankWrBursts::2 79464 # Per bank write bursts
-system.physmem.perBankWrBursts::3 82775 # Per bank write bursts
-system.physmem.perBankWrBursts::4 80648 # Per bank write bursts
-system.physmem.perBankWrBursts::5 87124 # Per bank write bursts
-system.physmem.perBankWrBursts::6 80406 # Per bank write bursts
-system.physmem.perBankWrBursts::7 83854 # Per bank write bursts
-system.physmem.perBankWrBursts::8 77300 # Per bank write bursts
-system.physmem.perBankWrBursts::9 82321 # Per bank write bursts
-system.physmem.perBankWrBursts::10 78447 # Per bank write bursts
-system.physmem.perBankWrBursts::11 84798 # Per bank write bursts
-system.physmem.perBankWrBursts::12 79286 # Per bank write bursts
-system.physmem.perBankWrBursts::13 85569 # Per bank write bursts
-system.physmem.perBankWrBursts::14 81705 # Per bank write bursts
-system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
-system.physmem.totGap 47310814104000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 25 # Read request sizes (log2)
-system.physmem.readPktSize::4 5 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 2 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
-system.physmem.totQLat 57570179828 # Total ticks spent queuing
-system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
-system.physmem.readRowHits 798943 # Number of row buffer hits during reads
-system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
-system.physmem.avgGap 19718434.32 # Average gap between requests
-system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
-system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
-system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
-system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
-system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
-system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 91107490 # DTB read hits
-system.cpu0.dtb.read_misses 238663 # DTB read misses
-system.cpu0.dtb.write_hits 81148084 # DTB write hits
-system.cpu0.dtb.write_misses 53270 # DTB write misses
-system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
-system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 172255574 # DTB hits
-system.cpu0.dtb.misses 291933 # DTB misses
-system.cpu0.dtb.accesses 172547507 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 65131 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 201165320 # ITB inst hits
-system.cpu0.itb.inst_misses 65131 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
-system.cpu0.itb.hits 201165320 # DTB hits
-system.cpu0.itb.misses 65131 # DTB misses
-system.cpu0.itb.accesses 201230451 # DTB accesses
-system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 923231946 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 433947137 # Number of instructions committed
-system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.127522 # CPI: cycles per instruction
-system.cpu0.ipc 0.470030 # IPC: instructions per cycle
-system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
-system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
-system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
-system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
-system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
-system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::total 516803462 # Class of committed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
-system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 6005277 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits
-system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses
-system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks
-system.cpu0.dcache.writebacks::total 6005280 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 9998472 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits
-system.cpu0.icache.overall_hits::total 190986664 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses
-system.cpu0.icache.overall_misses::total 9998995 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses
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-system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks
-system.cpu0.icache.writebacks::total 9998472 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses
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-system.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 2932551 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits
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-system.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits
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-system.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses
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-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 85144665 # DTB read hits
-system.cpu1.dtb.read_misses 232605 # DTB read misses
-system.cpu1.dtb.write_hits 73861979 # DTB write hits
-system.cpu1.dtb.write_misses 45370 # DTB write misses
-system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
-system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 159006644 # DTB hits
-system.cpu1.dtb.misses 277975 # DTB misses
-system.cpu1.dtb.accesses 159284619 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 63204 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 184175570 # ITB inst hits
-system.cpu1.itb.inst_misses 63204 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
-system.cpu1.itb.hits 184175570 # DTB hits
-system.cpu1.itb.misses 63204 # DTB misses
-system.cpu1.itb.accesses 184238774 # DTB accesses
-system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 798693745 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 398322797 # Number of instructions committed
-system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.005142 # CPI: cycles per instruction
-system.cpu1.ipc 0.498718 # IPC: instructions per cycle
-system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
-system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
-system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
-system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
-system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
-system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::total 474376671 # Class of committed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
-system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 5132038 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits
-system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses
-system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks
-system.cpu1.dcache.writebacks::total 5132050 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 8722673 # number of replacements
-system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
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-system.cpu1.icache.overall_hits::total 175283400 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 8723185 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks
-system.cpu1.icache.writebacks::total 8722673 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency
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-system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 2217652 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks.
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-system.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id
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-system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses
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-system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits
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-system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits
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-system.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses
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-system.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses
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-system.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles
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-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks
-system.cpu1.l2cache.writebacks::total 1164875 # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115597 # number of replacements
-system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040910 # Number of tag accesses
-system.iocache.tags.data_accesses 1040910 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115657 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115617 # number of overall misses
-system.iocache.overall_misses::total 115657 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106693 # number of writebacks
-system.iocache.writebacks::total 106693 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 1609900 # number of replacements
-system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use
-system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks.
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-system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 42476 # Transaction distribution
-system.membus.trans_dist::ReadResp 989688 # Transaction distribution
-system.membus.trans_dist::WriteReq 37999 # Transaction distribution
-system.membus.trans_dist::WriteResp 37999 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution
-system.membus.trans_dist::CleanEvict 291937 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 150791 # Transaction distribution
-system.membus.trans_dist::ReadExResp 135122 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 586564 # Total snoops (count)
-system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
-system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2402773 # Request fanout histogram
-system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3035429 # Total snoops (count)
-system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000024] Console: colour dummy device 80x25\r
-[ 0.000027] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000028] pid_max: default: 32768 minimum: 301\r
-[ 0.000039] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000040] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000160] hw perfevents: no hardware support available\r
-[ 0.060042] CPU1: Booted secondary processor\r
-[ 1.080079] CPU2: failed to come online\r
-[ 2.100148] CPU3: failed to come online\r
-[ 2.100151] Brought up 2 CPUs\r
-[ 2.100152] SMP: Total of 2 processors activated.\r
-[ 2.100226] devtmpfs: initialized\r
-[ 2.100728] atomic64_test: passed\r
-[ 2.100773] regulator-dummy: no parameters\r
-[ 2.101119] NET: Registered protocol family 16\r
-[ 2.101251] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101259] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.101662] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.101665] Serial: AMBA PL011 UART driver\r
-[ 2.101855] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101892] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.102468] console [ttyAMA0] enabled\r
-[ 2.102623] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.102687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.102745] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.102803] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140306] 3V3: 3300 mV \r
-[ 2.140354] vgaarb: loaded\r
-[ 2.140400] SCSI subsystem initialized\r
-[ 2.140435] libata version 3.00 loaded.\r
-[ 2.140482] usbcore: registered new interface driver usbfs\r
-[ 2.140500] usbcore: registered new interface driver hub\r
-[ 2.140526] usbcore: registered new device driver usb\r
-[ 2.140554] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140564] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140583] PTP clock support registered\r
-[ 2.140715] Switched to clocksource arch_sys_counter\r
-[ 2.142179] NET: Registered protocol family 2\r
-[ 2.142255] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.142273] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.142290] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.142312] TCP: reno registered\r
-[ 2.142319] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142331] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142367] NET: Registered protocol family 1\r
-[ 2.142431] RPC: Registered named UNIX socket transport module.\r
-[ 2.142441] RPC: Registered udp transport module.\r
-[ 2.142450] RPC: Registered tcp transport module.\r
-[ 2.142458] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.142471] PCI: CLS 0 bytes, default 64\r
-[ 2.142634] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.142729] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.144357] fuse init (API version 7.23)\r
-[ 2.144445] msgmni has been set to 469\r
-[ 2.144792] io scheduler noop registered\r
-[ 2.144847] io scheduler cfq registered (default)\r
-[ 2.145229] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.145243] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.145255] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.145268] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.145278] pci_bus 0000:00: scanning bus\r
-[ 2.145289] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.145303] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.145317] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145353] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.145366] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.145377] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.145388] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.145399] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.145410] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.145421] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145456] pci_bus 0000:00: fixups for bus\r
-[ 2.145464] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.145476] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.145496] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.145505] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.145516] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.145525] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.145537] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.145551] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.145564] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.145577] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.145589] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.145601] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.145612] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.145624] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.146092] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.146340] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.146352] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.146375] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.146628] scsi0 : ata_piix\r
-[ 2.146701] scsi1 : ata_piix\r
-[ 2.146733] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.146746] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.146850] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.146863] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.146877] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.146889] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.300748] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.300759] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.300788] ata1.00: configured for UDMA/33\r
-[ 2.300844] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.300954] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.300958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.300986] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.300996] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.301021] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.301150] sda: sda1\r
-[ 2.301268] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.421014] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.421028] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.421050] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.421060] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.421081] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.421093] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.421166] usbcore: registered new interface driver usb-storage\r
-[ 2.421232] mousedev: PS/2 mouse device common for all mice\r
-[ 2.421395] usbcore: registered new interface driver usbhid\r
-[ 2.421405] usbhid: USB HID core driver\r
-[ 2.421435] TCP: cubic registered\r
-[ 2.421443] NET: Registered protocol family 17\r
-\0[ 2.421846] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.421896] devtmpfs: mounted\r
-[ 2.421929] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.460465] udevd[609]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.543480] random: dd urandom read with 18 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.670941] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
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-choiceCtrBits=2
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-indirectWays=2
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-localCtrBits=2
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-
-[system.cpu.dcache]
-type=Cache
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-clk_domain=system.cpu_clk_domain
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-p_state_clk_gate_bins=20
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-power_model=Null
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-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
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-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
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-sys=system
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-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
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-is_stage2=true
-size=32
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-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
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-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
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-
-[system.cpu.dtb.walker]
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-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
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-
-[system.cpu.executeFuncUnits.funcUnits0]
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-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
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-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits1]
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-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
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-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits2]
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-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
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-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits3]
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-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits4]
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-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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-[system.cpu.executeFuncUnits.funcUnits4.timings]
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-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits5]
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-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
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-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
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-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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-[system.cpu.executeFuncUnits.funcUnits5.timings]
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-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
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-[system.cpu.executeFuncUnits.funcUnits6]
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-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
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-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
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-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
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-[system.cpu.icache]
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-[system.cpu.icache.tags]
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-
-[system.cpu.interrupts]
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-[system.cpu.isa]
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-
-[system.cpu.istage2_mmu]
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-
-[system.cpu.istage2_mmu.stage2_tlb]
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-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
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-[system.cpu.itb]
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-[system.cpu.itb.walker]
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-
-[system.cpu.l2cache]
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-[system.cpu.l2cache.tags]
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-[system.cpu.toL2Bus]
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:01:48
-gem5 executing on e108600-lin, pid 17560
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51688774990000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.643658 # Number of seconds simulated
-sim_ticks 51643657651000 # Number of ticks simulated
-final_tick 51643657651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 290656 # Simulator instruction rate (inst/s)
-host_op_rate 346501 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16573581112 # Simulator tick rate (ticks/s)
-host_mem_usage 686852 # Number of bytes of host memory used
-host_seconds 3116.02 # Real time elapsed on the host
-sim_insts 905689769 # Number of instructions simulated
-sim_ops 1079705427 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 481856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 390720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 7301696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 78480968 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 396608 # Number of bytes read from this memory
-system.physmem.bytes_read::total 87051848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 7301696 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7301696 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 106840192 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 106860772 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 7529 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6105 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 114089 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1226278 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6197 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1360198 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1669378 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1671951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 9330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 7566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 141386 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1519663 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7680 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1685625 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 141386 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141386 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2068796 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2069194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2068796 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 9330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 7566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 141386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1520062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7680 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3754820 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1360198 # Number of read requests accepted
-system.physmem.writeReqs 1671951 # Number of write requests accepted
-system.physmem.readBursts 1360198 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1671951 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 86990528 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 62144 # Total number of bytes read from write queue
-system.physmem.bytesWritten 106858944 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 87051848 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 106860772 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 971 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 83237 # Per bank write bursts
-system.physmem.perBankRdBursts::1 85225 # Per bank write bursts
-system.physmem.perBankRdBursts::2 82489 # Per bank write bursts
-system.physmem.perBankRdBursts::3 80125 # Per bank write bursts
-system.physmem.perBankRdBursts::4 87648 # Per bank write bursts
-system.physmem.perBankRdBursts::5 94125 # Per bank write bursts
-system.physmem.perBankRdBursts::6 89556 # Per bank write bursts
-system.physmem.perBankRdBursts::7 88166 # Per bank write bursts
-system.physmem.perBankRdBursts::8 78937 # Per bank write bursts
-system.physmem.perBankRdBursts::9 92012 # Per bank write bursts
-system.physmem.perBankRdBursts::10 85547 # Per bank write bursts
-system.physmem.perBankRdBursts::11 87304 # Per bank write bursts
-system.physmem.perBankRdBursts::12 77322 # Per bank write bursts
-system.physmem.perBankRdBursts::13 84061 # Per bank write bursts
-system.physmem.perBankRdBursts::14 80795 # Per bank write bursts
-system.physmem.perBankRdBursts::15 82678 # Per bank write bursts
-system.physmem.perBankWrBursts::0 101181 # Per bank write bursts
-system.physmem.perBankWrBursts::1 102649 # Per bank write bursts
-system.physmem.perBankWrBursts::2 102280 # Per bank write bursts
-system.physmem.perBankWrBursts::3 101626 # Per bank write bursts
-system.physmem.perBankWrBursts::4 106705 # Per bank write bursts
-system.physmem.perBankWrBursts::5 111943 # Per bank write bursts
-system.physmem.perBankWrBursts::6 107546 # Per bank write bursts
-system.physmem.perBankWrBursts::7 108809 # Per bank write bursts
-system.physmem.perBankWrBursts::8 101631 # Per bank write bursts
-system.physmem.perBankWrBursts::9 107791 # Per bank write bursts
-system.physmem.perBankWrBursts::10 102979 # Per bank write bursts
-system.physmem.perBankWrBursts::11 104017 # Per bank write bursts
-system.physmem.perBankWrBursts::12 98121 # Per bank write bursts
-system.physmem.perBankWrBursts::13 104909 # Per bank write bursts
-system.physmem.perBankWrBursts::14 102656 # Per bank write bursts
-system.physmem.perBankWrBursts::15 104828 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 458 # Number of times write queue was full causing retry
-system.physmem.totGap 51643655791000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 13 # Read request sizes (log2)
-system.physmem.readPktSize::4 2 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1360183 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 1 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1669378 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1282957 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 70161 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 871 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 445 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 945 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 570 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 269 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 159 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 78 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 31821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 39955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 90821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 97628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 100256 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 96883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 101095 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 99439 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 101345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 97950 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 101005 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 102593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 99923 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 96951 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 96056 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 95043 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 92451 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 92535 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 2382 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 2134 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1567 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1311 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1115 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 953 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 933 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 998 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 891 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 728 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 867 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 705 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 880 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 1479 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1458 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 568 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1009 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 752315 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 257.670024 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 155.219861 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 291.691185 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 319843 42.51% 42.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 192789 25.63% 68.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 70379 9.35% 77.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 39533 5.25% 82.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 27835 3.70% 86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 18762 2.49% 88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 14354 1.91% 90.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 11626 1.55% 92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 57194 7.60% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 752315 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 89671 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 15.157342 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 22.777727 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 89658 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 7 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 89671 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 89671 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.619966 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.881543 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.948219 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23 81046 90.38% 90.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31 5562 6.20% 96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39 1304 1.45% 98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47 395 0.44% 98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55 213 0.24% 98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63 159 0.18% 98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71 654 0.73% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79 203 0.23% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87 30 0.03% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95 3 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103 5 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111 17 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119 4 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127 4 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135 32 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143 13 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151 6 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199 10 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 89671 # Writes before turning the bus around for reads
-system.physmem.totQLat 40684785332 # Total ticks spent queuing
-system.physmem.totMemAccLat 66170291582 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6796135000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29932.30 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48682.30 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.07 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.69 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.07 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing
-system.physmem.readRowHits 1052962 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1223619 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes
-system.physmem.avgGap 17032031.01 # Average gap between requests
-system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2732670780 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1452445170 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4930676940 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4399097580 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 51881762400.000015 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 47976087180 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 3104058720 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 109980529290 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 71485388640 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 12273611587950 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 12571576503750 # Total energy per rank (pJ)
-system.physmem_0.averagePower 243.429243 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 51530314812756 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 5413929000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 22045432000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 51102968874750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 186159553736 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 85883432494 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 241186429020 # Time in different power states
-system.physmem_1.actEnergy 2638872600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1402590255 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4774203840 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4316585040 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 51214263360.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 48316306500 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 3067085280 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 106463182980 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 70942598400 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 12275647651350 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 12568805141895 # Total energy per rank (pJ)
-system.physmem_1.averagePower 243.375580 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 51529660585796 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 5336166484 # Time in different power states
-system.physmem_1.memoryStateTime::REF 21762952000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 51111446865750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 184746715790 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 86892179220 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 233472771756 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 230671595 # Number of BP lookups
-system.cpu.branchPred.condPredicted 148977251 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12591272 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 161205478 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 94166388 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 58.413888 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 32707519 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2199358 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 7428890 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 5357971 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 2070919 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 851352 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 612824 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 612824 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 25045 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 213625 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 612824 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 612824 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 612824 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 238670 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 26656.848368 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 235680 98.75% 98.75% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 2495 1.05% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 126 0.05% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 157 0.07% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 28 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 238670 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 411876000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 411876000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 411876000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 213626 89.51% 89.51% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 25045 10.49% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 238671 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 612824 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 612824 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 238671 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 238671 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 851495 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 191427667 # DTB read hits
-system.cpu.dtb.read_misses 503751 # DTB read misses
-system.cpu.dtb.write_hits 170371453 # DTB write hits
-system.cpu.dtb.write_misses 109073 # DTB write misses
-system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 82805 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 891 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 16210 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 24062 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 191931418 # DTB read accesses
-system.cpu.dtb.write_accesses 170480526 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 361799120 # DTB hits
-system.cpu.dtb.misses 612824 # DTB misses
-system.cpu.dtb.accesses 362411944 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 137744 # Table walker walks requested
-system.cpu.itb.walker.walksLong 137744 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1060 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 119122 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 137744 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 137744 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 137744 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 120182 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28731.482252 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24330.551658 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24049.037609 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 116919 97.28% 97.28% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 2876 2.39% 99.68% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 146 0.12% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 107 0.09% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 36 0.03% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 64 0.05% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 120182 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 411203500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 411203500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 411203500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 119122 99.12% 99.12% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1060 0.88% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 120182 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 137744 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 137744 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120182 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 120182 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 257926 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 367199991 # ITB inst hits
-system.cpu.itb.inst_misses 137744 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 59110 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 331525 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 367337735 # ITB inst accesses
-system.cpu.itb.hits 367199991 # DTB hits
-system.cpu.itb.misses 137744 # DTB misses
-system.cpu.itb.accesses 367337735 # DTB accesses
-system.cpu.numPwrStateTransitions 33588 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 16794 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 3006267839.468917 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 59370181603.459618 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 7493 44.62% 44.62% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 9266 55.17% 99.79% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988777658384 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 16794 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 1156395554959 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 2312845645 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 905689769 # Number of instructions committed
-system.cpu.committedOps 1079705427 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 38872378 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 7934 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 100975614107 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.553684 # CPI: cycles per instruction
-system.cpu.ipc 0.391591 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 721452382 66.82% 66.82% # Class of committed instruction
-system.cpu.op_class_0::IntMult 2371003 0.22% 67.04% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 100622 0.01% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 8 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 13 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 21 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 67.05% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 107773 0.01% 67.06% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.06% # Class of committed instruction
-system.cpu.op_class_0::MemRead 185747611 17.20% 84.26% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 169152555 15.67% 99.93% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 112557 0.01% 99.94% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 660881 0.06% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 1079705427 # Class of committed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16794 # number of quiesce instructions executed
-system.cpu.tickCycles 1555844114 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 757001531 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 11832637 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.995677 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 345046750 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 11833149 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.159335 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 456752500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.995677 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999992 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1449239878 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1449239878 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 176307264 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 176307264 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 158900158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 158900158 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 537417 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 537417 # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data 337852 # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total 337852 # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4300418 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4300418 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4627725 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4627725 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 335545274 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 335545274 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 336082691 # number of overall hits
-system.cpu.dcache.overall_hits::total 336082691 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 6490291 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 6490291 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 4646590 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 4646590 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1620869 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1620869 # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data 1254011 # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total 1254011 # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 329077 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 329077 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 12390892 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 12390892 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 14011761 # number of overall misses
-system.cpu.dcache.overall_misses::total 14011761 # number of overall misses
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-system.cpu.dcache.demand_miss_latency::total 339352442999 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_mshr_uncacheable_misses::total 67228 # number of overall MSHR uncacheable misses
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6209488500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553 # average ReadReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153 # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153 # average WriteLineReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421 # average overall mshr uncacheable latency
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-system.cpu.icache.tags.replacements 25121901 # number of replacements
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-system.cpu.icache.tags.sampled_refs 25122413 # Sample count of references to valid blocks.
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.icache.tags.data_accesses 391979921 # Number of data accesses
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-system.cpu.icache.overall_avg_miss_latency::total 13428.664385 # average overall miss latency
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 7955.769070 # Average occupied blocks per requestor
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-system.cpu.l2cache.demand_mshr_misses::total 1350922 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7529 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6105 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 109824 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1227464 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1350922 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 37899 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71519 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 801715000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 583775000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1385490000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76139500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76139500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 71929817502 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 71929817502 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10594574503 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10594574503 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36650353047 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36650353047 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11657372001 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11657372001 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 801715000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 583775000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10594574503 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108580170549 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 120560235052 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 801715000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 583775000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10594574503 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 120560235052 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 299820000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5789264500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6089084500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 299820000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5789264500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6089084500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111080 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111080 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.337030 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.337030 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004372 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045792 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045792 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.451358 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.451358 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.036514 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.036514 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 74678701 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 37723093 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4208 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1985 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1985 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 1826986 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 34978302 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33620 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33620 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 10621415 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 25121901 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 3034475 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 35914 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 35915 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2551242 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2551242 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 25122423 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 8030982 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1284314 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1253880 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75375327 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35706122 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 683214 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2401023 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 114165686 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3215911232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1257073518 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2170984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 8190216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 4483345950 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 2351379 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 104018568 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 40708735 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.018149 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.133491 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 39969899 98.19% 98.19% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 738836 1.81% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 40708735 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 72100713496 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1533365 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 37694541038 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 16565349400 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 411872936 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1377265960 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40237 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40237 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136485 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136485 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353444 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 37126500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25225000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36490500 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 569036756 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115484 # number of replacements
-system.iocache.tags.tagsinuse 10.444243 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13137487927000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 5.867221 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 4.577022 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.366701 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.286064 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.652765 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039875 # Number of tag accesses
-system.iocache.tags.data_accesses 1039875 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115502 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115542 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115502 # number of overall misses
-system.iocache.overall_misses::total 115542 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 2014766150 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 2019852150 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13376583606 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13376583606 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15391349756 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15396786756 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15391349756 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15396786756 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115502 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115542 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115502 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115542 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 227588.974648 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125408.606521 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 133257.055928 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 133257.055928 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 51744 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3369 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 15.358860 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106631 # number of writebacks
-system.iocache.writebacks::total 106631 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115502 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115542 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115502 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115542 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1572866150 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1576102150 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8037847459 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8037847459 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 9610713609 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9614150609 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 9610713609 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9614150609 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 3974449 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 1973040 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 37899 # Transaction distribution
-system.membus.trans_dist::ReadResp 537851 # Transaction distribution
-system.membus.trans_dist::WriteReq 33620 # Transaction distribution
-system.membus.trans_dist::WriteResp 33620 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1669378 # Transaction distribution
-system.membus.trans_dist::CleanEvict 268224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
-system.membus.trans_dist::ReadExReq 859285 # Transaction distribution
-system.membus.trans_dist::ReadExResp 859285 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 499952 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 672599 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 30234 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6910 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5106407 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5235709 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237223 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237223 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5472932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13820 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186691628 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186861678 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 194082670 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 33575 # Total snoops (count)
-system.membus.snoopTraffic 213376 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2107909 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.016147 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.126040 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2073873 98.39% 98.39% # Request fanout histogram
-system.membus.snoop_fanout::1 34036 1.61% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2107909 # Request fanout histogram
-system.membus.reqLayer0.occupancy 99276000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5601000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10934593718 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 7287611424 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 76573457 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000027] Console: colour dummy device 80x25\r
-[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000032] pid_max: default: 32768 minimum: 301\r
-[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000181] hw perfevents: no hardware support available\r
-[ 1.060097] CPU1: failed to come online\r
-[ 2.080187] CPU2: failed to come online\r
-[ 3.100278] CPU3: failed to come online\r
-[ 3.100281] Brought up 1 CPUs\r
-[ 3.100283] SMP: Total of 1 processors activated.\r
-[ 3.100354] devtmpfs: initialized\r
-[ 3.100991] atomic64_test: passed\r
-[ 3.101046] regulator-dummy: no parameters\r
-[ 3.101555] NET: Registered protocol family 16\r
-[ 3.101721] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101732] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.102038] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.102043] Serial: AMBA PL011 UART driver\r
-[ 3.102290] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.102335] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102901] console [ttyAMA0] enabled\r
-[ 3.103000] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.103038] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.103076] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.103112] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130703] 3V3: 3300 mV \r
-[ 3.130755] vgaarb: loaded\r
-[ 3.130815] SCSI subsystem initialized\r
-[ 3.130867] libata version 3.00 loaded.\r
-[ 3.130924] usbcore: registered new interface driver usbfs\r
-[ 3.130945] usbcore: registered new interface driver hub\r
-[ 3.130986] usbcore: registered new device driver usb\r
-[ 3.131018] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131047] PTP clock support registered\r
-[ 3.131197] Switched to clocksource arch_sys_counter\r
-[ 3.132637] NET: Registered protocol family 2\r
-[ 3.132735] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.132757] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.132784] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.132801] TCP: reno registered\r
-[ 3.132809] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132824] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132871] NET: Registered protocol family 1\r
-[ 3.132921] RPC: Registered named UNIX socket transport module.\r
-[ 3.132932] RPC: Registered udp transport module.\r
-[ 3.132940] RPC: Registered tcp transport module.\r
-[ 3.132948] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132961] PCI: CLS 0 bytes, default 64\r
-[ 3.133158] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.133307] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.135503] fuse init (API version 7.23)\r
-[ 3.135611] msgmni has been set to 469\r
-[ 3.138767] io scheduler noop registered\r
-[ 3.138836] io scheduler cfq registered (default)\r
-[ 3.139309] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.139322] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.139334] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.139347] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.139357] pci_bus 0000:00: scanning bus\r
-[ 3.139369] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.139383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.139398] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139443] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.139455] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.139467] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.139478] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.139489] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.139501] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.139513] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139555] pci_bus 0000:00: fixups for bus\r
-[ 3.139564] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.139576] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.139598] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.139607] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.139619] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.139628] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.139641] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.139654] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.139668] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.139681] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.139693] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.139705] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.139717] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.139729] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.140375] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.140706] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.140717] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.140741] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.141104] scsi0 : ata_piix\r
-[ 3.141497] scsi1 : ata_piix\r
-[ 3.141534] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.141547] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.141673] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.141686] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.141703] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.141715] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301229] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301240] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301271] ata1.00: configured for UDMA/33\r
-[ 3.301328] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.301469] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.301499] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.301548] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.301558] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.301583] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.301736] sda: sda1\r
-[ 3.301887] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.421517] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.421531] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.421555] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.421565] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.421589] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.421601] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.421690] usbcore: registered new interface driver usb-storage\r
-[ 3.421758] mousedev: PS/2 mouse device common for all mice\r
-[ 3.421951] usbcore: registered new interface driver usbhid\r
-[ 3.421962] usbhid: USB HID core driver\r
-[ 3.421997] TCP: cubic registered\r
-[ 3.422006] NET: Registered protocol family 17\r
-\0[ 3.422432] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.422472] devtmpfs: mounted\r
-[ 3.422501] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.464513] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.604760] random: dd urandom read with 21 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.771432] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu0.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu0.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
-eventq_index=0
-
-[system.cpu0.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList0.opList
-
-[system.cpu0.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2
-
-[system.cpu0.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu0.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList
-
-[system.cpu0.fuPool.FUList2.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList3]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList
-
-[system.cpu0.fuPool.FUList3.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
-
-[system.cpu0.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu0.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu0.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu0.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu1.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=1
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu1.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
-eventq_index=0
-
-[system.cpu1.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList0.opList
-
-[system.cpu1.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
-
-[system.cpu1.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu1.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList
-
-[system.cpu1.fuPool.FUList2.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList3]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList
-
-[system.cpu1.fuPool.FUList3.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
-
-[system.cpu1.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu1.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu1.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu1.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: allocating bonus target for snoop
-warn: allocating bonus target for snoop
-warn: allocating bonus target for snoop
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:00
-gem5 executing on e108600-lin, pid 17330
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47384942719000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.341923 # Number of seconds simulated
-sim_ticks 47341923254000 # Number of ticks simulated
-final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 198941 # Simulator instruction rate (inst/s)
-host_op_rate 237233 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10723675807 # Simulator tick rate (ticks/s)
-host_mem_usage 786956 # Number of bytes of host memory used
-host_seconds 4414.71 # Real time elapsed on the host
-sim_insts 878265186 # Number of instructions simulated
-sim_ops 1047316960 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1277902 # Number of read requests accepted
-system.physmem.writeReqs 1529475 # Number of write requests accepted
-system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue
-system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 74308 # Per bank write bursts
-system.physmem.perBankRdBursts::1 87985 # Per bank write bursts
-system.physmem.perBankRdBursts::2 79775 # Per bank write bursts
-system.physmem.perBankRdBursts::3 80704 # Per bank write bursts
-system.physmem.perBankRdBursts::4 79279 # Per bank write bursts
-system.physmem.perBankRdBursts::5 87661 # Per bank write bursts
-system.physmem.perBankRdBursts::6 78349 # Per bank write bursts
-system.physmem.perBankRdBursts::7 78833 # Per bank write bursts
-system.physmem.perBankRdBursts::8 69442 # Per bank write bursts
-system.physmem.perBankRdBursts::9 78370 # Per bank write bursts
-system.physmem.perBankRdBursts::10 69793 # Per bank write bursts
-system.physmem.perBankRdBursts::11 81996 # Per bank write bursts
-system.physmem.perBankRdBursts::12 80451 # Per bank write bursts
-system.physmem.perBankRdBursts::13 82396 # Per bank write bursts
-system.physmem.perBankRdBursts::14 80116 # Per bank write bursts
-system.physmem.perBankRdBursts::15 88030 # Per bank write bursts
-system.physmem.perBankWrBursts::0 92185 # Per bank write bursts
-system.physmem.perBankWrBursts::1 101129 # Per bank write bursts
-system.physmem.perBankWrBursts::2 94103 # Per bank write bursts
-system.physmem.perBankWrBursts::3 97328 # Per bank write bursts
-system.physmem.perBankWrBursts::4 94264 # Per bank write bursts
-system.physmem.perBankWrBursts::5 99023 # Per bank write bursts
-system.physmem.perBankWrBursts::6 94391 # Per bank write bursts
-system.physmem.perBankWrBursts::7 95568 # Per bank write bursts
-system.physmem.perBankWrBursts::8 90026 # Per bank write bursts
-system.physmem.perBankWrBursts::9 95851 # Per bank write bursts
-system.physmem.perBankWrBursts::10 88927 # Per bank write bursts
-system.physmem.perBankWrBursts::11 96294 # Per bank write bursts
-system.physmem.perBankWrBursts::12 94934 # Per bank write bursts
-system.physmem.perBankWrBursts::13 97047 # Per bank write bursts
-system.physmem.perBankWrBursts::14 95210 # Per bank write bursts
-system.physmem.perBankWrBursts::15 100911 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry
-system.physmem.totGap 47341921675500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 25 # Read request sizes (log2)
-system.physmem.readPktSize::4 2133 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1275744 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 2 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1526901 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads
-system.physmem.totQLat 79629370316 # Total ticks spent queuing
-system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing
-system.physmem.readRowHits 958718 # Number of row buffer hits during reads
-system.physmem.writeRowHits 675564 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes
-system.physmem.avgGap 16863400.13 # Average gap between requests
-system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ)
-system.physmem_0.averagePower 242.399417 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states
-system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states
-system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ)
-system.physmem_1.averagePower 242.420579 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 135771616 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 656993 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 107772870 # DTB read hits
-system.cpu0.dtb.read_misses 484010 # DTB read misses
-system.cpu0.dtb.write_hits 87417439 # DTB write hits
-system.cpu0.dtb.write_misses 172983 # DTB write misses
-system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 108256880 # DTB read accesses
-system.cpu0.dtb.write_accesses 87590422 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 195190309 # DTB hits
-system.cpu0.dtb.misses 656993 # DTB misses
-system.cpu0.dtb.accesses 195847302 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 88518 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 209275517 # ITB inst hits
-system.cpu0.itb.inst_misses 88518 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses
-system.cpu0.itb.hits 209275517 # DTB hits
-system.cpu0.itb.misses 88518 # DTB misses
-system.cpu0.itb.accesses 209364035 # DTB accesses
-system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 671656145 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued
-system.cpu0.iq.rate 0.884706 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 135817 # number of nop insts executed
-system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 107644173 # Number of branches executed
-system.cpu0.iew.exec_stores 87417057 # Number of stores executed
-system.cpu0.iew.exec_rate 0.872488 # Inst execution rate
-system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 283557258 # num instructions producing a value
-system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 461890383 # Number of instructions committed
-system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 179586814 # Number of memory references committed
-system.cpu0.commit.loads 94510447 # Number of loads committed
-system.cpu0.commit.membars 4189650 # Number of memory barriers committed
-system.cpu0.commit.branches 102007560 # Number of branches committed
-system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 15004572 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads
-system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes
-system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 461890383 # Number of Instructions Simulated
-system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads
-system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 6620968 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits
-system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses
-system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks
-system.cpu0.dcache.writebacks::total 6621095 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 6024041 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits
-system.cpu0.icache.overall_hits::total 202652654 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses
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-system.cpu0.icache.overall_misses::total 6379961 # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency
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-system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked
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-system.cpu0.icache.writebacks::total 6024041 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits
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-system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
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-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency
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-system.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 2885626 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
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-system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses
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-system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits
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-system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
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-system.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits
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-system.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits
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-system.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits
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-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses
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-system.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses
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-system.cpu0.l2cache.ReadCleanReq_misses::total 604135 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1115532 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 1115532 # number of ReadSharedReq misses
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-system.cpu0.l2cache.InvalidateReq_misses::total 620315 # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 24436 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12223 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 604135 # number of demand (read+write) misses
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-system.cpu0.l2cache.overall_misses::cpu0.inst 604135 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 1403707 # number of overall misses
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-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 596923500 # number of ReadReq miss cycles
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total 951661000 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365355500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365355500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2010499 # number of SCUpgradeFailReq miss cycles
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-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19225466000 # number of ReadExReq miss cycles
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-system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22664217000 # number of ReadCleanReq miss cycles
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-system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46789999492 # number of ReadSharedReq miss cycles
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-system.cpu0.l2cache.InvalidateReq_miss_latency::total 209000 # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 912274000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 596923500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22664217000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data 66015465492 # number of demand (read+write) miss cycles
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-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 596923500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22664217000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data 66015465492 # number of overall miss cycles
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-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204887 # number of ReadReq accesses(hits+misses)
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-system.cpu0.l2cache.WritebackDirty_accesses::total 4337132 # number of WritebackDirty accesses(hits+misses)
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-system.cpu0.l2cache.UpgradeReq_accesses::total 266388 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202727 # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 124325317 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 580775 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 97816184 # DTB read hits
-system.cpu1.dtb.read_misses 397931 # DTB read misses
-system.cpu1.dtb.write_hits 81264416 # DTB write hits
-system.cpu1.dtb.write_misses 182844 # DTB write misses
-system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 98214115 # DTB read accesses
-system.cpu1.dtb.write_accesses 81447260 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 179080600 # DTB hits
-system.cpu1.dtb.misses 580775 # DTB misses
-system.cpu1.dtb.accesses 179661375 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 87135 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 190777093 # ITB inst hits
-system.cpu1.itb.inst_misses 87135 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses
-system.cpu1.itb.hits 190777093 # DTB hits
-system.cpu1.itb.misses 87135 # DTB misses
-system.cpu1.itb.accesses 190864228 # DTB accesses
-system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 605218102 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued
-system.cpu1.iq.rate 0.892811 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 138202 # number of nop insts executed
-system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 97312103 # Number of branches executed
-system.cpu1.iew.exec_stores 81264721 # Number of stores executed
-system.cpu1.iew.exec_rate 0.879706 # Inst execution rate
-system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 254758095 # num instructions producing a value
-system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 416374803 # Number of instructions committed
-system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 164651061 # Number of memory references committed
-system.cpu1.commit.loads 85667366 # Number of loads committed
-system.cpu1.commit.membars 3698541 # Number of memory barriers committed
-system.cpu1.commit.branches 91988554 # Number of branches committed
-system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 13152854 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads
-system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes
-system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 416374803 # Number of Instructions Simulated
-system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads
-system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 5530000 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits
-system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses
-system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks
-system.cpu1.dcache.writebacks::total 5530029 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 6156366 # number of replacements
-system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits
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-system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 184011394 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 6513585 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks
-system.cpu1.icache.writebacks::total 6156366 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits
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-system.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency
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-system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified
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-system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 2237289 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use
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-system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
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-system.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits
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-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40285 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40285 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136579 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136579 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115633 # number of replacements
-system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040946 # Number of tag accesses
-system.iocache.tags.data_accesses 1040946 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115661 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115621 # number of overall misses
-system.iocache.overall_misses::total 115661 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106710 # number of writebacks
-system.iocache.writebacks::total 106710 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 1858608 # number of replacements
-system.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use
-system.l2c.tags.total_refs 7355255 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy
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-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 40965 # Transaction distribution
-system.membus.trans_dist::ReadResp 1170673 # Transaction distribution
-system.membus.trans_dist::WriteReq 38689 # Transaction distribution
-system.membus.trans_dist::WriteResp 38689 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution
-system.membus.trans_dist::CleanEvict 301973 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 162891 # Transaction distribution
-system.membus.trans_dist::ReadExResp 148894 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 585668 # Total snoops (count)
-system.membus.snoopTraffic 182912 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2626196 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram
-system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2626196 # Request fanout histogram
-system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3295138 # Total snoops (count)
-system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000015] Console: colour dummy device 80x25\r
-[ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000018] pid_max: default: 32768 minimum: 301\r
-[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000102] hw perfevents: no hardware support available\r
-[ 0.060026] CPU1: Booted secondary processor\r
-[ 1.080049] CPU2: failed to come online\r
-[ 2.100093] CPU3: failed to come online\r
-[ 2.100095] Brought up 2 CPUs\r
-[ 2.100096] SMP: Total of 2 processors activated.\r
-[ 2.100135] devtmpfs: initialized\r
-[ 2.100443] atomic64_test: passed\r
-[ 2.100471] regulator-dummy: no parameters\r
-[ 2.100695] NET: Registered protocol family 16\r
-[ 2.100778] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.100785] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.100927] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.100930] Serial: AMBA PL011 UART driver\r
-[ 2.101048] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101072] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.101655] console [ttyAMA0] enabled\r
-[ 2.101721] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.101750] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.101779] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.101807] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140200] 3V3: 3300 mV \r
-[ 2.140234] vgaarb: loaded\r
-[ 2.140266] SCSI subsystem initialized\r
-[ 2.140287] libata version 3.00 loaded.\r
-[ 2.140319] usbcore: registered new interface driver usbfs\r
-[ 2.140334] usbcore: registered new interface driver hub\r
-[ 2.140351] usbcore: registered new device driver usb\r
-[ 2.140371] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140398] PTP clock support registered\r
-[ 2.140483] Switched to clocksource arch_sys_counter\r
-[ 2.141317] NET: Registered protocol family 2\r
-[ 2.141370] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141386] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.141401] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.141417] TCP: reno registered\r
-[ 2.141424] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141435] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141463] NET: Registered protocol family 1\r
-[ 2.141503] RPC: Registered named UNIX socket transport module.\r
-[ 2.141513] RPC: Registered udp transport module.\r
-[ 2.141522] RPC: Registered tcp transport module.\r
-[ 2.141530] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.141542] PCI: CLS 0 bytes, default 64\r
-[ 2.141648] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.141718] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.142752] fuse init (API version 7.23)\r
-[ 2.142809] msgmni has been set to 469\r
-[ 2.142890] io scheduler noop registered\r
-[ 2.142925] io scheduler cfq registered (default)\r
-[ 2.143148] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.143161] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.143172] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.143184] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.143195] pci_bus 0000:00: scanning bus\r
-[ 2.143204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.143217] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.143231] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.143270] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.143280] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.143291] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.143302] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.143312] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.143323] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143351] pci_bus 0000:00: fixups for bus\r
-[ 2.143359] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.143371] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.143388] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.143397] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.143406] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.143415] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.143425] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.143438] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.143451] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.143463] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.143475] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.143486] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.143497] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.143509] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.143798] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.143959] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.143970] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.143987] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.144155] scsi0 : ata_piix\r
-[ 2.144211] scsi1 : ata_piix\r
-[ 2.144232] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.144244] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.144315] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.144327] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.144340] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.144352] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.300506] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.300516] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.300541] ata1.00: configured for UDMA/33\r
-[ 2.300579] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.300655] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.300670] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.300700] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.300709] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.300725] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.300818] sda: sda1\r
-[ 2.300900] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.420759] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.420772] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.420790] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.420801] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.420818] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.420830] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.420879] usbcore: registered new interface driver usb-storage\r
-[ 2.420923] mousedev: PS/2 mouse device common for all mice\r
-[ 2.421032] usbcore: registered new interface driver usbhid\r
-[ 2.421042] usbhid: USB HID core driver\r
-[ 2.421068] TCP: cubic registered\r
-[ 2.421076] NET: Registered protocol family 17\r
-\0[ 2.421334] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.421363] devtmpfs: mounted\r
-[ 2.421381] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.457503] udevd[609]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.532427] random: dd urandom read with 18 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.640714] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
-Starting auto-serial-console:
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
-
-[system.cpu.fuPool.FUList2.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
-
-[system.cpu.fuPool.FUList3.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:05:44
-gem5 executing on e108600-lin, pid 17601
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51558697863000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.277959 # Number of seconds simulated
-sim_ticks 51277959410000 # Number of ticks simulated
-final_tick 51277959410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 210382 # Simulator instruction rate (inst/s)
-host_op_rate 250295 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 13357159040 # Simulator tick rate (ticks/s)
-host_mem_usage 689664 # Number of bytes of host memory used
-host_seconds 3838.99 # Real time elapsed on the host
-sim_insts 807652759 # Number of instructions simulated
-sim_ops 960879271 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 253184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 234496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5589856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 47714440 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 412800 # Number of bytes read from this memory
-system.physmem.bytes_read::total 54204776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5589856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5589856 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 74605824 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 74626404 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 3956 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3664 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 88894 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 745551 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6450 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 848515 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1165716 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1168289 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 4937 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 109011 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 930506 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1057077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 109011 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 109011 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1454930 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1455331 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1454930 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 4937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 109011 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 930907 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2512408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 848516 # Number of read requests accepted
-system.physmem.writeReqs 1168289 # Number of write requests accepted
-system.physmem.readBursts 848516 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1168289 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 54258624 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 46336 # Total number of bytes read from write queue
-system.physmem.bytesWritten 74623296 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 54204840 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 74626404 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 724 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 50870 # Per bank write bursts
-system.physmem.perBankRdBursts::1 59107 # Per bank write bursts
-system.physmem.perBankRdBursts::2 53673 # Per bank write bursts
-system.physmem.perBankRdBursts::3 52283 # Per bank write bursts
-system.physmem.perBankRdBursts::4 52009 # Per bank write bursts
-system.physmem.perBankRdBursts::5 59846 # Per bank write bursts
-system.physmem.perBankRdBursts::6 50421 # Per bank write bursts
-system.physmem.perBankRdBursts::7 52784 # Per bank write bursts
-system.physmem.perBankRdBursts::8 49319 # Per bank write bursts
-system.physmem.perBankRdBursts::9 57871 # Per bank write bursts
-system.physmem.perBankRdBursts::10 53663 # Per bank write bursts
-system.physmem.perBankRdBursts::11 59850 # Per bank write bursts
-system.physmem.perBankRdBursts::12 49313 # Per bank write bursts
-system.physmem.perBankRdBursts::13 51526 # Per bank write bursts
-system.physmem.perBankRdBursts::14 46865 # Per bank write bursts
-system.physmem.perBankRdBursts::15 48391 # Per bank write bursts
-system.physmem.perBankWrBursts::0 70028 # Per bank write bursts
-system.physmem.perBankWrBursts::1 76221 # Per bank write bursts
-system.physmem.perBankWrBursts::2 72051 # Per bank write bursts
-system.physmem.perBankWrBursts::3 73117 # Per bank write bursts
-system.physmem.perBankWrBursts::4 72572 # Per bank write bursts
-system.physmem.perBankWrBursts::5 78772 # Per bank write bursts
-system.physmem.perBankWrBursts::6 71408 # Per bank write bursts
-system.physmem.perBankWrBursts::7 73272 # Per bank write bursts
-system.physmem.perBankWrBursts::8 71515 # Per bank write bursts
-system.physmem.perBankWrBursts::9 77080 # Per bank write bursts
-system.physmem.perBankWrBursts::10 72838 # Per bank write bursts
-system.physmem.perBankWrBursts::11 77780 # Per bank write bursts
-system.physmem.perBankWrBursts::12 69170 # Per bank write bursts
-system.physmem.perBankWrBursts::13 71642 # Per bank write bursts
-system.physmem.perBankWrBursts::14 68698 # Per bank write bursts
-system.physmem.perBankWrBursts::15 69825 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 522 # Number of times write queue was full causing retry
-system.physmem.totGap 51277958025500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 13 # Read request sizes (log2)
-system.physmem.readPktSize::4 2072 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 846431 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 1 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1165716 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 541295 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 247060 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 38783 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15383 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::5 464 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::60 1772 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1419 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 718 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1155 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 505782 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 254.816375 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 152.511846 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 294.316020 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 218537 43.21% 43.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 130980 25.90% 69.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 46546 9.20% 78.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 24886 4.92% 83.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 16948 3.35% 86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 10705 2.12% 88.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8138 1.61% 90.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 6857 1.36% 91.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 42185 8.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 505782 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 52835 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 16.045538 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 23.735472 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 52822 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 8 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 3 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 52835 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 52835 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.068496 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.791739 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 25.919021 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 48708 92.19% 92.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 1351 2.56% 94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 388 0.73% 95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 806 1.53% 97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 454 0.86% 97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 263 0.50% 98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 370 0.70% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 158 0.30% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 43 0.08% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 52 0.10% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 56 0.11% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 28 0.05% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 16 0.03% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 21 0.04% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 12 0.02% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 27 0.05% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 19 0.04% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 15 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 5 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 4 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 8 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 3 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::592-607 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-623 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::624-639 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655 4 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::880-895 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::992-1007 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 52835 # Writes before turning the bus around for reads
-system.physmem.totQLat 32888008041 # Total ticks spent queuing
-system.physmem.totMemAccLat 48784089291 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4238955000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 38792.54 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 57542.52 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.06 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing
-system.physmem.readRowHits 648292 # Number of row buffer hits during reads
-system.physmem.writeRowHits 859704 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes
-system.physmem.avgGap 25425342.57 # Average gap between requests
-system.physmem.pageHitRate 74.88 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1849802640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 983185830 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3077290020 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3066442020 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 32858039760.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 30159163980 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1958344800 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 66073114650 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 46519620000 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 12231781860420 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 12418342348350 # Total energy per rank (pJ)
-system.physmem_0.averagePower 242.176999 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 51206686329778 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 3544531992 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13966174000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 50940644588000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 121144747142 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 53762327980 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 144897040886 # Time in different power states
-system.physmem_1.actEnergy 1761495120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 936256860 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2975937720 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3020020560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 32012909760.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 29684228010 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1902447840 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 63461801580 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 45299969760 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 12234156504570 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 12415225828860 # Total energy per rank (pJ)
-system.physmem_1.averagePower 242.116222 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 51207876412176 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 3424177242 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13608086000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 50950737151500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 117968786503 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 53050734582 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 139170474173 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 214792288 # Number of BP lookups
-system.cpu.branchPred.condPredicted 137846282 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12464803 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 146135265 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 84448125 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 57.787643 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 31594768 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 349324 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 6874034 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 4883721 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1990313 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 771971 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 970467 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 970467 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 18061 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 162102 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 433748 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 536719 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 2148.778970 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14488.438649 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535 533045 99.32% 99.32% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071 2702 0.50% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607 468 0.09% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143 229 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679 124 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215 18 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751 94 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359 22 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 536719 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 489559 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21856.142978 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 16984.908569 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 19510.602702 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 478829 97.81% 97.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 9216 1.88% 99.69% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 680 0.14% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 491 0.10% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 167 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 18 0.00% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 87 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 489559 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 687539152416 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.766147 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.508794 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 685391448916 99.69% 99.69% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 1144327500 0.17% 99.85% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 477284500 0.07% 99.92% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 191925000 0.03% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 139963500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 102241500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 33074500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 56365000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 2522000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 687539152416 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 162103 89.98% 89.98% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 18061 10.02% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 180164 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 970467 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 970467 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 180164 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 180164 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 1150631 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 174485449 # DTB read hits
-system.cpu.dtb.read_misses 696020 # DTB read misses
-system.cpu.dtb.write_hits 152010399 # DTB write hits
-system.cpu.dtb.write_misses 274447 # DTB write misses
-system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 74778 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 103 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10363 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 69607 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 175181469 # DTB read accesses
-system.cpu.dtb.write_accesses 152284846 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 326495848 # DTB hits
-system.cpu.dtb.misses 970467 # DTB misses
-system.cpu.dtb.accesses 327466315 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 166329 # Table walker walks requested
-system.cpu.itb.walker.walksLong 166329 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1543 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 121824 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 18039 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 148290 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 1030.507789 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 10121.197556 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-65535 147791 99.66% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-131071 435 0.29% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-196607 25 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-262143 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::524288-589823 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::589824-655359 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 148290 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 141406 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 26889.721794 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 22183.567838 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 21940.142141 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 138369 97.85% 97.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 2580 1.82% 99.68% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 191 0.14% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 150 0.11% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 49 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 141406 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 580161918016 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.951845 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.214419 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 27974300560 4.82% 4.82% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 552153156456 95.17% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 33290000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 609500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4 49000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::5 512500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 580161918016 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 121824 98.75% 98.75% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1543 1.25% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 123367 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 166329 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 166329 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123367 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 123367 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 289696 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 333977355 # ITB inst hits
-system.cpu.itb.inst_misses 166329 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 54464 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 373131 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 334143684 # ITB inst accesses
-system.cpu.itb.hits 333977355 # DTB hits
-system.cpu.itb.misses 166329 # DTB misses
-system.cpu.itb.accesses 334143684 # DTB accesses
-system.cpu.numPwrStateTransitions 32546 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 16273 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 3107516335.044798 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 60196725189.485252 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 6948 42.70% 42.70% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 9289 57.08% 99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 16273 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 709346089816 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50568613320184 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1418701600 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 626970761 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 964955706 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 214792288 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 120926614 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 712354427 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 26627776 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 3832226 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 25955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9044924 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1035738 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 1059 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333569052 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6336680 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 48713 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 1366578978 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.835386 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.187527 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 828034594 60.59% 60.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 202016384 14.78% 75.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 69979562 5.12% 80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 266548438 19.50% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1366578978 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.151401 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.680168 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 523831535 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 358407215 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 444986242 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 29823356 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9530630 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 82997397 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 3840205 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1051662188 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 29872784 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9530630 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 559062030 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 58275029 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 221284587 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 439543391 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 78883311 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1030946151 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 7084405 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 5220432 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 401053 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 689601 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 52909282 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 20659 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 944726342 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1460373617 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1214391439 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1466073 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 877604087 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 67122252 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11621737 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 7877357 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 58456344 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 178961087 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 155538156 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 10194150 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9195511 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1010975595 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 11936880 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1010573430 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3406540 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 62033200 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 34713553 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 312805 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1366578978 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.739491 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.966076 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 766524619 56.09% 56.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 278054062 20.35% 76.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 240507320 17.60% 94.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 74487645 5.45% 99.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6984867 0.51% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20465 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1366578978 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59327643 34.80% 34.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 97860 0.06% 34.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 26629 0.02% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 606 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 45774518 26.85% 61.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 64550245 37.86% 99.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 65013 0.04% 99.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 650262 0.38% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 675222587 66.82% 66.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2579661 0.26% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 123552 0.01% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 118042 0.01% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 178525210 17.67% 84.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 153211297 15.16% 99.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 117761 0.01% 99.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 674889 0.07% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1010573430 # Type of FU issued
-system.cpu.iq.rate 0.712323 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 170492776 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.168709 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3559085350 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1084154908 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 991977756 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2539803 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 933979 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 905255 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1179439202 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1626993 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 4435926 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14385160 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 15174 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 144472 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6174251 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2629445 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1524875 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9530630 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 7210038 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4323845 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1023153770 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 178961087 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 155538156 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7437223 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 69213 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4169498 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 144472 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3542728 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 5585702 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 9128430 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 998939859 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 174475303 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10677060 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 241295 # number of nop insts executed
-system.cpu.iew.exec_refs 326482764 # number of memory reference insts executed
-system.cpu.iew.exec_branches 185483896 # Number of branches executed
-system.cpu.iew.exec_stores 152007461 # Number of stores executed
-system.cpu.iew.exec_rate 0.704123 # Inst execution rate
-system.cpu.iew.wb_sent 993723823 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 992883011 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 420701773 # num instructions producing a value
-system.cpu.iew.wb_consumers 671731184 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.699853 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.626295 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 52581924 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 11624075 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8681545 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1354317292 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.709493 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.365584 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 893350952 65.96% 65.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 231145639 17.07% 83.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 123165028 9.09% 92.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 37514552 2.77% 94.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 29252763 2.16% 97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14325561 1.06% 98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8938173 0.66% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4404967 0.33% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 12219657 0.90% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1354317292 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 807652759 # Number of instructions committed
-system.cpu.commit.committedOps 960879271 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 313939831 # Number of memory references committed
-system.cpu.commit.loads 164575926 # Number of loads committed
-system.cpu.commit.membars 7185354 # Number of memory barriers committed
-system.cpu.commit.branches 178524482 # Number of branches committed
-system.cpu.commit.fp_insts 893967 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 893684330 # Number of committed integer instructions.
-system.cpu.commit.function_calls 25910780 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 644536442 67.08% 67.08% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2193608 0.23% 67.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 98465 0.01% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 8 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 13 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 21 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 110883 0.01% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 164464107 17.12% 84.44% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 148692682 15.47% 99.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 111819 0.01% 99.93% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 671223 0.07% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 960879271 # Class of committed instruction
-system.cpu.commit.bw_lim_events 12219657 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2347791153 # The number of ROB reads
-system.cpu.rob.rob_writes 2039089805 # The number of ROB writes
-system.cpu.timesIdled 8233460 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 52122622 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 101137217350 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 807652759 # Number of Instructions Simulated
-system.cpu.committedOps 960879271 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.756574 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.756574 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.569290 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.569290 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1178021092 # number of integer regfile reads
-system.cpu.int_regfile_writes 719548586 # number of integer regfile writes
-system.cpu.fp_regfile_reads 1455011 # number of floating regfile reads
-system.cpu.fp_regfile_writes 777624 # number of floating regfile writes
-system.cpu.cc_regfile_reads 183031164 # number of cc regfile reads
-system.cpu.cc_regfile_writes 183683629 # number of cc regfile writes
-system.cpu.misc_regfile_reads 2245464732 # number of misc regfile reads
-system.cpu.misc_regfile_writes 11742996 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 10097387 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.998168 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 291447803 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 10097899 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 28.862222 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 194046500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.998168 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1275104379 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1275104379 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 151424979 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 151424979 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 131950159 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 131950159 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 388682 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 388682 # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data 326177 # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total 326177 # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3459521 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3459521 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3868336 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3868336 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 283701315 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 283701315 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 284089997 # number of overall hits
-system.cpu.dcache.overall_hits::total 284089997 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 9913119 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 9913119 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 11970495 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 11970495 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1253745 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1253745 # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data 1236891 # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total 1236891 # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 459501 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 459501 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 23120505 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 23120505 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 24374250 # number of overall misses
-system.cpu.dcache.overall_misses::total 24374250 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 163455721000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 163455721000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 418494791659 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 418494791659 # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27820801905 # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total 27820801905 # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6946845500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 6946845500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 284500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 284500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 609771314564 # number of demand (read+write) miss cycles
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-system.cpu.dcache.StoreCondReq_accesses::total 3868345 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16488.828693 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16488.828693 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34960.525163 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34960.525163 # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22492.525134 # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22492.525134 # average WriteLineReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15118.238045 # average LoadLockedReq miss latency
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-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 31611.111111 # average StoreCondReq miss latency
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 225673 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_uncacheable::total 33590 # number of ReadReq MSHR uncacheable
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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 275500 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6204454000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032990 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15838.418814 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15838.418814 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33492.043115 # average WriteReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18280.776140 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21391.789248 # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21391.789248 # average WriteLineReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13907.183913 # average LoadLockedReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20904.558753 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92329.558476 # average overall mshr uncacheable latency
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-system.cpu.icache.tags.replacements 15304958 # number of replacements
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-system.cpu.icache.tags.total_refs 317502771 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15305470 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 20.744399 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 12156673500 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.tags.occ_percent::cpu.inst 0.999940 # Average percentage of cache occupancy
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 348872656 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 348872656 # Number of data accesses
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-system.cpu.icache.overall_avg_miss_latency::total 13397.928477 # average overall miss latency
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-system.cpu.icache.overall_mshr_uncacheable_latency::total 174071500 # number of overall MSHR uncacheable cycles
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 6963.202905 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst 86839 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 746739 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 841198 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 35684 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 69293 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 392212500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 345880000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 738092500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 78102500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 78102500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44854250540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44854250540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8789667055 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8789667055 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28257377566 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28257377566 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 10480376502 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 10480376502 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 392212500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 345880000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8789667055 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73111628106 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 82639387661 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 392212500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 345880000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8789667055 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73111628106 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 82639387661 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 147896500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5784421000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5932317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 147896500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5784421000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 5932317500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007008 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136873 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136873 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231159 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231159 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005674 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039477 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039477 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407427 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407427 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.033301 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.033301 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 96862.532808 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19077.308256 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19077.308256 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93768.097075 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93768.097075 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101217.967215 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101217.967215 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105286.332245 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105286.332245 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20912.486984 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20912.486984 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172206.638881 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166245.866495 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86078.974389 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85612.074813 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 51553426 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 26149596 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7713 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1993 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1993 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 1662998 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23767979 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33609 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33609 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 8824066 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 15304958 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2522010 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 29914 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 29923 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2069369 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2069369 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15305703 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6801111 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1260813 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1230062 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45920340 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30488261 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 721887 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1992767 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 79123255 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959102240 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1064742138 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2294120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6404600 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 3032543098 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1823037 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 72164080 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 28412224 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025596 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.157926 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 27684996 97.44% 97.44% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 727226 2.56% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 28412224 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 49353009980 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1469889 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22969214259 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13985386089 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 435462274 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1192643074 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40205 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40205 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136485 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136485 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7491768 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 41589500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 341500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25178000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36502000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 568968268 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147700000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115451 # number of replacements
-system.iocache.tags.tagsinuse 10.420620 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115467 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13090295539000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.547144 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.873475 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.221697 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.429592 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039587 # Number of tag accesses
-system.iocache.tags.data_accesses 1039587 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115510 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115470 # number of overall misses
-system.iocache.overall_misses::total 115510 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1876442585 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1881528585 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13387619683 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13387619683 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15264062268 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15269499268 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15264062268 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15269499268 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 213086.825460 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 212770.392966 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125512.072330 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125512.072330 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 132192.011670 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 132192.011670 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 45104 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.176746 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106630 # number of writebacks
-system.iocache.writebacks::total 106630 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8806 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115470 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115510 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115470 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115510 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1436142585 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1439378585 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8048941203 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8048941203 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 9485083788 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9488520788 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 9485083788 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9488520788 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163086.825460 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 162770.392966 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75460.710296 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75460.710296 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 2825507 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 1398744 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3574 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 35684 # Transaction distribution
-system.membus.trans_dist::ReadResp 407371 # Transaction distribution
-system.membus.trans_dist::WriteReq 33609 # Transaction distribution
-system.membus.trans_dist::WriteResp 33609 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1165716 # Transaction distribution
-system.membus.trans_dist::CleanEvict 197310 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4655 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 477795 # Transaction distribution
-system.membus.trans_dist::ReadExResp 477795 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 371688 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 607818 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 30461 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3443320 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3572590 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237411 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237411 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 3810001 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 121594060 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 121763674 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7237120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 129000794 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 33521 # Total snoops (count)
-system.membus.snoopTraffic 195328 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1531252 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.022242 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.147469 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1497194 97.78% 97.78% # Request fanout histogram
-system.membus.snoop_fanout::1 34058 2.22% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1531252 # Request fanout histogram
-system.membus.reqLayer0.occupancy 103704000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5582500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7711716413 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4552014688 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 76660254 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16273 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000019] Console: colour dummy device 80x25\r
-[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000022] pid_max: default: 32768 minimum: 301\r
-[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000120] hw perfevents: no hardware support available\r
-[ 1.060065] CPU1: failed to come online\r
-[ 2.080126] CPU2: failed to come online\r
-[ 3.100188] CPU3: failed to come online\r
-[ 3.100190] Brought up 1 CPUs\r
-[ 3.100191] SMP: Total of 1 processors activated.\r
-[ 3.100238] devtmpfs: initialized\r
-[ 3.100663] atomic64_test: passed\r
-[ 3.100701] regulator-dummy: no parameters\r
-[ 3.101063] NET: Registered protocol family 16\r
-[ 3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101347] Serial: AMBA PL011 UART driver\r
-[ 3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102115] console [ttyAMA0] enabled\r
-[ 3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130478] 3V3: 3300 mV \r
-[ 3.130515] vgaarb: loaded\r
-[ 3.130558] SCSI subsystem initialized\r
-[ 3.130595] libata version 3.00 loaded.\r
-[ 3.130635] usbcore: registered new interface driver usbfs\r
-[ 3.130652] usbcore: registered new interface driver hub\r
-[ 3.130683] usbcore: registered new device driver usb\r
-[ 3.130706] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130734] PTP clock support registered\r
-[ 3.130840] Switched to clocksource arch_sys_counter\r
-[ 3.131799] NET: Registered protocol family 2\r
-[ 3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131902] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131917] TCP: reno registered\r
-[ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131972] NET: Registered protocol family 1\r
-[ 3.132017] RPC: Registered named UNIX socket transport module.\r
-[ 3.132028] RPC: Registered udp transport module.\r
-[ 3.132036] RPC: Registered tcp transport module.\r
-[ 3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132057] PCI: CLS 0 bytes, default 64\r
-[ 3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133790] fuse init (API version 7.23)\r
-[ 3.133866] msgmni has been set to 469\r
-[ 3.135967] io scheduler noop registered\r
-[ 3.136016] io scheduler cfq registered (default)\r
-[ 3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136349] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136383] pci_bus 0000:00: scanning bus\r
-[ 3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136466] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136477] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136488] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136499] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136510] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136554] pci_bus 0000:00: fixups for bus\r
-[ 3.136562] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136592] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136601] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136611] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136620] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136682] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136693] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136705] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136716] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137373] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137403] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137653] scsi0 : ata_piix\r
-[ 3.137740] scsi1 : ata_piix\r
-[ 3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137911] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290873] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290899] ata1.00: configured for UDMA/33\r
-[ 3.290941] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.291102] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291239] sda: sda1\r
-[ 3.291342] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411268] usbcore: registered new interface driver usb-storage\r
-[ 3.411318] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411454] usbcore: registered new interface driver usbhid\r
-[ 3.411464] usbhid: USB HID core driver\r
-[ 3.411492] TCP: cubic registered\r
-[ 3.411499] NET: Registered protocol family 17\r
-\0[ 3.411807] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411840] devtmpfs: mounted\r
-[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.450256] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.603394] random: dd urandom read with 21 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.741068] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:49:27
-gem5 executing on e108600-lin, pid 23294
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47296281748500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.256223 # Number of seconds simulated
-sim_ticks 47256222864000 # Number of ticks simulated
-final_tick 47256222864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1686655 # Simulator instruction rate (inst/s)
-host_op_rate 2012712 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 87867845670 # Simulator tick rate (ticks/s)
-host_mem_usage 696856 # Number of bytes of host memory used
-host_seconds 537.81 # Real time elapsed on the host
-sim_insts 907100218 # Number of instructions simulated
-sim_ops 1082456754 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 160064 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 126784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3921972 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 37880648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 245824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 244416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3131208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 41316208 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 428544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 87455668 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3921972 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3131208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7053180 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 106476736 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 106497320 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2501 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1981 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 65688 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 591898 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3841 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 3819 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 49032 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 645582 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6696 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1371038 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1663699 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1666273 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3387 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2683 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 82994 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 801601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 5202 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 5172 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 66260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 874302 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1850670 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 82994 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 66260 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 149254 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2253179 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2253615 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2253179 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3387 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2683 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 82994 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 802037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 5202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 5172 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 66260 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 874302 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4104285 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 130714 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 130714 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 130714 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 130714 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 130714 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 100196 89.16% 89.16% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 12181 10.84% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 112377 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130714 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130714 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112377 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112377 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 243091 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 93175374 # DTB read hits
-system.cpu0.dtb.read_misses 92435 # DTB read misses
-system.cpu0.dtb.write_hits 86370526 # DTB write hits
-system.cpu0.dtb.write_misses 38279 # DTB write misses
-system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36393 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 5252 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10620 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 93267809 # DTB read accesses
-system.cpu0.dtb.write_accesses 86408805 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 179545900 # DTB hits
-system.cpu0.dtb.misses 130714 # DTB misses
-system.cpu0.dtb.accesses 179676614 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 60670 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 60670 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 60670 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 60670 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 60670 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 54534 98.81% 98.81% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 657 1.19% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 55191 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60670 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60670 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55191 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55191 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 115861 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 460432126 # ITB inst hits
-system.cpu0.itb.inst_misses 60670 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25186 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 460492796 # ITB inst accesses
-system.cpu0.itb.hits 460432126 # DTB hits
-system.cpu0.itb.misses 60670 # DTB misses
-system.cpu0.itb.accesses 460492796 # DTB accesses
-system.cpu0.numPwrStateTransitions 26581 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 13288 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 3535659625.946418 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 88810636016.861053 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 3229 24.30% 24.30% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 10032 75.50% 99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7390911651500 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 13288 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 274377754424 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46981845109576 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 94512459022 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13293 # number of quiesce instructions executed
-system.cpu0.committedInsts 460154624 # Number of instructions committed
-system.cpu0.committedOps 548413661 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 509180687 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 522850 # Number of float alu accesses
-system.cpu0.num_func_calls 28957516 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 67014933 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 509180687 # number of integer instructions
-system.cpu0.num_fp_insts 522850 # number of float instructions
-system.cpu0.num_int_register_reads 679939222 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 397756518 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 842282 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 446532 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 104721942 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 104390194 # number of times the CC registers were written
-system.cpu0.num_mem_refs 179652770 # number of memory refs
-system.cpu0.num_load_insts 93252874 # Number of load instructions
-system.cpu0.num_store_insts 86399896 # Number of store instructions
-system.cpu0.num_idle_cycles 93963703435.962769 # Number of idle cycles
-system.cpu0.num_busy_cycles 548755586.037238 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.005806 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.994194 # Percentage of idle cycles
-system.cpu0.Branches 101918794 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 367730477 67.01% 67.01% # Class of executed instruction
-system.cpu0.op_class::IntMult 1235344 0.23% 67.24% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59786 0.01% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 8 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 13 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 21 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatMisc 72659 0.01% 67.26% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu0.op_class::MemRead 93191543 16.98% 84.24% # Class of executed instruction
-system.cpu0.op_class::MemWrite 86011078 15.67% 99.92% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead 61331 0.01% 99.93% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite 388818 0.07% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 548751079 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 6361267 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 499.577143 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 173125033 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6361779 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.213305 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.577143 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975737 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.975737 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 365631383 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 365631383 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 86603750 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 86603750 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 81517458 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 81517458 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 217950 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 217950 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259225 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 259225 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2136353 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 2136353 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2100440 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 2100440 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 168380433 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 168380433 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 168598383 # number of overall hits
-system.cpu0.dcache.overall_hits::total 168598383 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3343142 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3343142 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1509525 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1509525 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 802963 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 802963 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 820079 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 820079 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119939 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 119939 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154648 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 154648 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 5672746 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 5672746 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 6475709 # number of overall misses
-system.cpu0.dcache.overall_misses::total 6475709 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 89946892 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 89946892 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 83026983 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 83026983 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1020913 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 1020913 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1079304 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 1079304 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2255088 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2255088 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 174053179 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 174053179 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 175074092 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 175074092 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037168 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.037168 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018181 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018181 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786515 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786515 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759822 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759822 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053158 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053158 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068577 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068577 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032592 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.032592 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036988 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.036988 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 6361267 # number of writebacks
-system.cpu0.dcache.writebacks::total 6361267 # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 5436488 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.989232 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 455050312 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 5437000 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 83.695110 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 5738328000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989232 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 926411639 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 926411639 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 455050312 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 455050312 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 455050312 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 455050312 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 455050312 # number of overall hits
-system.cpu0.icache.overall_hits::total 455050312 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 5437005 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 5437005 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 5437005 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 5437005 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 5437005 # number of overall misses
-system.cpu0.icache.overall_misses::total 5437005 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 460487317 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 460487317 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 460487317 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 460487317 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 460487317 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 460487317 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011807 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.011807 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011807 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.011807 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011807 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.011807 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 5436488 # number of writebacks
-system.cpu0.icache.writebacks::total 5436488 # number of writebacks
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 2619867 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15716.053325 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 9431762 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2635628 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 3.578563 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 269403000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15665.638757 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.618352 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.796216 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.956155 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001869 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001208 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.959232 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15683 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2189 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5717 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5104 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.957214 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 403271236 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 403271236 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 300949 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154418 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 455367 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 4541229 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 4541229 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 7255159 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 7255159 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 644334 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 644334 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4939776 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 4939776 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3020372 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 3020372 # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222433 # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total 222433 # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 300949 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154418 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 4939776 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 3664706 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 9059849 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 300949 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154418 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 4939776 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 3664706 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 9059849 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21207 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 31327 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134662 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 134662 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154648 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 154648 # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 730529 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 730529 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1245672 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 1245672 # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597646 # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total 597646 # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21207 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 1976201 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 2504757 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21207 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 1976201 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 2504757 # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 322156 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164538 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 486694 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4541229 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 4541229 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 7255159 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 7255159 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134662 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 134662 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154648 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 154648 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1374863 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 1374863 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5437005 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 5437005 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4266044 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 4266044 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 820079 # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total 820079 # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 322156 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164538 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 5437005 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 5640907 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 11564606 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 322156 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164538 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 5437005 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 5640907 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 11564606 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061506 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.064367 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.531347 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.531347 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091453 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091453 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.291997 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.291997 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728766 # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728766 # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061506 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091453 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350334 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.216588 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061506 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091453 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350334 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.216588 # miss rate for overall accesses
-system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.writebacks::writebacks 1595934 # number of writebacks
-system.cpu0.l2cache.writebacks::total 1595934 # number of writebacks
-system.cpu0.toL2Bus.snoop_filter.tot_requests 24251358 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12353916 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1372 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 295344 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 295344 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 597776 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 10300825 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 32321 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 32321 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 4541229 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 7256526 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 134662 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154648 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 289310 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1374863 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1374863 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5437005 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4266044 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 820079 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 820079 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16319948 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19991301 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362448 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 758854 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 37432551 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 695922452 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 768331945 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1449792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3035416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1468739605 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4809457 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 106507396 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 29250499 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.019295 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.137560 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 28686107 98.07% 98.07% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 564392 1.93% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 29250499 # Request fanout histogram
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 149830 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 149830 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 149830 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 149830 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 149830 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walksPending::samples -295973872 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -295973872 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -295973872 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 115525 88.27% 88.27% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 15355 11.73% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 130880 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 149830 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 149830 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 130880 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 130880 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 280710 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 93113840 # DTB read hits
-system.cpu1.dtb.read_misses 115970 # DTB read misses
-system.cpu1.dtb.write_hits 83725509 # DTB write hits
-system.cpu1.dtb.write_misses 33860 # DTB write misses
-system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 45912 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4582 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11647 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 93229810 # DTB read accesses
-system.cpu1.dtb.write_accesses 83759369 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 176839349 # DTB hits
-system.cpu1.dtb.misses 149830 # DTB misses
-system.cpu1.dtb.accesses 176989179 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 62588 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 62588 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 62588 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 62588 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 62588 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walksPending::samples -295974872 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -295974872 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -295974872 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 55491 99.07% 99.07% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 523 0.93% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 56014 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62588 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62588 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56014 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56014 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 118602 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 447202663 # ITB inst hits
-system.cpu1.itb.inst_misses 62588 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 32344 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 447265251 # ITB inst accesses
-system.cpu1.itb.hits 447202663 # DTB hits
-system.cpu1.itb.misses 62588 # DTB misses
-system.cpu1.itb.accesses 447265251 # DTB accesses
-system.cpu1.numPwrStateTransitions 12622 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 6311 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 7445577920.705118 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 138960729730.016388 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 4567 72.37% 72.37% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 1718 27.22% 99.59% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.67% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.05% 99.71% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.75% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.03% 99.78% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 6953792880276 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 6311 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 267180606430 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46989042257570 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 94512452040 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 6311 # number of quiesce instructions executed
-system.cpu1.committedInsts 446945594 # Number of instructions committed
-system.cpu1.committedOps 534043093 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 497796457 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 375258 # Number of float alu accesses
-system.cpu1.num_func_calls 29044812 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 64056743 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 497796457 # number of integer instructions
-system.cpu1.num_fp_insts 375258 # number of float instructions
-system.cpu1.num_int_register_reads 659899184 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 389220604 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 611056 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 302696 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 95980638 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 95700174 # number of times the CC registers were written
-system.cpu1.num_mem_refs 176965712 # number of memory refs
-system.cpu1.num_load_insts 93216701 # Number of load instructions
-system.cpu1.num_store_insts 83749011 # Number of store instructions
-system.cpu1.num_idle_cycles 93978090791.450775 # Number of idle cycles
-system.cpu1.num_busy_cycles 534361248.549225 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.005654 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.994346 # Percentage of idle cycles
-system.cpu1.Branches 98364194 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 356129610 66.65% 66.65% # Class of executed instruction
-system.cpu1.op_class::IntMult 1162336 0.22% 66.86% # Class of executed instruction
-system.cpu1.op_class::IntDiv 62196 0.01% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatMisc 36452 0.01% 66.88% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.88% # Class of executed instruction
-system.cpu1.op_class::MemRead 93166406 17.44% 84.32% # Class of executed instruction
-system.cpu1.op_class::MemWrite 83460500 15.62% 99.94% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead 50295 0.01% 99.95% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite 288511 0.05% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 534356306 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 6135169 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 439.724728 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 170720636 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 6135681 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 27.824236 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8470256211500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.724728 # Average occupied blocks per requestor
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-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 360116437 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 360116437 # Number of data accesses
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-system.cpu1.dcache.SoftPFReq_hits::total 192310 # number of SoftPFReq hits
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-system.cpu1.dcache.WriteLineReq_hits::total 67346 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2116228 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 2116228 # number of LoadLockedReq hits
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-system.cpu1.dcache.overall_hits::total 166195447 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 3476659 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1488439 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1488439 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 809340 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 809340 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 440862 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 440862 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151875 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 151875 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 156847 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 6215300 # number of overall misses
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-system.cpu1.dcache.WriteReq_accesses::total 80960527 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 1001650 # number of SoftPFReq accesses(hits+misses)
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-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 508208 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 508208 # number of WriteLineReq accesses(hits+misses)
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-system.cpu1.dcache.StoreCondReq_accesses::total 2266841 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 171409097 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 171409097 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 172410747 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.038655 # miss rate for ReadReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808007 # miss rate for SoftPFReq accesses
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-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.867483 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066961 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069192 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069192 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.writebacks::total 6135169 # number of writebacks
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-system.cpu1.icache.tags.replacements 4821762 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.439302 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 442436403 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 4822274 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 91.748499 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8470184249000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439302 # Average occupied blocks per requestor
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-system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 899339628 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 899339628 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 442436403 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 442436403 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 442436403 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 4822274 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 4822274 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 4822274 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 4822274 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 4822274 # number of overall misses
-system.cpu1.icache.overall_misses::total 4822274 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 447258677 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 447258677 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 447258677 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 447258677 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 447258677 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 447258677 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_miss_rate::total 0.010782 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::total 0.010782 # miss rate for demand accesses
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-system.cpu1.icache.writebacks::total 4821762 # number of writebacks
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 2257136 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13044.860493 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 8980176 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 2273016 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 3.950776 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 13005.388479 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.571640 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.900374 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15820 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 29 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 398 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7364 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.965576 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 376404615 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 376404615 # Number of data accesses
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-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155851 # number of ReadReq hits
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-system.cpu1.l2cache.WritebackDirty_hits::writebacks 4161473 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 4161473 # number of WritebackDirty hits
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-system.cpu1.l2cache.WritebackClean_hits::total 6795092 # number of WritebackClean hits
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-system.cpu1.l2cache.ReadExReq_hits::total 621244 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4351439 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 4351439 # number of ReadCleanReq hits
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-system.cpu1.l2cache.ReadSharedReq_hits::total 3193387 # number of ReadSharedReq hits
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-system.cpu1.l2cache.InvalidateReq_hits::total 167103 # number of InvalidateReq hits
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-system.cpu1.l2cache.demand_hits::cpu1.inst 4351439 # number of demand (read+write) hits
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-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11519 # number of ReadReq misses
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-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167370 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 4822274 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 5784434 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 11146954 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068824 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.063523 # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538644 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538644 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097638 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097638 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.280424 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.280424 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620963 # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620963 # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068824 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097638 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340535 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.222030 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068824 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097638 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340535 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.222030 # miss rate for overall accesses
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.writebacks::writebacks 1247214 # number of writebacks
-system.cpu1.l2cache.writebacks::total 1247214 # number of writebacks
-system.cpu1.toL2Bus.snoop_filter.tot_requests 22589206 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11541877 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 281509 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 281509 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 627108 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9887256 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 6357 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 6357 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4161473 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 6795458 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 141879 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156847 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 298726 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1346560 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1346560 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4822274 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4437874 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 440862 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 440862 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14466570 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19208649 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374184 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 867050 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 34916453 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617218824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 762892902 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1496736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3468200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1385076662 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4471176 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 86426880 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 27252775 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.020850 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.142882 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 26684555 97.92% 97.92% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 568220 2.08% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 27252775 # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40208 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40208 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136550 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136550 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47302 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122236 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353516 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47322 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155343 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496245 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115580 # number of replacements
-system.iocache.tags.tagsinuse 11.294790 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115596 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9107754177509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.848737 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.446053 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.240546 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.465378 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705924 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040757 # Number of tag accesses
-system.iocache.tags.data_accesses 1040757 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115600 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115640 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115600 # number of overall misses
-system.iocache.overall_misses::total 115640 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115600 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115640 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115600 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115640 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106693 # number of writebacks
-system.iocache.writebacks::total 106693 # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 2000796 # number of replacements
-system.l2c.tags.tagsinuse 65236.747854 # Cycle average of tags in use
-system.l2c.tags.total_refs 5872089 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2062236 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.847438 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 458916500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 10773.265369 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.425728 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 60.472796 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3088.117960 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 16913.790714 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 343.005231 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 383.707168 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2970.710524 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 30646.252365 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.164387 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000876 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000923 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.047121 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.258084 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005234 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.005855 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.045329 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.467625 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.995434 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 61204 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3527 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4478 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52898 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.933899 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 73224508 # Number of tag accesses
-system.l2c.tags.data_accesses 73224508 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 2843148 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 2843148 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 57335 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 51488 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 108823 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 8370 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 7752 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 16122 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 205747 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 172848 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 378595 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13551 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5506 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 436242 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 735903 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12336 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4370 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 421904 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 692405 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 2322217 # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data 112000 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data 99469 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total 211469 # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 13551 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 5506 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 436242 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 941650 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 12336 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 4370 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 421904 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 865253 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2700812 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 13551 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 5506 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 436242 # number of overall hits
-system.l2c.overall_hits::cpu0.data 941650 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 12336 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 4370 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 421904 # number of overall hits
-system.l2c.overall_hits::cpu1.data 865253 # number of overall hits
-system.l2c.overall_hits::total 2700812 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 20153 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 22374 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 42527 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 465 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1417 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 404904 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 443379 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 848283 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2501 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1981 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 60987 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 188974 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3841 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3819 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 48931 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 203657 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 514691 # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data 441546 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data 132806 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total 574352 # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 2501 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 1981 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 60987 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 593878 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 3841 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 3819 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 48931 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 647036 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1362974 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 2501 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 1981 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 60987 # number of overall misses
-system.l2c.overall_misses::cpu0.data 593878 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 3841 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 3819 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 48931 # number of overall misses
-system.l2c.overall_misses::cpu1.data 647036 # number of overall misses
-system.l2c.overall_misses::total 1362974 # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks 2843148 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 2843148 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 77488 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 73862 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 151350 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 8835 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 8704 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 17539 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 610651 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 616227 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 1226878 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16052 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7487 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 924877 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16177 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8189 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 470835 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 896062 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 2836908 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data 553546 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data 232275 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total 785821 # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 16052 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 7487 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1535528 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 16177 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 8189 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 470835 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 1512289 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 4063786 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 16052 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 7487 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1535528 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 16177 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 8189 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 470835 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 1512289 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 4063786 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260079 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.302916 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.280984 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.052632 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.109375 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.080791 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.663069 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.719506 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.691416 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.264592 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.122654 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.204323 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.466357 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.103924 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.227280 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.181427 # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data 0.797668 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data 0.571762 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total 0.730894 # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.264592 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.122654 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.386758 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.466357 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.103924 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.427852 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.335395 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.264592 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.122654 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.386758 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.466357 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.103924 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.427852 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.335395 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 1557006 # number of writebacks
-system.l2c.writebacks::total 1557006 # number of writebacks
-system.membus.snoop_filter.tot_requests 4511574 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 2519656 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3180 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 43614 # Transaction distribution
-system.membus.trans_dist::ReadResp 567214 # Transaction distribution
-system.membus.trans_dist::WriteReq 38678 # Transaction distribution
-system.membus.trans_dist::WriteResp 38678 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1663699 # Transaction distribution
-system.membus.trans_dist::CleanEvict 266504 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 223308 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 295373 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 46773 # Transaction distribution
-system.membus.trans_dist::ReadExReq 849453 # Transaction distribution
-system.membus.trans_dist::ReadExResp 845457 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 523600 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 689636 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 681080 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122236 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27410 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6276469 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 6426207 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 346860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6773067 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155343 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54820 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 186738012 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 186948379 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7398528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 194346907 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 4593865 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.007098 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.083952 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 4561256 99.29% 99.29% # Request fanout histogram
-system.membus.snoop_fanout::1 32609 0.71% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4593865 # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 11315905 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 5737208 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1831359 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 298423 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 272858 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 25565 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 43616 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3567484 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38678 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38678 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 2843148 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2033600 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 329302 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 311495 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 640797 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1403084 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1403084 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 3523868 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 871405 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 871405 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9542040 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8377604 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 17919644 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260882877 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 236654062 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 497536939 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2048171 # Total snoops (count)
-system.toL2Bus.snoopTraffic 99695936 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 13430913 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.303362 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.463832 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 9382052 69.85% 69.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 4023296 29.96% 99.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 25565 0.19% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 13430913 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 0.060015] CPU1: Booted secondary processor\r
-[ 1.080050] CPU2: failed to come online\r
-[ 2.100100] CPU3: failed to come online\r
-[ 2.100101] Brought up 2 CPUs\r
-[ 2.100102] SMP: Total of 2 processors activated.\r
-[ 2.100134] devtmpfs: initialized\r
-[ 2.100536] atomic64_test: passed\r
-[ 2.100559] regulator-dummy: no parameters\r
-[ 2.100800] NET: Registered protocol family 16\r
-[ 2.100894] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.100898] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.100937] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.100938] Serial: AMBA PL011 UART driver\r
-[ 2.101059] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101082] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.101116] console [ttyAMA0] enabled\r
-[ 2.101154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.101168] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.101183] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.101195] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140179] 3V3: 3300 mV \r
-[ 2.140202] vgaarb: loaded\r
-[ 2.140232] SCSI subsystem initialized\r
-[ 2.140246] libata version 3.00 loaded.\r
-[ 2.140272] usbcore: registered new interface driver usbfs\r
-[ 2.140279] usbcore: registered new interface driver hub\r
-[ 2.140288] usbcore: registered new device driver usb\r
-[ 2.140300] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140301] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140304] PTP clock support registered\r
-[ 2.140381] Switched to clocksource arch_sys_counter\r
-[ 2.141215] NET: Registered protocol family 2\r
-[ 2.141272] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141277] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.141282] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.141285] TCP: reno registered\r
-[ 2.141286] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141288] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141303] NET: Registered protocol family 1\r
-[ 2.141330] RPC: Registered named UNIX socket transport module.\r
-[ 2.141331] RPC: Registered udp transport module.\r
-[ 2.141331] RPC: Registered tcp transport module.\r
-[ 2.141332] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.141334] PCI: CLS 0 bytes, default 64\r
-[ 2.141433] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.141477] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.143024] fuse init (API version 7.23)\r
-[ 2.143091] msgmni has been set to 469\r
-[ 2.143142] io scheduler noop registered\r
-[ 2.143175] io scheduler cfq registered (default)\r
-[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.143452] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.143453] pci_bus 0000:00: scanning bus\r
-[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.143460] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143476] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.143483] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143503] pci_bus 0000:00: fixups for bus\r
-[ 2.143505] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.143506] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.143511] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.143512] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.143515] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.143516] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.143519] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.143520] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.143522] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.143524] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.143525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.143527] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.143529] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.143531] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.143891] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.144060] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.144062] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.144068] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.144250] scsi0 : ata_piix\r
-[ 2.144297] scsi1 : ata_piix\r
-[ 2.144314] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.144315] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.144376] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.144382] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290387] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290388] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.290395] ata1.00: configured for UDMA/33\r
-[ 2.290411] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.290465] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.290468] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.290485] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.290492] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.290547] sda: sda1\r
-[ 2.290609] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.410653] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.410661] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.410662] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.410706] usbcore: registered new interface driver usb-storage\r
-[ 2.410735] mousedev: PS/2 mouse device common for all mice\r
-[ 2.410834] usbcore: registered new interface driver usbhid\r
-[ 2.410835] usbhid: USB HID core driver\r
-[ 2.410850] TCP: cubic registered\r
-[ 2.410852] NET: Registered protocol family 17\r
-\0[ 2.411039] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.411050] devtmpfs: mounted\r
-[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.446370] udevd[609]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.521984] random: dd urandom read with 17 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.620646] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-done.\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
-Starting auto-serial-console:
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:53:59
-gem5 executing on e108600-lin, pid 23916
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51111167192000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.071102 # Number of seconds simulated
-sim_ticks 51071102402000 # Number of ticks simulated
-final_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1747137 # Simulator instruction rate (inst/s)
-host_op_rate 2084338 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 95484785421 # Simulator tick rate (ticks/s)
-host_mem_usage 679432 # Number of bytes of host memory used
-host_seconds 534.86 # Real time elapsed on the host
-sim_insts 934475925 # Number of instructions simulated
-sim_ops 1114831373 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory
-system.physmem.bytes_read::total 93979708 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 115483492 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 297729 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 192113611 # DTB read hits
-system.cpu.dtb.read_misses 218086 # DTB read misses
-system.cpu.dtb.write_hits 176013555 # DTB write hits
-system.cpu.dtb.write_misses 79643 # DTB write misses
-system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 192331697 # DTB read accesses
-system.cpu.dtb.write_accesses 176093198 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 368127166 # DTB hits
-system.cpu.dtb.misses 297729 # DTB misses
-system.cpu.dtb.accesses 368424895 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 128928 # Table walker walks requested
-system.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 935011975 # ITB inst hits
-system.cpu.itb.inst_misses 128928 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 935140903 # ITB inst accesses
-system.cpu.itb.hits 935011975 # DTB hits
-system.cpu.itb.misses 128928 # DTB misses
-system.cpu.itb.accesses 935140903 # DTB accesses
-system.cpu.numPwrStateTransitions 33906 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 102142221758 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed
-system.cpu.committedInsts 934475925 # Number of instructions committed
-system.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses
-system.cpu.num_func_calls 59056085 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1036744712 # number of integer instructions
-system.cpu.num_fp_insts 878021 # number of float instructions
-system.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read
-system.cpu.num_int_register_writes 809399347 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 747664 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written
-system.cpu.num_mem_refs 368379179 # number of memory refs
-system.cpu.num_load_insts 192305014 # Number of load instructions
-system.cpu.num_store_insts 176074165 # Number of store instructions
-system.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles
-system.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles
-system.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.989079 # Percentage of idle cycles
-system.cpu.Branches 206489174 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction
-system.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction
-system.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction
-system.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction
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-system.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction
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-system.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks
-system.cpu.l2cache.writebacks::total 1697477 # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1977015 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40168 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40168 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136429 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136429 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115471 # number of replacements
-system.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039758 # Number of tag accesses
-system.iocache.tags.data_accesses 1039758 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8862 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115529 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115489 # number of overall misses
-system.iocache.overall_misses::total 115529 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106631 # number of writebacks
-system.iocache.writebacks::total 106631 # number of writebacks
-system.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 38191 # Transaction distribution
-system.membus.trans_dist::ReadResp 527322 # Transaction distribution
-system.membus.trans_dist::WriteReq 33519 # Transaction distribution
-system.membus.trans_dist::WriteResp 33519 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution
-system.membus.trans_dist::CleanEvict 249631 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4439 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4440 # Transaction distribution
-system.membus.trans_dist::ReadExReq 981656 # Transaction distribution
-system.membus.trans_dist::ReadExResp 981656 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 677491 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 677491 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 4278167 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.008735 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram
-system.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4278167 # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 1.060049] CPU1: failed to come online\r
-[ 2.080098] CPU2: failed to come online\r
-[ 3.100148] CPU3: failed to come online\r
-[ 3.100150] Brought up 1 CPUs\r
-[ 3.100151] SMP: Total of 1 processors activated.\r
-[ 3.100177] devtmpfs: initialized\r
-[ 3.100579] atomic64_test: passed\r
-[ 3.100603] regulator-dummy: no parameters\r
-[ 3.100844] NET: Registered protocol family 16\r
-[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.100981] Serial: AMBA PL011 UART driver\r
-[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101160] console [ttyAMA0] enabled\r
-[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130356] 3V3: 3300 mV \r
-[ 3.130377] vgaarb: loaded\r
-[ 3.130406] SCSI subsystem initialized\r
-[ 3.130425] libata version 3.00 loaded.\r
-[ 3.130450] usbcore: registered new interface driver usbfs\r
-[ 3.130457] usbcore: registered new interface driver hub\r
-[ 3.130471] usbcore: registered new device driver usb\r
-[ 3.130482] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130487] PTP clock support registered\r
-[ 3.130559] Switched to clocksource arch_sys_counter\r
-[ 3.131204] NET: Registered protocol family 2\r
-[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131263] TCP: reno registered\r
-[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131281] NET: Registered protocol family 1\r
-[ 3.131311] RPC: Registered named UNIX socket transport module.\r
-[ 3.131311] RPC: Registered udp transport module.\r
-[ 3.131312] RPC: Registered tcp transport module.\r
-[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131315] PCI: CLS 0 bytes, default 64\r
-[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.132687] fuse init (API version 7.23)\r
-[ 3.132738] msgmni has been set to 469\r
-[ 3.133992] io scheduler noop registered\r
-[ 3.134025] io scheduler cfq registered (default)\r
-[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.134302] pci_bus 0000:00: scanning bus\r
-[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134354] pci_bus 0000:00: fixups for bus\r
-[ 3.134355] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.134362] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.134363] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.134366] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.134367] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.134813] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.135009] scsi0 : ata_piix\r
-[ 3.135063] scsi1 : ata_piix\r
-[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.135150] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290572] ata1.00: configured for UDMA/33\r
-[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290733] sda: sda1\r
-[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.410886] usbcore: registered new interface driver usb-storage\r
-[ 3.410912] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411009] usbcore: registered new interface driver usbhid\r
-[ 3.411010] usbhid: USB HID core driver\r
-[ 3.411025] TCP: cubic registered\r
-[ 3.411026] NET: Registered protocol family 17\r
-\0[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411214] devtmpfs: mounted\r
-[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.446950] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.532262] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.701968
-sim_ticks 47701967881000
-final_tick 47701967881000
-sim_freq 1000000000000
-host_inst_rate 169263
-host_op_rate 201687
-host_tick_rate 9441246628
-host_mem_usage 1351660
-host_seconds 5052.51
-sim_insts 855204516
-sim_ops 1019023572
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 47701967881000
-system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 60133632
-system.mem_ctrls0.bytes_read::total 60133632
-system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 45711488
-system.mem_ctrls0.bytes_written::total 45711488
-system.mem_ctrls0.num_reads::ruby.dir_cntrl0 939588
-system.mem_ctrls0.num_reads::total 939588
-system.mem_ctrls0.num_writes::ruby.dir_cntrl0 714242
-system.mem_ctrls0.num_writes::total 714242
-system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1260611
-system.mem_ctrls0.bw_read::total 1260611
-system.mem_ctrls0.bw_write::ruby.dir_cntrl0 958273
-system.mem_ctrls0.bw_write::total 958273
-system.mem_ctrls0.bw_total::ruby.dir_cntrl0 2218884
-system.mem_ctrls0.bw_total::total 2218884
-system.mem_ctrls0.readReqs 939588
-system.mem_ctrls0.writeReqs 714242
-system.mem_ctrls0.readBursts 939588
-system.mem_ctrls0.writeBursts 714242
-system.mem_ctrls0.bytesReadDRAM 60043648
-system.mem_ctrls0.bytesReadWrQ 89984
-system.mem_ctrls0.bytesWritten 45709184
-system.mem_ctrls0.bytesReadSys 60133632
-system.mem_ctrls0.bytesWrittenSys 45711488
-system.mem_ctrls0.servicedByWrQ 1406
-system.mem_ctrls0.mergedWrBursts 6
-system.mem_ctrls0.neitherReadNorWriteReqs 0
-system.mem_ctrls0.perBankRdBursts::0 53584
-system.mem_ctrls0.perBankRdBursts::1 60253
-system.mem_ctrls0.perBankRdBursts::2 66103
-system.mem_ctrls0.perBankRdBursts::3 60855
-system.mem_ctrls0.perBankRdBursts::4 61195
-system.mem_ctrls0.perBankRdBursts::5 63337
-system.mem_ctrls0.perBankRdBursts::6 56073
-system.mem_ctrls0.perBankRdBursts::7 58711
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-system.mem_ctrls0.bytesPerActivate::256-383 34205 5.94% 87.85%
-system.mem_ctrls0.bytesPerActivate::384-511 15826 2.75% 90.60%
-system.mem_ctrls0.bytesPerActivate::512-639 8058 1.40% 92.00%
-system.mem_ctrls0.bytesPerActivate::640-767 5353 0.93% 92.93%
-system.mem_ctrls0.bytesPerActivate::768-895 4563 0.79% 93.72%
-system.mem_ctrls0.bytesPerActivate::896-1023 4048 0.70% 94.42%
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-system.mem_ctrls0.rdPerTurnAround::samples 39552
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-system.mem_ctrls0.rdPerTurnAround::27648-28671 1 0.00% 100.00%
-system.mem_ctrls0.rdPerTurnAround::total 39552
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-system.mem_ctrls0.wrPerTurnAround::17 856 2.16% 21.76%
-system.mem_ctrls0.wrPerTurnAround::18 23854 60.31% 82.07%
-system.mem_ctrls0.wrPerTurnAround::19 3880 9.81% 91.88%
-system.mem_ctrls0.wrPerTurnAround::20 1380 3.49% 95.37%
-system.mem_ctrls0.wrPerTurnAround::21 483 1.22% 96.59%
-system.mem_ctrls0.wrPerTurnAround::22 626 1.58% 98.17%
-system.mem_ctrls0.wrPerTurnAround::23 177 0.45% 98.62%
-system.mem_ctrls0.wrPerTurnAround::24 65 0.16% 98.79%
-system.mem_ctrls0.wrPerTurnAround::25 143 0.36% 99.15%
-system.mem_ctrls0.wrPerTurnAround::26 26 0.07% 99.21%
-system.mem_ctrls0.wrPerTurnAround::27 18 0.05% 99.26%
-system.mem_ctrls0.wrPerTurnAround::28 13 0.03% 99.29%
-system.mem_ctrls0.wrPerTurnAround::29 19 0.05% 99.34%
-system.mem_ctrls0.wrPerTurnAround::30 24 0.06% 99.40%
-system.mem_ctrls0.wrPerTurnAround::31 11 0.03% 99.43%
-system.mem_ctrls0.wrPerTurnAround::32 23 0.06% 99.49%
-system.mem_ctrls0.wrPerTurnAround::33 30 0.08% 99.56%
-system.mem_ctrls0.wrPerTurnAround::34 28 0.07% 99.63%
-system.mem_ctrls0.wrPerTurnAround::35 11 0.03% 99.66%
-system.mem_ctrls0.wrPerTurnAround::36 19 0.05% 99.71%
-system.mem_ctrls0.wrPerTurnAround::37 12 0.03% 99.74%
-system.mem_ctrls0.wrPerTurnAround::38 10 0.03% 99.76%
-system.mem_ctrls0.wrPerTurnAround::39 9 0.02% 99.79%
-system.mem_ctrls0.wrPerTurnAround::40 7 0.02% 99.81%
-system.mem_ctrls0.wrPerTurnAround::41 8 0.02% 99.83%
-system.mem_ctrls0.wrPerTurnAround::42 8 0.02% 99.85%
-system.mem_ctrls0.wrPerTurnAround::43 12 0.03% 99.88%
-system.mem_ctrls0.wrPerTurnAround::44 9 0.02% 99.90%
-system.mem_ctrls0.wrPerTurnAround::45 6 0.02% 99.91%
-system.mem_ctrls0.wrPerTurnAround::46 12 0.03% 99.94%
-system.mem_ctrls0.wrPerTurnAround::47 5 0.01% 99.96%
-system.mem_ctrls0.wrPerTurnAround::48 7 0.02% 99.97%
-system.mem_ctrls0.wrPerTurnAround::49 4 0.01% 99.98%
-system.mem_ctrls0.wrPerTurnAround::50 2 0.01% 99.99%
-system.mem_ctrls0.wrPerTurnAround::52 1 0.00% 99.99%
-system.mem_ctrls0.wrPerTurnAround::55 1 0.00% 99.99%
-system.mem_ctrls0.wrPerTurnAround::56 1 0.00% 100.00%
-system.mem_ctrls0.wrPerTurnAround::57 1 0.00% 100.00%
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-system.mem_ctrls1.bytesPerActivate::384-511 15434 2.72% 90.57%
-system.mem_ctrls1.bytesPerActivate::512-639 7903 1.39% 91.96%
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-system.mem_ctrls1.wrPerTurnAround::samples 39168
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-system.mem_ctrls1.wrPerTurnAround::17 837 2.14% 20.85%
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-system.mem_ctrls1.wrPerTurnAround::21 491 1.25% 96.59%
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-system.mem_ctrls1.wrPerTurnAround::26 10 0.03% 99.17%
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-system.mem_ctrls1.wrPerTurnAround::46 4 0.01% 99.95%
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-system.mem_ctrls1.wrPerTurnAround::total 39168
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-system.ruby.Directory_Controller.GETS | 245019 51.79% 51.79% | 228107 48.21% 100.00%
-system.ruby.Directory_Controller.GETS::total 473126
-system.ruby.Directory_Controller.PUTX | 660729 50.23% 50.23% | 654766 49.77% 100.00%
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-system.ruby.Directory_Controller.PUTO_SHARERS | 18 46.15% 46.15% | 21 53.85% 100.00%
-system.ruby.Directory_Controller.PUTO_SHARERS::total 39
-system.ruby.Directory_Controller.Unblock | 157675 52.25% 52.25% | 144082 47.75% 100.00%
-system.ruby.Directory_Controller.Unblock::total 301757
-system.ruby.Directory_Controller.Last_Unblock | 87343 50.97% 50.97% | 84025 49.03% 100.00%
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-system.ruby.Directory_Controller.Exclusive_Unblock | 744913 50.20% 50.20% | 739060 49.80% 100.00%
-system.ruby.Directory_Controller.Exclusive_Unblock::total 1483973
-system.ruby.Directory_Controller.Dirty_Writeback | 660747 50.23% 50.23% | 654787 49.77% 100.00%
-system.ruby.Directory_Controller.Dirty_Writeback::total 1315534
-system.ruby.Directory_Controller.Memory_Data | 939588 50.61% 50.61% | 916820 49.39% 100.00%
-system.ruby.Directory_Controller.Memory_Data::total 1856408
-system.ruby.Directory_Controller.Memory_Ack | 714242 50.21% 50.21% | 708279 49.79% 100.00%
-system.ruby.Directory_Controller.Memory_Ack::total 1422521
-system.ruby.Directory_Controller.DMA_READ | 4906 54.93% 54.93% | 4025 45.07% 100.00%
-system.ruby.Directory_Controller.DMA_READ::total 8931
-system.ruby.Directory_Controller.DMA_WRITE | 53497 50.00% 50.00% | 53492 50.00% 100.00%
-system.ruby.Directory_Controller.DMA_WRITE::total 106989
-system.ruby.Directory_Controller.DMA_ACK | 1558 69.68% 69.68% | 678 30.32% 100.00%
-system.ruby.Directory_Controller.DMA_ACK::total 2236
-system.ruby.Directory_Controller.Data | 13410 49.88% 49.88% | 13476 50.12% 100.00%
-system.ruby.Directory_Controller.Data::total 26886
-system.ruby.Directory_Controller.I.GETX | 580218 49.67% 49.67% | 588017 50.33% 100.00%
-system.ruby.Directory_Controller.I.GETX::total 1168235
-system.ruby.Directory_Controller.I.GETS | 157676 52.25% 52.25% | 144082 47.75% 100.00%
-system.ruby.Directory_Controller.I.GETS::total 301758
-system.ruby.Directory_Controller.I.Memory_Ack | 660852 50.23% 50.23% | 654874 49.77% 100.00%
-system.ruby.Directory_Controller.I.Memory_Ack::total 1315726
-system.ruby.Directory_Controller.I.DMA_READ | 3151 50.05% 50.05% | 3145 49.95% 100.00%
-system.ruby.Directory_Controller.I.DMA_READ::total 6296
-system.ruby.Directory_Controller.I.DMA_WRITE | 39898 50.07% 50.07% | 39790 49.93% 100.00%
-system.ruby.Directory_Controller.I.DMA_WRITE::total 79688
-system.ruby.Directory_Controller.S.GETX | 111200 53.27% 53.27% | 97551 46.73% 100.00%
-system.ruby.Directory_Controller.S.GETX::total 208751
-system.ruby.Directory_Controller.S.GETS | 87343 50.97% 50.97% | 84025 49.03% 100.00%
-system.ruby.Directory_Controller.S.GETS::total 171368
-system.ruby.Directory_Controller.S.Memory_Ack | 18 46.15% 46.15% | 21 53.85% 100.00%
-system.ruby.Directory_Controller.S.Memory_Ack::total 39
-system.ruby.Directory_Controller.S.DMA_READ | 197 49.37% 49.37% | 202 50.63% 100.00%
-system.ruby.Directory_Controller.S.DMA_READ::total 399
-system.ruby.Directory_Controller.S.DMA_WRITE | 187 45.28% 45.28% | 226 54.72% 100.00%
-system.ruby.Directory_Controller.S.DMA_WRITE::total 413
-system.ruby.Directory_Controller.M.PUTX | 660729 50.23% 50.23% | 654766 49.77% 100.00%
-system.ruby.Directory_Controller.M.PUTX::total 1315495
-system.ruby.Directory_Controller.M.PUTO_SHARERS | 18 46.15% 46.15% | 21 53.85% 100.00%
-system.ruby.Directory_Controller.M.PUTO_SHARERS::total 39
-system.ruby.Directory_Controller.M.DMA_READ | 1558 69.68% 69.68% | 678 30.32% 100.00%
-system.ruby.Directory_Controller.M.DMA_READ::total 2236
-system.ruby.Directory_Controller.M.DMA_WRITE | 13410 49.88% 49.88% | 13476 50.12% 100.00%
-system.ruby.Directory_Controller.M.DMA_WRITE::total 26886
-system.ruby.Directory_Controller.IS.Unblock | 157675 52.25% 52.25% | 144082 47.75% 100.00%
-system.ruby.Directory_Controller.IS.Unblock::total 301757
-system.ruby.Directory_Controller.IS.Memory_Data | 157676 52.25% 52.25% | 144082 47.75% 100.00%
-system.ruby.Directory_Controller.IS.Memory_Data::total 301758
-system.ruby.Directory_Controller.IS.Memory_Ack | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory_Controller.IS.Memory_Ack::total 1
-system.ruby.Directory_Controller.SS.Last_Unblock | 87343 50.97% 50.97% | 84025 49.03% 100.00%
-system.ruby.Directory_Controller.SS.Last_Unblock::total 171368
-system.ruby.Directory_Controller.SS.Memory_Data | 87343 50.97% 50.97% | 84025 49.03% 100.00%
-system.ruby.Directory_Controller.SS.Memory_Data::total 171368
-system.ruby.Directory_Controller.MM.Exclusive_Unblock | 691418 50.21% 50.21% | 685568 49.79% 100.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 1376986
-system.ruby.Directory_Controller.MM.Memory_Data | 691418 50.21% 50.21% | 685568 49.79% 100.00%
-system.ruby.Directory_Controller.MM.Memory_Data::total 1376986
-system.ruby.Directory_Controller.MI.Dirty_Writeback | 660729 50.23% 50.23% | 654766 49.77% 100.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback::total 1315495
-system.ruby.Directory_Controller.MI.DMA_WRITE | 2 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory_Controller.MI.DMA_WRITE::total 2
-system.ruby.Directory_Controller.MIS.Dirty_Writeback | 18 46.15% 46.15% | 21 53.85% 100.00%
-system.ruby.Directory_Controller.MIS.Dirty_Writeback::total 39
-system.ruby.Directory_Controller.XI_M.Memory_Data | 3151 50.05% 50.05% | 3145 49.95% 100.00%
-system.ruby.Directory_Controller.XI_M.Memory_Data::total 6296
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 53495 50.00% 50.00% | 53492 50.00% 100.00%
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 106987
-system.ruby.Directory_Controller.XI_U.Memory_Ack | 53371 49.99% 49.99% | 53384 50.01% 100.00%
-system.ruby.Directory_Controller.XI_U.Memory_Ack::total 106755
-system.ruby.Directory_Controller.OI_D.Data | 13410 49.88% 49.88% | 13476 50.12% 100.00%
-system.ruby.Directory_Controller.OI_D.Data::total 26886
-system.ruby.Directory_Controller.MD.DMA_ACK | 1558 69.68% 69.68% | 678 30.32% 100.00%
-system.ruby.Directory_Controller.MD.DMA_ACK::total 2236
-system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 250301 99.92% 99.92% | 202 0.08% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 250503
-system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3309822 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.WriteRequest::total 3309825
-system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 8931
-system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.DMA_Ack::total 106987
-system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Inv_Ack::total 413
-system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.All_Acks::total 106987
-system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 8931
-system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.WriteRequest::total 106987
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 241407 99.93% 99.93% | 165 0.07% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 241572
-system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 8931
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3202838 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 3202838
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 106987
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 413
-system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 106987
-system.ruby.L1Cache_Controller.Load | 93672271 54.53% 54.53% | 78099262 45.47% 100.00%
-system.ruby.L1Cache_Controller.Load::total 171771533
-system.ruby.L1Cache_Controller.Ifetch | 472009619 55.15% 55.15% | 383825779 44.85% 100.00%
-system.ruby.L1Cache_Controller.Ifetch::total 855835398
-system.ruby.L1Cache_Controller.Store | 89261373 54.72% 54.72% | 73866508 45.28% 100.00%
-system.ruby.L1Cache_Controller.Store::total 163127881
-system.ruby.L1Cache_Controller.L1_Replacement | 11613388 54.55% 54.55% | 9676755 45.45% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 21290143
-system.ruby.L1Cache_Controller.Own_GETX | 1536 50.23% 50.23% | 1522 49.77% 100.00%
-system.ruby.L1Cache_Controller.Own_GETX::total 3058
-system.ruby.L1Cache_Controller.Fwd_GETX | 57472 52.69% 52.69% | 51613 47.31% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 109085
-system.ruby.L1Cache_Controller.Fwd_GETS | 145222 48.78% 48.78% | 152500 51.22% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 297722
-system.ruby.L1Cache_Controller.Fwd_DMA | 569 57.19% 57.19% | 426 42.81% 100.00%
-system.ruby.L1Cache_Controller.Fwd_DMA::total 995
-system.ruby.L1Cache_Controller.Inv | 2626 48.33% 48.33% | 2808 51.67% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 5434
-system.ruby.L1Cache_Controller.Ack | 54505 47.53% 47.53% | 60164 52.47% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 114669
-system.ruby.L1Cache_Controller.Data | 6875924 52.70% 52.70% | 6170294 47.30% 100.00%
-system.ruby.L1Cache_Controller.Data::total 13046218
-system.ruby.L1Cache_Controller.Exclusive_Data | 4898127 57.38% 57.38% | 3637556 42.62% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 8535683
-system.ruby.L1Cache_Controller.Writeback_Ack | 6574964 52.61% 52.61% | 5923695 47.39% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 12498659
-system.ruby.L1Cache_Controller.Writeback_Ack_Data | 4941903 57.31% 57.31% | 3681780 42.69% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 8623683
-system.ruby.L1Cache_Controller.Writeback_Nack | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total 3
-system.ruby.L1Cache_Controller.All_acks | 2395111 59.49% 59.49% | 1630974 40.51% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 4026085
-system.ruby.L1Cache_Controller.Use_Timeout | 4899662 57.38% 57.38% | 3639078 42.62% 100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total 8538740
-system.ruby.L1Cache_Controller.I.Load | 4014305 54.73% 54.73% | 3321076 45.27% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 7335381
-system.ruby.L1Cache_Controller.I.Ifetch | 5366172 52.49% 52.49% | 4857322 47.51% 100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total 10223494
-system.ruby.L1Cache_Controller.I.Store | 2275464 59.45% 59.45% | 1551875 40.55% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 3827339
-system.ruby.L1Cache_Controller.I.L1_Replacement | 96510 57.52% 57.52% | 71277 42.48% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 167787
-system.ruby.L1Cache_Controller.S.Load | 12058362 53.08% 53.08% | 10658255 46.92% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 22716617
-system.ruby.L1Cache_Controller.S.Ifetch | 466637721 55.18% 55.18% | 378967131 44.82% 100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total 845604852
-system.ruby.L1Cache_Controller.S.Store | 118110 60.36% 60.36% | 77572 39.64% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 195682
-system.ruby.L1Cache_Controller.S.L1_Replacement | 6754604 52.59% 52.59% | 6089329 47.41% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 12843933
-system.ruby.L1Cache_Controller.S.Fwd_GETS | 2238 42.24% 42.24% | 3060 57.76% 100.00%
-system.ruby.L1Cache_Controller.S.Fwd_GETS::total 5298
-system.ruby.L1Cache_Controller.S.Inv | 2622 48.31% 48.31% | 2806 51.69% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 5428
-system.ruby.L1Cache_Controller.O.Load | 266729 48.34% 48.34% | 285028 51.66% 100.00%
-system.ruby.L1Cache_Controller.O.Load::total 551757
-system.ruby.L1Cache_Controller.O.Store | 1537 50.16% 50.16% | 1527 49.84% 100.00%
-system.ruby.L1Cache_Controller.O.Store::total 3064
-system.ruby.L1Cache_Controller.O.L1_Replacement | 27965 46.61% 46.61% | 32033 53.39% 100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total 59998
-system.ruby.L1Cache_Controller.O.Fwd_GETX | 14380 44.27% 44.27% | 18102 55.73% 100.00%
-system.ruby.L1Cache_Controller.O.Fwd_GETX::total 32482
-system.ruby.L1Cache_Controller.O.Fwd_GETS | 18863 41.80% 41.80% | 26263 58.20% 100.00%
-system.ruby.L1Cache_Controller.O.Fwd_GETS::total 45126
-system.ruby.L1Cache_Controller.M.Load | 11815755 57.14% 57.14% | 8864201 42.86% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 20679956
-system.ruby.L1Cache_Controller.M.Store | 661017 54.08% 54.08% | 561249 45.92% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 1222266
-system.ruby.L1Cache_Controller.M.L1_Replacement | 1318265 57.42% 57.42% | 977394 42.58% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 2295659
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 3703 48.47% 48.47% | 3937 51.53% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 7640
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 43887 45.93% 45.93% | 51664 54.07% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 95551
-system.ruby.L1Cache_Controller.M_W.Load | 1121024 57.47% 57.47% | 829567 42.53% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 1950591
-system.ruby.L1Cache_Controller.M_W.Ifetch | 13 65.00% 65.00% | 7 35.00% 100.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch::total 20
-system.ruby.L1Cache_Controller.M_W.Store | 477638 53.58% 53.58% | 413796 46.42% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 891434
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 5 83.33% 83.33% | 1 16.67% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 6
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 630 57.22% 57.22% | 471 42.78% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 1101
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 427 47.82% 47.82% | 466 52.18% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 893
-system.ruby.L1Cache_Controller.M_W.Use_Timeout | 2026913 55.97% 55.97% | 1594308 44.03% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 3621221
-system.ruby.L1Cache_Controller.MM.Load | 64125299 54.32% 54.32% | 53925291 45.68% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 118050590
-system.ruby.L1Cache_Controller.MM.Store | 79145149 54.60% 54.60% | 65821135 45.40% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 144966284
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 3416036 57.68% 57.68% | 2506720 42.32% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 5922756
-system.ruby.L1Cache_Controller.MM.Fwd_GETX | 37950 57.34% 57.34% | 28233 42.66% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 66183
-system.ruby.L1Cache_Controller.MM.Fwd_GETS | 79392 52.90% 52.90% | 70698 47.10% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 150090
-system.ruby.L1Cache_Controller.MM.Fwd_DMA | 569 57.19% 57.19% | 426 42.81% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_DMA::total 995
-system.ruby.L1Cache_Controller.MM_W.Load | 266298 55.41% 55.41% | 214299 44.59% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 480597
-system.ruby.L1Cache_Controller.MM_W.Store | 6582446 54.75% 54.75% | 5439354 45.25% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 12021800
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 3 75.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 798 48.07% 48.07% | 862 51.93% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 1660
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 405 54.22% 54.22% | 342 45.78% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 747
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 2872749 58.42% 58.42% | 2044770 41.58% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 4917519
-system.ruby.L1Cache_Controller.IM.Ack | 32733 43.61% 43.61% | 42322 56.39% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 75055
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 2275469 59.45% 59.45% | 1551882 40.55% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 3827351
-system.ruby.L1Cache_Controller.SM.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Fwd_GETS::total 1
-system.ruby.L1Cache_Controller.SM.Inv | 4 66.67% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.SM.Inv::total 6
-system.ruby.L1Cache_Controller.SM.Ack | 17428 55.99% 55.99% | 13698 44.01% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 31126
-system.ruby.L1Cache_Controller.SM.Exclusive_Data | 118106 60.36% 60.36% | 77570 39.64% 100.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 195676
-system.ruby.L1Cache_Controller.OM.Own_GETX | 1536 50.23% 50.23% | 1522 49.77% 100.00%
-system.ruby.L1Cache_Controller.OM.Own_GETX::total 3058
-system.ruby.L1Cache_Controller.OM.Fwd_GETX | 1 16.67% 16.67% | 5 83.33% 100.00%
-system.ruby.L1Cache_Controller.OM.Fwd_GETX::total 6
-system.ruby.L1Cache_Controller.OM.Ack | 4344 51.18% 51.18% | 4144 48.82% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 8488
-system.ruby.L1Cache_Controller.OM.All_acks | 2395111 59.49% 59.49% | 1630974 40.51% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total 4026085
-system.ruby.L1Cache_Controller.IS.Data | 6875924 52.70% 52.70% | 6170294 47.30% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 13046218
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 2504552 55.50% 55.50% | 2008104 44.50% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 4512656
-system.ruby.L1Cache_Controller.SI.Load | 4145 77.19% 77.19% | 1225 22.81% 100.00%
-system.ruby.L1Cache_Controller.SI.Load::total 5370
-system.ruby.L1Cache_Controller.SI.Ifetch | 5709 81.23% 81.23% | 1319 18.77% 100.00%
-system.ruby.L1Cache_Controller.SI.Ifetch::total 7028
-system.ruby.L1Cache_Controller.SI.Store | 10 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SI.Store::total 10
-system.ruby.L1Cache_Controller.SI.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 1
-system.ruby.L1Cache_Controller.SI.Writeback_Ack | 6574964 52.61% 52.61% | 5923695 47.39% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 12498659
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 179639 52.03% 52.03% | 165634 47.97% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 345273
-system.ruby.L1Cache_Controller.OI.Fwd_GETX | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 3
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 27973 46.61% 46.61% | 32037 53.39% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 60010
-system.ruby.L1Cache_Controller.MI.Load | 354 52.52% 52.52% | 320 47.48% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 674
-system.ruby.L1Cache_Controller.MI.Ifetch | 4 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Ifetch::total 4
-system.ruby.L1Cache_Controller.MI.Store | 2 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Store::total 2
-system.ruby.L1Cache_Controller.MI.Fwd_GETX | 8 80.00% 80.00% | 2 20.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 10
-system.ruby.L1Cache_Controller.MI.Fwd_GETS | 10 66.67% 66.67% | 5 33.33% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 15
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 4734283 57.61% 57.61% | 3484107 42.39% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 8218390
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 8 80.00% 80.00% | 2 20.00% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 10
-system.ruby.L1Cache_Controller.II.Writeback_Nack | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3
-system.ruby.L2Cache_Controller.L1_GETS 17569650 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 4026941 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTO 60018 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 8218470 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 10753831 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS 2091031 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_GETX 26886 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_DMA 2236 0.00% 0.00%
-system.ruby.L2Cache_Controller.Inv 413 0.00% 0.00%
-system.ruby.L2Cache_Controller.IntAck 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 1376990 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 1850112 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive 143 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 345273 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 8278399 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 1315534 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 25544886 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 8538741 0.00% 0.00%
-system.ruby.L2Cache_Controller.DmaAck 995 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 1573415 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 473076 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 1188736 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Inv 223 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 50 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS 5300 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 129088 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 340565 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS 4708 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.Inv 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS 245656 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX 73690 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTO 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 8218400 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_GETX 143 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_DMA 995 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETS 45126 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETX 1850 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO 23044 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETX 33699 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 36951 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 70024 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 10339310 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 29587 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Inv 186 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 256661 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETS 38787 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETX 6233 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 30689 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS 37098 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L2_Replacement 39 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETS 2049003 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 29575 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 10312172 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS 2048676 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 1220 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 4362566 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 2533627 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_GETX 26743 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_DMA 1241 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 1315495 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 143 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 23044 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.Unblock 70024 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 36966 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L1_PUTS 548 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.Unblock 2048676 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 4708 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 340565 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 512 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 10312172 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.Unblock 30689 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.Unblock 37098 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS 31 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETX 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 8218389 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.Unblock 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.Unblock 5300 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Unblock 45126 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6233 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 161 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 768 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 55 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Unblock 95566 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 225630 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_GETS 43 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_GETX 31 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTO 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 33699 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETS 9653 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 473126 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 473125 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 1218323 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_GETX 24 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 158663 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETX 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 1376986 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 1376986 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.IntAck 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.All_Acks 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2533627 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 364 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 10339310 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 4362566 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.Unblock 38787 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 372 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.Unblock 2049003 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 1315495 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 39 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXD.DmaAck 995 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:42:59
-gem5 executing on e108600-lin, pid 17314
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47405012960500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.401371 # Number of seconds simulated
-sim_ticks 47401370587500 # Number of ticks simulated
-final_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1122973 # Simulator instruction rate (inst/s)
-host_op_rate 1337206 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 65940331964 # Simulator tick rate (ticks/s)
-host_mem_usage 757896 # Number of bytes of host memory used
-host_seconds 718.85 # Real time elapsed on the host
-sim_insts 807251718 # Number of instructions simulated
-sim_ops 961253990 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory
-system.physmem.bytes_read::total 51897028 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70880488 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 815412 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 815412 # Number of read requests accepted
-system.physmem.writeReqs 1109760 # Number of write requests accepted
-system.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue
-system.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 50443 # Per bank write bursts
-system.physmem.perBankRdBursts::1 58279 # Per bank write bursts
-system.physmem.perBankRdBursts::2 46176 # Per bank write bursts
-system.physmem.perBankRdBursts::3 52637 # Per bank write bursts
-system.physmem.perBankRdBursts::4 47826 # Per bank write bursts
-system.physmem.perBankRdBursts::5 55648 # Per bank write bursts
-system.physmem.perBankRdBursts::6 52176 # Per bank write bursts
-system.physmem.perBankRdBursts::7 51274 # Per bank write bursts
-system.physmem.perBankRdBursts::8 44248 # Per bank write bursts
-system.physmem.perBankRdBursts::9 55412 # Per bank write bursts
-system.physmem.perBankRdBursts::10 43487 # Per bank write bursts
-system.physmem.perBankRdBursts::11 55151 # Per bank write bursts
-system.physmem.perBankRdBursts::12 50800 # Per bank write bursts
-system.physmem.perBankRdBursts::13 57431 # Per bank write bursts
-system.physmem.perBankRdBursts::14 46539 # Per bank write bursts
-system.physmem.perBankRdBursts::15 47507 # Per bank write bursts
-system.physmem.perBankWrBursts::0 68734 # Per bank write bursts
-system.physmem.perBankWrBursts::1 74075 # Per bank write bursts
-system.physmem.perBankWrBursts::2 65910 # Per bank write bursts
-system.physmem.perBankWrBursts::3 69531 # Per bank write bursts
-system.physmem.perBankWrBursts::4 66080 # Per bank write bursts
-system.physmem.perBankWrBursts::5 73115 # Per bank write bursts
-system.physmem.perBankWrBursts::6 69817 # Per bank write bursts
-system.physmem.perBankWrBursts::7 69743 # Per bank write bursts
-system.physmem.perBankWrBursts::8 63555 # Per bank write bursts
-system.physmem.perBankWrBursts::9 71485 # Per bank write bursts
-system.physmem.perBankWrBursts::10 64662 # Per bank write bursts
-system.physmem.perBankWrBursts::11 72406 # Per bank write bursts
-system.physmem.perBankWrBursts::12 68380 # Per bank write bursts
-system.physmem.perBankWrBursts::13 74722 # Per bank write bursts
-system.physmem.perBankWrBursts::14 65945 # Per bank write bursts
-system.physmem.perBankWrBursts::15 69295 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 463 # Number of times write queue was full causing retry
-system.physmem.totGap 47401367297000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 4795 # Read request sizes (log2)
-system.physmem.readPktSize::3 25 # Read request sizes (log2)
-system.physmem.readPktSize::4 5 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 810587 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 2 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1107186 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads
-system.physmem.totQLat 43191913053 # Total ticks spent queuing
-system.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 599171 # Number of row buffer hits during reads
-system.physmem.writeRowHits 461094 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes
-system.physmem.avgGap 24621886.93 # Average gap between requests
-system.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ)
-system.physmem_0.averagePower 242.857940 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states
-system.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states
-system.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ)
-system.physmem_1.averagePower 242.880926 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states
-system.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 92556 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 77415423 # DTB read hits
-system.cpu0.dtb.read_misses 69730 # DTB read misses
-system.cpu0.dtb.write_hits 70114940 # DTB write hits
-system.cpu0.dtb.write_misses 22826 # DTB write misses
-system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 77485153 # DTB read accesses
-system.cpu0.dtb.write_accesses 70137766 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 147530363 # DTB hits
-system.cpu0.dtb.misses 92556 # DTB misses
-system.cpu0.dtb.accesses 147622919 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 51144 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 385005651 # ITB inst hits
-system.cpu0.itb.inst_misses 51144 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 385056795 # ITB inst accesses
-system.cpu0.itb.hits 385005651 # DTB hits
-system.cpu0.itb.misses 51144 # DTB misses
-system.cpu0.itb.accesses 385056795 # DTB accesses
-system.cpu0.numPwrStateTransitions 8306 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 94802741175 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed
-system.cpu0.committedInsts 384730653 # Number of instructions committed
-system.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses
-system.cpu0.num_func_calls 24795410 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 424236423 # number of integer instructions
-system.cpu0.num_fp_insts 341428 # number of float instructions
-system.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written
-system.cpu0.num_mem_refs 147523428 # number of memory refs
-system.cpu0.num_load_insts 77412307 # Number of load instructions
-system.cpu0.num_store_insts 70111121 # Number of store instructions
-system.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles
-system.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.989623 # Percentage of idle cycles
-system.cpu0.Branches 84896632 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction
-system.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction
-system.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction
-system.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction
-system.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction
-system.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 456691600 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 5013046 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits
-system.cpu0.dcache.overall_hits::total 138639484 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5260909 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks
-system.cpu0.dcache.writebacks::total 5013046 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 4327935 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits
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-system.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits
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-system.cpu0.icache.overall_hits::total 380677204 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total 4328447 # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles
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-system.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks
-system.cpu0.icache.writebacks::total 4327935 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses
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-system.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable
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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 11.284107 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 280.489666 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 540 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4190 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7117 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2983 # Occupied blocks per task id
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-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 272723500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15771055500 # number of overall miss cycles
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-system.cpu0.l2cache.UpgradeReq_accesses::total 218667 # number of UpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 40177.669861 # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches 34479 # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks 1361012 # number of writebacks
-system.cpu0.l2cache.writebacks::total 1361012 # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5370 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total 5370 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 489 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 489 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5859 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total 5859 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5859 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total 5859 # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 15216 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8071 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total 23287 # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total 675054 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 218667 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total 218667 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 191059 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 191059 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 223423 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total 223423 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 411411 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 411411 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 830283 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 830283 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 558166 # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total 558166 # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 15216 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8071 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 411411 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1053706 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 1488404 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 15216 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8071 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 411411 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1053706 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 2163458 # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20616 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37416 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 224297500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 569280000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32033056811 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4084370000 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4084370000 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2911469499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2911469499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2248998 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2248998 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10644364000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10644364000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13302589500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13302589500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 25893671500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 25893671500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 17612762500 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 17612762500 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 224297500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13302589500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36538035500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 50409905000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 224297500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13302589500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4847803 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 108097 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 86913541 # DTB read hits
-system.cpu1.dtb.read_misses 78813 # DTB read misses
-system.cpu1.dtb.write_hits 79382446 # DTB write hits
-system.cpu1.dtb.write_misses 29284 # DTB write misses
-system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 86992354 # DTB read accesses
-system.cpu1.dtb.write_accesses 79411730 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 166295987 # DTB hits
-system.cpu1.dtb.misses 108097 # DTB misses
-system.cpu1.dtb.accesses 166404084 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 67294 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 422829218 # ITB inst hits
-system.cpu1.itb.inst_misses 67294 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 422896512 # ITB inst accesses
-system.cpu1.itb.hits 422829218 # DTB hits
-system.cpu1.itb.misses 67294 # DTB misses
-system.cpu1.itb.accesses 422896512 # DTB accesses
-system.cpu1.numPwrStateTransitions 29136 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 94802741175 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed
-system.cpu1.committedInsts 422521065 # Number of instructions committed
-system.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses
-system.cpu1.num_func_calls 27792823 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 470472983 # number of integer instructions
-system.cpu1.num_fp_insts 594254 # number of float instructions
-system.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written
-system.cpu1.num_mem_refs 166284311 # number of memory refs
-system.cpu1.num_load_insts 86908703 # Number of load instructions
-system.cpu1.num_store_insts 79375608 # Number of store instructions
-system.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles
-system.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988683 # Percentage of idle cycles
-system.cpu1.Branches 93458434 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction
-system.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction
-system.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction
-system.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction
-system.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 505150374 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 5478037 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits
-system.cpu1.dcache.overall_hits::total 156658996 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5659360 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks
-system.cpu1.dcache.writebacks::total 5478037 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency
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-system.cpu1.icache.tags.replacements 5778503 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
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-system.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits
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-system.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 417050198 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 5779020 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 5779020 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 5779020 # number of overall misses
-system.cpu1.icache.overall_misses::total 5779020 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 61138169500 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 61138169500 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 61138169500 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency
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-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.writebacks::total 5778503 # number of writebacks
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-system.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 58248659500 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency
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-system.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 1924030 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 387081443 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 387081443 # Number of data accesses
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-system.cpu1.l2cache.ReadReq_hits::total 418202 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 3475258 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 3475258 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 7780467 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 7780467 # number of WritebackClean hits
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-system.cpu1.l2cache.ReadCleanReq_hits::total 5308980 # number of ReadCleanReq hits
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-system.cpu1.l2cache.ReadSharedReq_hits::total 2962504 # number of ReadSharedReq hits
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-system.cpu1.l2cache.InvalidateReq_hits::total 264311 # number of InvalidateReq hits
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-system.cpu1.l2cache.demand_hits::cpu1.inst 5308980 # number of demand (read+write) hits
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-system.cpu1.l2cache.overall_hits::cpu1.inst 5308980 # number of overall hits
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-system.cpu1.l2cache.UpgradeReq_misses::total 208398 # number of UpgradeReq misses
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-system.cpu1.l2cache.InvalidateReq_misses::total 261134 # number of InvalidateReq misses
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-system.cpu1.l2cache.overall_misses::cpu1.data 1155445 # number of overall misses
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-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2107498 # number of SCUpgradeFailReq miss cycles
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-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17654070500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32780970500 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32780970500 # number of ReadSharedReq miss cycles
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-system.cpu1.l2cache.InvalidateReq_miss_latency::total 198500 # number of InvalidateReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 383665000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17654070500 # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4566671 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40263 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40263 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136535 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136535 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115618 # number of replacements
-system.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040955 # Number of tag accesses
-system.iocache.tags.data_accesses 1040955 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8931 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115662 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115622 # number of overall misses
-system.iocache.overall_misses::total 115662 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency
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-system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
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-system.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
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-system.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked
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-system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked
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-system.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106694 # number of writebacks
-system.iocache.writebacks::total 106694 # number of writebacks
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-system.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses
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-system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
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-system.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses
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-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1577555480 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1580900480 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8010840420 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8010840420 # number of WriteLineReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::realview.ide 9588395900 # number of demand (read+write) MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::total 9591959900 # number of overall MSHR miss cycles
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-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
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-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177373.002024 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 177012.706304 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75058.470317 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75058.470317 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency
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-system.l2c.tags.replacements 1289685 # number of replacements
-system.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use
-system.l2c.tags.total_refs 5723107 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 65194650 # Number of tag accesses
-system.l2c.tags.data_accesses 65194650 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 165997 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 157094 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 323091 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 44921 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 51888 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 96809 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 41742 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 58696 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 100438 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7485 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3707 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 366128 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 471159 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 250331 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11134 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 423879 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 535784 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283571 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 2358374 # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data 108961 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data 126093 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total 235054 # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 7485 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3707 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 366128 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 512901 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 250331 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 11134 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 423879 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 594480 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 283571 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2458812 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 7485 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 3707 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 366128 # number of overall hits
-system.l2c.overall_hits::cpu0.data 512901 # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher 250331 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 11134 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 423879 # number of overall hits
-system.l2c.overall_hits::cpu1.data 594480 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 283571 # number of overall hits
-system.l2c.overall_hits::total 2458812 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 21704 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 22525 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 44229 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 639 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 868 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1507 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 68872 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 49716 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 118588 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 981 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 934 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 45283 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 111817 # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1691 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1806 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 46161 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 105560 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 172390 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 687444 # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data 412236 # number of InvalidateReq misses
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-system.l2c.InvalidateReq_misses::total 502594 # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 981 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 934 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 45283 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 180689 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher 200821 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 1691 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 1806 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 46161 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 155276 # number of demand (read+write) misses
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-system.l2c.demand_misses::total 806032 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu0.inst 45283 # number of overall misses
-system.l2c.overall_misses::cpu0.data 180689 # number of overall misses
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-system.l2c.overall_misses::cpu1.dtb.walker 1691 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 1806 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 46161 # number of overall misses
-system.l2c.overall_misses::cpu1.data 155276 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 172390 # number of overall misses
-system.l2c.overall_misses::total 806032 # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::cpu1.data 137680500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 261038000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7905500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10002000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 17907500 # number of SCUpgradeReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5195669500 # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 176942500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 186194000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5476488000 # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 86331961414 # number of ReadSharedReq miss cycles
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-system.l2c.demand_miss_latency::cpu1.inst 5476488000 # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 99454015414 # number of demand (read+write) miss cycles
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-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21488000 # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1724009500 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total 9856919500 # number of InvalidateReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94817501 # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst 5000535031 # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::total 91316383578 # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.inst 5000535031 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 16469292724 # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total 91316383578 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343198000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2516105003 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7788000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3411021500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 6278112503 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343198000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2516105003 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7788000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3411021500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 6278112503 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 43096 # Transaction distribution
-system.membus.trans_dist::ReadResp 738496 # Transaction distribution
-system.membus.trans_dist::WriteReq 38143 # Transaction distribution
-system.membus.trans_dist::WriteResp 38143 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution
-system.membus.trans_dist::CleanEvict 202416 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 304555 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.membus.trans_dist::ReadExReq 135023 # Transaction distribution
-system.membus.trans_dist::ReadExResp 117908 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 620101 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 29545 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 615067 # Total snoops (count)
-system.membus.snoopTraffic 174144 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2133066 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.015313 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram
-system.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2133066 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2787811 # Total snoops (count)
-system.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000029] Console: colour dummy device 80x25\r
-[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000033] pid_max: default: 32768 minimum: 301\r
-[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000190] hw perfevents: no hardware support available\r
-[ 0.060052] CPU1: Booted secondary processor\r
-[ 1.080092] CPU2: failed to come online\r
-[ 2.100178] CPU3: failed to come online\r
-[ 2.100181] Brought up 2 CPUs\r
-[ 2.100182] SMP: Total of 2 processors activated.\r
-[ 2.100254] devtmpfs: initialized\r
-[ 2.100899] atomic64_test: passed\r
-[ 2.100953] regulator-dummy: no parameters\r
-[ 2.101395] NET: Registered protocol family 16\r
-[ 2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.102374] Serial: AMBA PL011 UART driver\r
-[ 2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.103226] console [ttyAMA0] enabled\r
-[ 2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.130484] 3V3: 3300 mV \r
-[ 2.130542] vgaarb: loaded\r
-[ 2.130598] SCSI subsystem initialized\r
-[ 2.130640] libata version 3.00 loaded.\r
-[ 2.130696] usbcore: registered new interface driver usbfs\r
-[ 2.130716] usbcore: registered new interface driver hub\r
-[ 2.130745] usbcore: registered new device driver usb\r
-[ 2.130775] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.130805] PTP clock support registered\r
-[ 2.130963] Switched to clocksource arch_sys_counter\r
-[ 2.132610] NET: Registered protocol family 2\r
-[ 2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.132748] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.132775] TCP: reno registered\r
-[ 2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132838] NET: Registered protocol family 1\r
-[ 2.132904] RPC: Registered named UNIX socket transport module.\r
-[ 2.132915] RPC: Registered udp transport module.\r
-[ 2.132923] RPC: Registered tcp transport module.\r
-[ 2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.132945] PCI: CLS 0 bytes, default 64\r
-[ 2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.135328] fuse init (API version 7.23)\r
-[ 2.135440] msgmni has been set to 469\r
-[ 2.135797] io scheduler noop registered\r
-[ 2.135862] io scheduler cfq registered (default)\r
-[ 2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.136447] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.136482] pci_bus 0000:00: scanning bus\r
-[ 2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.136577] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.136588] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.136600] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.136611] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.136622] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.136675] pci_bus 0000:00: fixups for bus\r
-[ 2.136684] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.136718] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.136727] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.136739] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.136748] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.136801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.136813] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.136825] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.136837] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.136849] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.137740] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.137778] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.138110] scsi0 : ata_piix\r
-[ 2.138200] scsi1 : ata_piix\r
-[ 2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.138423] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290994] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.291024] ata1.00: configured for UDMA/33\r
-[ 2.291083] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.291255] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.291434] sda: sda1\r
-[ 2.291570] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.411448] usbcore: registered new interface driver usb-storage\r
-[ 2.411534] mousedev: PS/2 mouse device common for all mice\r
-[ 2.411744] usbcore: registered new interface driver usbhid\r
-[ 2.411754] usbhid: USB HID core driver\r
-[ 2.411794] TCP: cubic registered\r
-[ 2.411802] NET: Registered protocol family 17\r
-\0[ 2.412301] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.412341] devtmpfs: mounted\r
-[ 2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.452586] udevd[609]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.534161] random: dd urandom read with 18 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.671190] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-done.\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.787462
-sim_ticks 51787462200000
-final_tick 51787462200000
-sim_freq 1000000000000
-host_inst_rate 182261
-host_op_rate 216980
-host_tick_rate 11279646930
-host_mem_usage 1341804
-host_seconds 4591.23
-sim_insts 836801197
-sim_ops 996203379
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 51787462200000
-system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 54732480
-system.mem_ctrls0.bytes_read::total 54732480
-system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 42463040
-system.mem_ctrls0.bytes_written::total 42463040
-system.mem_ctrls0.num_reads::ruby.dir_cntrl0 855195
-system.mem_ctrls0.num_reads::total 855195
-system.mem_ctrls0.num_writes::ruby.dir_cntrl0 663485
-system.mem_ctrls0.num_writes::total 663485
-system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1056867
-system.mem_ctrls0.bw_read::total 1056867
-system.mem_ctrls0.bw_write::ruby.dir_cntrl0 819948
-system.mem_ctrls0.bw_write::total 819948
-system.mem_ctrls0.bw_total::ruby.dir_cntrl0 1876816
-system.mem_ctrls0.bw_total::total 1876816
-system.mem_ctrls0.readReqs 855195
-system.mem_ctrls0.writeReqs 663485
-system.mem_ctrls0.readBursts 855195
-system.mem_ctrls0.writeBursts 663485
-system.mem_ctrls0.bytesReadDRAM 54638080
-system.mem_ctrls0.bytesReadWrQ 94400
-system.mem_ctrls0.bytesWritten 42460672
-system.mem_ctrls0.bytesReadSys 54732480
-system.mem_ctrls0.bytesWrittenSys 42463040
-system.mem_ctrls0.servicedByWrQ 1475
-system.mem_ctrls0.mergedWrBursts 7
-system.mem_ctrls0.neitherReadNorWriteReqs 0
-system.mem_ctrls0.perBankRdBursts::0 53979
-system.mem_ctrls0.perBankRdBursts::1 56453
-system.mem_ctrls0.perBankRdBursts::2 56859
-system.mem_ctrls0.perBankRdBursts::3 55806
-system.mem_ctrls0.perBankRdBursts::4 52130
-system.mem_ctrls0.perBankRdBursts::5 56684
-system.mem_ctrls0.perBankRdBursts::6 52943
-system.mem_ctrls0.perBankRdBursts::7 51954
-system.mem_ctrls0.perBankRdBursts::8 54653
-system.mem_ctrls0.perBankRdBursts::9 54363
-system.mem_ctrls0.perBankRdBursts::10 53142
-system.mem_ctrls0.perBankRdBursts::11 51431
-system.mem_ctrls0.perBankRdBursts::12 53363
-system.mem_ctrls0.perBankRdBursts::13 52122
-system.mem_ctrls0.perBankRdBursts::14 48274
-system.mem_ctrls0.perBankRdBursts::15 49564
-system.mem_ctrls0.perBankWrBursts::0 42330
-system.mem_ctrls0.perBankWrBursts::1 43715
-system.mem_ctrls0.perBankWrBursts::2 43620
-system.mem_ctrls0.perBankWrBursts::3 43275
-system.mem_ctrls0.perBankWrBursts::4 40870
-system.mem_ctrls0.perBankWrBursts::5 42357
-system.mem_ctrls0.perBankWrBursts::6 40606
-system.mem_ctrls0.perBankWrBursts::7 40498
-system.mem_ctrls0.perBankWrBursts::8 40878
-system.mem_ctrls0.perBankWrBursts::9 41982
-system.mem_ctrls0.perBankWrBursts::10 41541
-system.mem_ctrls0.perBankWrBursts::11 40396
-system.mem_ctrls0.perBankWrBursts::12 41596
-system.mem_ctrls0.perBankWrBursts::13 41135
-system.mem_ctrls0.perBankWrBursts::14 39231
-system.mem_ctrls0.perBankWrBursts::15 39418
-system.mem_ctrls0.numRdRetry 0
-system.mem_ctrls0.numWrRetry 0
-system.mem_ctrls0.totGap 51787460665000
-system.mem_ctrls0.readPktSize::0 0
-system.mem_ctrls0.readPktSize::1 0
-system.mem_ctrls0.readPktSize::2 0
-system.mem_ctrls0.readPktSize::3 0
-system.mem_ctrls0.readPktSize::4 0
-system.mem_ctrls0.readPktSize::5 0
-system.mem_ctrls0.readPktSize::6 855195
-system.mem_ctrls0.writePktSize::0 0
-system.mem_ctrls0.writePktSize::1 0
-system.mem_ctrls0.writePktSize::2 0
-system.mem_ctrls0.writePktSize::3 0
-system.mem_ctrls0.writePktSize::4 0
-system.mem_ctrls0.writePktSize::5 0
-system.mem_ctrls0.writePktSize::6 663485
-system.mem_ctrls0.rdQLenPdf::0 853574
-system.mem_ctrls0.rdQLenPdf::1 146
-system.mem_ctrls0.rdQLenPdf::2 0
-system.mem_ctrls0.rdQLenPdf::3 0
-system.mem_ctrls0.rdQLenPdf::4 0
-system.mem_ctrls0.rdQLenPdf::5 0
-system.mem_ctrls0.rdQLenPdf::6 0
-system.mem_ctrls0.rdQLenPdf::7 0
-system.mem_ctrls0.rdQLenPdf::8 0
-system.mem_ctrls0.rdQLenPdf::9 0
-system.mem_ctrls0.rdQLenPdf::10 0
-system.mem_ctrls0.rdQLenPdf::11 0
-system.mem_ctrls0.rdQLenPdf::12 0
-system.mem_ctrls0.rdQLenPdf::13 0
-system.mem_ctrls0.rdQLenPdf::14 0
-system.mem_ctrls0.rdQLenPdf::15 0
-system.mem_ctrls0.rdQLenPdf::16 0
-system.mem_ctrls0.rdQLenPdf::17 0
-system.mem_ctrls0.rdQLenPdf::18 0
-system.mem_ctrls0.rdQLenPdf::19 0
-system.mem_ctrls0.rdQLenPdf::20 0
-system.mem_ctrls0.rdQLenPdf::21 0
-system.mem_ctrls0.rdQLenPdf::22 0
-system.mem_ctrls0.rdQLenPdf::23 0
-system.mem_ctrls0.rdQLenPdf::24 0
-system.mem_ctrls0.rdQLenPdf::25 0
-system.mem_ctrls0.rdQLenPdf::26 0
-system.mem_ctrls0.rdQLenPdf::27 0
-system.mem_ctrls0.rdQLenPdf::28 0
-system.mem_ctrls0.rdQLenPdf::29 0
-system.mem_ctrls0.rdQLenPdf::30 0
-system.mem_ctrls0.rdQLenPdf::31 0
-system.mem_ctrls0.wrQLenPdf::0 1
-system.mem_ctrls0.wrQLenPdf::1 1
-system.mem_ctrls0.wrQLenPdf::2 1
-system.mem_ctrls0.wrQLenPdf::3 1
-system.mem_ctrls0.wrQLenPdf::4 1
-system.mem_ctrls0.wrQLenPdf::5 1
-system.mem_ctrls0.wrQLenPdf::6 1
-system.mem_ctrls0.wrQLenPdf::7 1
-system.mem_ctrls0.wrQLenPdf::8 1
-system.mem_ctrls0.wrQLenPdf::9 1
-system.mem_ctrls0.wrQLenPdf::10 1
-system.mem_ctrls0.wrQLenPdf::11 1
-system.mem_ctrls0.wrQLenPdf::12 1
-system.mem_ctrls0.wrQLenPdf::13 1
-system.mem_ctrls0.wrQLenPdf::14 1
-system.mem_ctrls0.wrQLenPdf::15 29248
-system.mem_ctrls0.wrQLenPdf::16 31010
-system.mem_ctrls0.wrQLenPdf::17 35107
-system.mem_ctrls0.wrQLenPdf::18 37417
-system.mem_ctrls0.wrQLenPdf::19 37947
-system.mem_ctrls0.wrQLenPdf::20 37603
-system.mem_ctrls0.wrQLenPdf::21 38022
-system.mem_ctrls0.wrQLenPdf::22 37653
-system.mem_ctrls0.wrQLenPdf::23 37911
-system.mem_ctrls0.wrQLenPdf::24 37335
-system.mem_ctrls0.wrQLenPdf::25 37355
-system.mem_ctrls0.wrQLenPdf::26 37373
-system.mem_ctrls0.wrQLenPdf::27 37266
-system.mem_ctrls0.wrQLenPdf::28 37665
-system.mem_ctrls0.wrQLenPdf::29 37325
-system.mem_ctrls0.wrQLenPdf::30 37104
-system.mem_ctrls0.wrQLenPdf::31 36888
-system.mem_ctrls0.wrQLenPdf::32 36808
-system.mem_ctrls0.wrQLenPdf::33 1428
-system.mem_ctrls0.wrQLenPdf::34 723
-system.mem_ctrls0.wrQLenPdf::35 488
-system.mem_ctrls0.wrQLenPdf::36 418
-system.mem_ctrls0.wrQLenPdf::37 358
-system.mem_ctrls0.wrQLenPdf::38 360
-system.mem_ctrls0.wrQLenPdf::39 343
-system.mem_ctrls0.wrQLenPdf::40 325
-system.mem_ctrls0.wrQLenPdf::41 298
-system.mem_ctrls0.wrQLenPdf::42 281
-system.mem_ctrls0.wrQLenPdf::43 304
-system.mem_ctrls0.wrQLenPdf::44 216
-system.mem_ctrls0.wrQLenPdf::45 197
-system.mem_ctrls0.wrQLenPdf::46 179
-system.mem_ctrls0.wrQLenPdf::47 171
-system.mem_ctrls0.wrQLenPdf::48 150
-system.mem_ctrls0.wrQLenPdf::49 102
-system.mem_ctrls0.wrQLenPdf::50 80
-system.mem_ctrls0.wrQLenPdf::51 5
-system.mem_ctrls0.wrQLenPdf::52 0
-system.mem_ctrls0.wrQLenPdf::53 0
-system.mem_ctrls0.wrQLenPdf::54 0
-system.mem_ctrls0.wrQLenPdf::55 0
-system.mem_ctrls0.wrQLenPdf::56 0
-system.mem_ctrls0.wrQLenPdf::57 0
-system.mem_ctrls0.wrQLenPdf::58 0
-system.mem_ctrls0.wrQLenPdf::59 0
-system.mem_ctrls0.wrQLenPdf::60 0
-system.mem_ctrls0.wrQLenPdf::61 0
-system.mem_ctrls0.wrQLenPdf::62 0
-system.mem_ctrls0.wrQLenPdf::63 0
-system.mem_ctrls0.bytesPerActivate::samples 464954
-system.mem_ctrls0.bytesPerActivate::mean 208.834766
-system.mem_ctrls0.bytesPerActivate::gmean 125.209988
-system.mem_ctrls0.bytesPerActivate::stdev 270.988110
-system.mem_ctrls0.bytesPerActivate::0-127 249011 53.56% 53.56%
-system.mem_ctrls0.bytesPerActivate::128-255 113120 24.33% 77.89%
-system.mem_ctrls0.bytesPerActivate::256-383 31905 6.86% 84.75%
-system.mem_ctrls0.bytesPerActivate::384-511 15844 3.41% 88.15%
-system.mem_ctrls0.bytesPerActivate::512-639 8162 1.76% 89.91%
-system.mem_ctrls0.bytesPerActivate::640-767 5473 1.18% 91.09%
-system.mem_ctrls0.bytesPerActivate::768-895 4605 0.99% 92.08%
-system.mem_ctrls0.bytesPerActivate::896-1023 4316 0.93% 93.01%
-system.mem_ctrls0.bytesPerActivate::1024-1151 32518 6.99% 100.00%
-system.mem_ctrls0.bytesPerActivate::total 464954
-system.mem_ctrls0.rdPerTurnAround::samples 36564
-system.mem_ctrls0.rdPerTurnAround::mean 23.347911
-system.mem_ctrls0.rdPerTurnAround::stdev 151.279974
-system.mem_ctrls0.rdPerTurnAround::0-1023 36561 99.99% 99.99%
-system.mem_ctrls0.rdPerTurnAround::1024-2047 2 0.01% 100.00%
-system.mem_ctrls0.rdPerTurnAround::27648-28671 1 0.00% 100.00%
-system.mem_ctrls0.rdPerTurnAround::total 36564
-system.mem_ctrls0.wrPerTurnAround::samples 36564
-system.mem_ctrls0.wrPerTurnAround::mean 18.144842
-system.mem_ctrls0.wrPerTurnAround::gmean 18.046618
-system.mem_ctrls0.wrPerTurnAround::stdev 2.223089
-system.mem_ctrls0.wrPerTurnAround::16 6078 16.62% 16.62%
-system.mem_ctrls0.wrPerTurnAround::17 812 2.22% 18.84%
-system.mem_ctrls0.wrPerTurnAround::18 23208 63.47% 82.32%
-system.mem_ctrls0.wrPerTurnAround::19 3494 9.56% 91.87%
-system.mem_ctrls0.wrPerTurnAround::20 1174 3.21% 95.08%
-system.mem_ctrls0.wrPerTurnAround::21 422 1.15% 96.24%
-system.mem_ctrls0.wrPerTurnAround::22 634 1.73% 97.97%
-system.mem_ctrls0.wrPerTurnAround::23 151 0.41% 98.38%
-system.mem_ctrls0.wrPerTurnAround::24 61 0.17% 98.55%
-system.mem_ctrls0.wrPerTurnAround::25 120 0.33% 98.88%
-system.mem_ctrls0.wrPerTurnAround::26 24 0.07% 98.94%
-system.mem_ctrls0.wrPerTurnAround::27 27 0.07% 99.02%
-system.mem_ctrls0.wrPerTurnAround::28 6 0.02% 99.03%
-system.mem_ctrls0.wrPerTurnAround::29 20 0.05% 99.09%
-system.mem_ctrls0.wrPerTurnAround::30 15 0.04% 99.13%
-system.mem_ctrls0.wrPerTurnAround::31 38 0.10% 99.23%
-system.mem_ctrls0.wrPerTurnAround::32 65 0.18% 99.41%
-system.mem_ctrls0.wrPerTurnAround::33 43 0.12% 99.53%
-system.mem_ctrls0.wrPerTurnAround::34 32 0.09% 99.62%
-system.mem_ctrls0.wrPerTurnAround::35 18 0.05% 99.67%
-system.mem_ctrls0.wrPerTurnAround::36 18 0.05% 99.72%
-system.mem_ctrls0.wrPerTurnAround::37 11 0.03% 99.75%
-system.mem_ctrls0.wrPerTurnAround::38 11 0.03% 99.78%
-system.mem_ctrls0.wrPerTurnAround::39 8 0.02% 99.80%
-system.mem_ctrls0.wrPerTurnAround::40 6 0.02% 99.81%
-system.mem_ctrls0.wrPerTurnAround::41 10 0.03% 99.84%
-system.mem_ctrls0.wrPerTurnAround::42 4 0.01% 99.85%
-system.mem_ctrls0.wrPerTurnAround::43 7 0.02% 99.87%
-system.mem_ctrls0.wrPerTurnAround::44 9 0.02% 99.90%
-system.mem_ctrls0.wrPerTurnAround::45 10 0.03% 99.92%
-system.mem_ctrls0.wrPerTurnAround::46 8 0.02% 99.95%
-system.mem_ctrls0.wrPerTurnAround::47 6 0.02% 99.96%
-system.mem_ctrls0.wrPerTurnAround::48 5 0.01% 99.98%
-system.mem_ctrls0.wrPerTurnAround::49 3 0.01% 99.98%
-system.mem_ctrls0.wrPerTurnAround::50 3 0.01% 99.99%
-system.mem_ctrls0.wrPerTurnAround::51 2 0.01% 100.00%
-system.mem_ctrls0.wrPerTurnAround::54 1 0.00% 100.00%
-system.mem_ctrls0.wrPerTurnAround::total 36564
-system.mem_ctrls0.totQLat 27227215500
-system.mem_ctrls0.totMemAccLat 43234465500
-system.mem_ctrls0.totBusLat 4268600000
-system.mem_ctrls0.avgQLat 31892.44
-system.mem_ctrls0.avgBusLat 5000.00
-system.mem_ctrls0.avgMemAccLat 50642.44
-system.mem_ctrls0.avgRdBW 1.06
-system.mem_ctrls0.avgWrBW 0.82
-system.mem_ctrls0.avgRdBWSys 1.06
-system.mem_ctrls0.avgWrBWSys 0.82
-system.mem_ctrls0.peakBW 12800.00
-system.mem_ctrls0.busUtil 0.01
-system.mem_ctrls0.busUtilRead 0.01
-system.mem_ctrls0.busUtilWrite 0.01
-system.mem_ctrls0.avgRdQLen 1.00
-system.mem_ctrls0.avgWrQLen 22.09
-system.mem_ctrls0.readRowHits 660828
-system.mem_ctrls0.writeRowHits 391385
-system.mem_ctrls0.readRowHitRate 77.41
-system.mem_ctrls0.writeRowHitRate 58.99
-system.mem_ctrls0.avgGap 34100311.23
-system.mem_ctrls0.pageHitRate 69.35
-system.mem_ctrls0_0.actEnergy 1732406760
-system.mem_ctrls0_0.preEnergy 920796030
-system.mem_ctrls0_0.readEnergy 3118809120
-system.mem_ctrls0_0.writeEnergy 1760554620
-system.mem_ctrls0_0.refreshEnergy 58798920960.000015
-system.mem_ctrls0_0.actBackEnergy 42795128040
-system.mem_ctrls0_0.preBackEnergy 3311088480
-system.mem_ctrls0_0.actPowerDownEnergy 123090170190
-system.mem_ctrls0_0.prePowerDownEnergy 85671951360
-system.mem_ctrls0_0.selfRefreshEnergy 12297450894510
-system.mem_ctrls0_0.totalEnergy 12618676172670
-system.mem_ctrls0_0.averagePower 243.662764
-system.mem_ctrls0_0.totalIdleTime 51684391186500
-system.mem_ctrls0_0.memoryStateTime::IDLE 6285943750
-system.mem_ctrls0_0.memoryStateTime::REF 24998958000
-system.mem_ctrls0_0.memoryStateTime::SREF 51191895262000
-system.mem_ctrls0_0.memoryStateTime::PRE_PDN 223103873751
-system.mem_ctrls0_0.memoryStateTime::ACT 71243678250
-system.mem_ctrls0_0.memoryStateTime::ACT_PDN 269934484249
-system.mem_ctrls0_1.actEnergy 1587371940
-system.mem_ctrls0_1.preEnergy 843704400
-system.mem_ctrls0_1.readEnergy 2976751680
-system.mem_ctrls0_1.writeEnergy 1702643940
-system.mem_ctrls0_1.refreshEnergy 57137549040.000015
-system.mem_ctrls0_1.actBackEnergy 41855001390
-system.mem_ctrls0_1.preBackEnergy 3183383520
-system.mem_ctrls0_1.actPowerDownEnergy 117205003410
-system.mem_ctrls0_1.prePowerDownEnergy 84164090400
-system.mem_ctrls0_1.selfRefreshEnergy 12301927302060
-system.mem_ctrls0_1.totalEnergy 12612608898270
-system.mem_ctrls0_1.averagePower 243.545606
-system.mem_ctrls0_1.totalIdleTime 51687326382500
-system.mem_ctrls0_1.memoryStateTime::IDLE 6016918250
-system.mem_ctrls0_1.memoryStateTime::REF 24294402000
-system.mem_ctrls0_1.memoryStateTime::SREF 51211120791500
-system.mem_ctrls0_1.memoryStateTime::PRE_PDN 219177607751
-system.mem_ctrls0_1.memoryStateTime::ACT 69824468500
-system.mem_ctrls0_1.memoryStateTime::ACT_PDN 257028011999
-system.mem_ctrls1.pwrStateResidencyTicks::UNDEFINED 51787462200000
-system.mem_ctrls1.bytes_read::ruby.dir_cntrl1 53720576
-system.mem_ctrls1.bytes_read::total 53720576
-system.mem_ctrls1.bytes_written::ruby.dir_cntrl1 42182592
-system.mem_ctrls1.bytes_written::total 42182592
-system.mem_ctrls1.num_reads::ruby.dir_cntrl1 839384
-system.mem_ctrls1.num_reads::total 839384
-system.mem_ctrls1.num_writes::ruby.dir_cntrl1 659103
-system.mem_ctrls1.num_writes::total 659103
-system.mem_ctrls1.bw_read::ruby.dir_cntrl1 1037328
-system.mem_ctrls1.bw_read::total 1037328
-system.mem_ctrls1.bw_write::ruby.dir_cntrl1 814533
-system.mem_ctrls1.bw_write::total 814533
-system.mem_ctrls1.bw_total::ruby.dir_cntrl1 1851861
-system.mem_ctrls1.bw_total::total 1851861
-system.mem_ctrls1.readReqs 839384
-system.mem_ctrls1.writeReqs 659103
-system.mem_ctrls1.readBursts 839384
-system.mem_ctrls1.writeBursts 659103
-system.mem_ctrls1.bytesReadDRAM 53627520
-system.mem_ctrls1.bytesReadWrQ 93056
-system.mem_ctrls1.bytesWritten 42181184
-system.mem_ctrls1.bytesReadSys 53720576
-system.mem_ctrls1.bytesWrittenSys 42182592
-system.mem_ctrls1.servicedByWrQ 1454
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-system.ruby.Directory_Controller.Exclusive_Unblock::total 1387139
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-system.ruby.Directory_Controller.Dirty_Writeback::total 1215921
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-system.ruby.Directory_Controller.DMA_WRITE::total 106667
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-system.ruby.Directory_Controller.DMA_ACK::total 2593
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-system.ruby.Directory_Controller.Data::total 30836
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-system.ruby.Directory_Controller.I.GETX::total 1104855
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-system.ruby.Directory_Controller.I.GETS::total 264642
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-system.ruby.Directory_Controller.I.Memory_Ack::total 1216147
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-system.ruby.Directory_Controller.I.DMA_READ::total 5932
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-system.ruby.Directory_Controller.S.GETX::total 175617
-system.ruby.Directory_Controller.S.GETS | 73477 51.19% 51.19% | 70056 48.81% 100.00%
-system.ruby.Directory_Controller.S.GETS::total 143533
-system.ruby.Directory_Controller.S.DMA_READ | 201 49.26% 49.26% | 207 50.74% 100.00%
-system.ruby.Directory_Controller.S.DMA_READ::total 408
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-system.ruby.Directory_Controller.S.DMA_WRITE::total 499
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-system.ruby.Directory_Controller.M.PUTX::total 1215921
-system.ruby.Directory_Controller.M.DMA_READ | 1742 67.18% 67.18% | 851 32.82% 100.00%
-system.ruby.Directory_Controller.M.DMA_READ::total 2593
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-system.ruby.Directory_Controller.M.DMA_WRITE::total 30836
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-system.ruby.Directory_Controller.IS.Unblock::total 264641
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-system.ruby.Directory_Controller.IS.Memory_Data::total 264642
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-system.ruby.Directory_Controller.SS.Last_Unblock::total 143533
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-system.ruby.Directory_Controller.SS.Memory_Data::total 143533
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-system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 1280472
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-system.ruby.Directory_Controller.MM.Memory_Data::total 1280472
-system.ruby.Directory_Controller.MM.Memory_Ack | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory_Controller.MM.Memory_Ack::total 1
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-system.ruby.Directory_Controller.MI.Dirty_Writeback::total 1215921
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-system.ruby.Directory_Controller.XI_M.Memory_Data::total 5932
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 53335 50.00% 50.00% | 53332 50.00% 100.00%
-system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 106667
-system.ruby.Directory_Controller.XI_U.Memory_Ack | 53212 49.99% 49.99% | 53228 50.01% 100.00%
-system.ruby.Directory_Controller.XI_U.Memory_Ack::total 106440
-system.ruby.Directory_Controller.OI_D.Data | 15370 49.84% 49.84% | 15466 50.16% 100.00%
-system.ruby.Directory_Controller.OI_D.Data::total 30836
-system.ruby.Directory_Controller.MD.DMA_ACK | 1742 67.18% 67.18% | 851 32.82% 100.00%
-system.ruby.Directory_Controller.MD.DMA_ACK::total 2593
-system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 249564 99.92% 99.92% | 202 0.08% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 249766
-system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3303262 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.WriteRequest::total 3303265
-system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 8933
-system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.DMA_Ack::total 106667
-system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 499 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Inv_Ack::total 499
-system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.All_Acks::total 106667
-system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 8933
-system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.WriteRequest::total 106667
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 240668 99.93% 99.93% | 165 0.07% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 240833
-system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 8933
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3196598 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 3196598
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 106667
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 499 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 499
-system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 106667
-system.ruby.L1Cache_Controller.Load 167785000 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 837412033 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 159465905 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 20311774 0.00% 0.00%
-system.ruby.L1Cache_Controller.Fwd_GETX 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.Fwd_DMA 899 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 12213133 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 8229365 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 11782494 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 8529231 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Nack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks 3849849 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_Timeout 8229365 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 7020240 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 9572409 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 3720149 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 42 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Load 21110173 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 827832452 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 129700 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 12082835 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 21542467 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 1206008 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 2311586 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Load 1919137 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Store 861844 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout 3517672 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 115730356 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 141996199 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 5917305 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX 44 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Fwd_DMA 899 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 456754 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 11551993 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout 4711693 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data 3720149 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data 129700 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.All_acks 3849849 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 12213133 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 4379516 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Load 5283 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Ifetch 7172 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Store 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack 11782494 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 300341 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Load 590 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Store 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 8228890 0.00% 0.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 16592651 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 3849849 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 8228892 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 12082835 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_GETX 30836 0.00% 0.00%
-system.ruby.L2Cache_Controller.Fwd_DMA 2593 0.00% 0.00%
-system.ruby.L2Cache_Controller.Inv 499 0.00% 0.00%
-system.ruby.L2Cache_Controller.IntAck 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 1280476 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 1688647 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 300341 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 8228890 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 1215921 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 23995626 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 8229365 0.00% 0.00%
-system.ruby.L2Cache_Controller.DmaAck 899 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 1434025 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 408154 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 1119537 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Inv 368 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 21 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 108445 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 300341 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.Inv 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 8228890 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_GETX 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.Fwd_DMA 899 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 11804958 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 31235 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Inv 127 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 217484 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 21255 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 11782494 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.Inv 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 620 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 4379516 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 2569377 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_GETX 30790 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Fwd_DMA 1694 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 1215921 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFGX.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 300341 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 11782494 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 8228890 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 408175 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 408174 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 1150772 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 129700 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 1280472 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 1280472 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.IntAck 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.II.All_Acks 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2569377 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 11804958 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 4379516 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 1215921 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXD.DmaAck 899 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:50:54
-gem5 executing on e108600-lin, pid 17458
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51821888787500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.818011 # Number of seconds simulated
-sim_ticks 51818010617500 # Number of ticks simulated
-final_tick 51818010617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1170120 # Simulator instruction rate (inst/s)
-host_op_rate 1392764 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 73119251351 # Simulator tick rate (ticks/s)
-host_mem_usage 679172 # Number of bytes of host memory used
-host_seconds 708.68 # Real time elapsed on the host
-sim_insts 829238196 # Number of instructions simulated
-sim_ops 987021276 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 290880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 276800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5155828 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 53423624 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 392768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59539900 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5155828 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5155828 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 81086784 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 81107364 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 4545 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 4325 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 84967 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 834757 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6137 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 934731 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1266981 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1269554 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 5613 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 5342 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 99499 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1030986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1149019 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 99499 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 99499 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1564838 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1565235 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1564838 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 5613 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 5342 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 99499 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1031383 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7580 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2714254 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 934731 # Number of read requests accepted
-system.physmem.writeReqs 1269554 # Number of write requests accepted
-system.physmem.readBursts 934731 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1269554 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 59774080 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 48704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 81104832 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 59539900 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 81107364 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 761 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 59992 # Per bank write bursts
-system.physmem.perBankRdBursts::1 60310 # Per bank write bursts
-system.physmem.perBankRdBursts::2 57698 # Per bank write bursts
-system.physmem.perBankRdBursts::3 58037 # Per bank write bursts
-system.physmem.perBankRdBursts::4 57948 # Per bank write bursts
-system.physmem.perBankRdBursts::5 67620 # Per bank write bursts
-system.physmem.perBankRdBursts::6 56261 # Per bank write bursts
-system.physmem.perBankRdBursts::7 53370 # Per bank write bursts
-system.physmem.perBankRdBursts::8 54837 # Per bank write bursts
-system.physmem.perBankRdBursts::9 66514 # Per bank write bursts
-system.physmem.perBankRdBursts::10 61956 # Per bank write bursts
-system.physmem.perBankRdBursts::11 59662 # Per bank write bursts
-system.physmem.perBankRdBursts::12 55006 # Per bank write bursts
-system.physmem.perBankRdBursts::13 54479 # Per bank write bursts
-system.physmem.perBankRdBursts::14 55622 # Per bank write bursts
-system.physmem.perBankRdBursts::15 54658 # Per bank write bursts
-system.physmem.perBankWrBursts::0 77492 # Per bank write bursts
-system.physmem.perBankWrBursts::1 79625 # Per bank write bursts
-system.physmem.perBankWrBursts::2 80003 # Per bank write bursts
-system.physmem.perBankWrBursts::3 79967 # Per bank write bursts
-system.physmem.perBankWrBursts::4 79681 # Per bank write bursts
-system.physmem.perBankWrBursts::5 86821 # Per bank write bursts
-system.physmem.perBankWrBursts::6 77332 # Per bank write bursts
-system.physmem.perBankWrBursts::7 76109 # Per bank write bursts
-system.physmem.perBankWrBursts::8 76222 # Per bank write bursts
-system.physmem.perBankWrBursts::9 83393 # Per bank write bursts
-system.physmem.perBankWrBursts::10 81152 # Per bank write bursts
-system.physmem.perBankWrBursts::11 79739 # Per bank write bursts
-system.physmem.perBankWrBursts::12 76657 # Per bank write bursts
-system.physmem.perBankWrBursts::13 78391 # Per bank write bursts
-system.physmem.perBankWrBursts::14 77174 # Per bank write bursts
-system.physmem.perBankWrBursts::15 77505 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 469 # Number of times write queue was full causing retry
-system.physmem.totGap 51818007690500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 4701 # Read request sizes (log2)
-system.physmem.readPktSize::3 13 # Read request sizes (log2)
-system.physmem.readPktSize::4 2 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 930015 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 1 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1266981 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 899250 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 28995 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 433 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 464 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 936 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 574 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 255 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 80 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 32926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 37724 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 68102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 72474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 75844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 72834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 71244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 73203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 75560 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 73943 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 77939 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 76725 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 72934 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 71213 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 72289 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 71241 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 69956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 69529 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 2492 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1882 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1372 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1160 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1043 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 900 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 849 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 867 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 917 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 711 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 685 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1012 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 811 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 743 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 631 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 652 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 702 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 1158 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 949 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 670 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 1096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 1457 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 599 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1035 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 576881 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 244.207370 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 147.656879 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 284.643014 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 255111 44.22% 44.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 152646 26.46% 70.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 51224 8.88% 79.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 27873 4.83% 84.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 18823 3.26% 87.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12144 2.11% 89.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9162 1.59% 91.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7710 1.34% 92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 42188 7.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 576881 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 67805 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 13.773807 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 23.890121 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 67793 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 5 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 3 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 67805 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 67805 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.689816 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.049494 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.758455 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 55088 81.24% 81.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 9632 14.21% 95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 629 0.93% 96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 315 0.46% 96.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 880 1.30% 98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 141 0.21% 98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 113 0.17% 98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 35 0.05% 98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 64 0.09% 98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 15 0.02% 98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 17 0.03% 98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 506 0.75% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 74 0.11% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 50 0.07% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 77 0.11% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 34 0.05% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 3 0.00% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.00% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 7 0.01% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.00% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 13 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 3 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 4 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 19 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 9 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 6 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 4 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 67805 # Writes before turning the bus around for reads
-system.physmem.totQLat 32840058772 # Total ticks spent queuing
-system.physmem.totMemAccLat 50351996272 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4669850000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 35161.79 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 53911.79 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.15 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
-system.physmem.readRowHits 700734 # Number of row buffer hits during reads
-system.physmem.writeRowHits 923617 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.03 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes
-system.physmem.avgGap 23507852.97 # Average gap between requests
-system.physmem.pageHitRate 73.79 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2121758100 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1127741175 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3364625040 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3325296600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 53356283760.000015 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 43527513060 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 3305473920 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 105977484840 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 78284868000 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 12316974110865 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 12611384893410 # Total energy per rank (pJ)
-system.physmem_0.averagePower 243.378407 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 51713320513020 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 6156853750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 22684760000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 51277629948750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 203866794298 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 75265891230 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 232406369472 # Time in different power states
-system.physmem_1.actEnergy 1997179380 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1061522220 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3303920760 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3289816260 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 51035403120.000008 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 42719469090 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 3040212960 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 99255699990 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 75177553440 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 12322732679115 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 12603635909925 # Total energy per rank (pJ)
-system.physmem_1.averagePower 243.228865 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 51716360660558 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 5564281492 # Time in different power states
-system.physmem_1.memoryStateTime::REF 21699622000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 51302919507000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 195774926499 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 74386011700 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 217666268809 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 216211 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 216211 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16346 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 167307 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 216192 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 0.138766 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 46.526694 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047 216190 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 216192 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 183672 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24269.346988 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20148.872722 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20272.280127 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 181570 98.86% 98.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 1738 0.95% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 90 0.05% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 74 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 86 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 33 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 59 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 183672 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 2036554556 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.701695 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.457514 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 607514500 29.83% 29.83% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1 1429040056 70.17% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 2036554556 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 167308 91.10% 91.10% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 16346 8.90% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 183654 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 216211 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 216211 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183654 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183654 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 399865 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 169128390 # DTB read hits
-system.cpu.dtb.read_misses 159496 # DTB read misses
-system.cpu.dtb.write_hits 153929844 # DTB write hits
-system.cpu.dtb.write_misses 56715 # DTB write misses
-system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 75955 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 8791 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 20041 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 169287886 # DTB read accesses
-system.cpu.dtb.write_accesses 153986559 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 323058234 # DTB hits
-system.cpu.dtb.misses 216211 # DTB misses
-system.cpu.dtb.accesses 323274445 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 123370 # Table walker walks requested
-system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1116 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 111000 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 112116 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27477.773021 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23151.580183 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24996.246984 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 109776 97.91% 97.91% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 1925 1.72% 99.63% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 106 0.09% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 116 0.10% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 77 0.07% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 36 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 73 0.07% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 112116 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 523074000 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 523074000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 523074000 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 111000 99.00% 99.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1116 1.00% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 112116 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112116 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 112116 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 235486 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 829831290 # ITB inst hits
-system.cpu.itb.inst_misses 123370 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 54054 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 829954660 # ITB inst accesses
-system.cpu.itb.hits 829831290 # DTB hits
-system.cpu.itb.misses 123370 # DTB misses
-system.cpu.itb.accesses 829954660 # DTB accesses
-system.cpu.numPwrStateTransitions 32736 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 16368 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 3071765118.618646 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 59759289847.266548 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 7078 43.24% 43.24% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 9254 56.54% 99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988775098960 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 16368 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 1539359155950 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50278651461550 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 103636021235 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16368 # number of quiesce instructions executed
-system.cpu.committedInsts 829238196 # Number of instructions committed
-system.cpu.committedOps 987021276 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 918155469 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 894809 # Number of float alu accesses
-system.cpu.num_func_calls 53301366 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 119804511 # number of instructions that are conditional controls
-system.cpu.num_int_insts 918155469 # number of integer instructions
-system.cpu.num_fp_insts 894809 # number of float instructions
-system.cpu.num_int_register_reads 1221916718 # number of times the integer registers were read
-system.cpu.num_int_register_writes 717363924 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 1441242 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 760964 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 183477837 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 182884399 # number of times the CC registers were written
-system.cpu.num_mem_refs 323042928 # number of memory refs
-system.cpu.num_load_insts 169122320 # Number of load instructions
-system.cpu.num_store_insts 153920608 # Number of store instructions
-system.cpu.num_idle_cycles 100557302923.098053 # Number of idle cycles
-system.cpu.num_busy_cycles 3078718311.901940 # Number of busy cycles
-system.cpu.not_idle_fraction 0.029707 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.970293 # Percentage of idle cycles
-system.cpu.Branches 183328759 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 662135321 67.04% 67.04% # Class of executed instruction
-system.cpu.op_class::IntMult 2232133 0.23% 67.27% # Class of executed instruction
-system.cpu.op_class::IntDiv 98376 0.01% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatAdd 8 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatCmp 13 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatCvt 21 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction
-system.cpu.op_class::FloatMisc 110293 0.01% 67.29% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction
-system.cpu.op_class::MemRead 169008582 17.11% 84.40% # Class of executed instruction
-system.cpu.op_class::MemWrite 153249872 15.52% 99.92% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 113738 0.01% 99.93% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 670736 0.07% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 987619094 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 10318810 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.994503 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 312537175 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 10319322 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 30.286600 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 585910500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994503 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1302212841 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1302212841 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 157972571 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 157972571 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 146050984 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 146050984 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 397864 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 397864 # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data 335205 # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total 335205 # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3722931 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3722931 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4027066 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4027066 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 304358760 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 304358760 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 304756624 # number of overall hits
-system.cpu.dcache.overall_hits::total 304756624 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 5371907 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 5371907 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2231014 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2231014 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1323692 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1323692 # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data 1234314 # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total 1234314 # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 305825 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 305825 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 8837235 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 8837235 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 10160927 # number of overall misses
-system.cpu.dcache.overall_misses::total 10160927 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 92847463000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 92847463000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76601172000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76601172000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25428557000 # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total 25428557000 # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4806019500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 4806019500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 194877192000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 194877192000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 194877192000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 194877192000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 163344478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 163344478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 148281998 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 148281998 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 1721556 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 1721556 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data 1569519 # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total 1569519 # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4028756 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 4028756 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4027067 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4027067 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 313195995 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 313195995 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 314917551 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 314917551 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032887 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.032887 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015046 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015046 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768893 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.768893 # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786428 # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total 0.786428 # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.075911 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.075911 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.028216 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.028216 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.032265 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.032265 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17283.892480 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17283.892480 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.689070 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.689070 # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20601.368047 # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20601.368047 # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15714.933377 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15714.933377 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22051.828655 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22051.828655 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19179.076082 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19179.076082 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 7954497 # number of writebacks
-system.cpu.dcache.writebacks::total 7954497 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22835 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 22835 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21214 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 21214 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 72449 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 72449 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 44049 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 44049 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 44049 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 44049 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5349072 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 5349072 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2209800 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2209800 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1323336 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 1323336 # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1234314 # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total 1234314 # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233376 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 233376 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 8793186 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 8793186 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 10116522 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 10116522 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 33620 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 67244 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86573126000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 86573126000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73656101500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 73656101500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23406113500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23406113500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24194243000 # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24194243000 # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3299673500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3299673500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 184423470500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 184423470500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207829584000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 207829584000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6212445000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6212445000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6212445000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 6212445000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032747 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032747 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014903 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014903 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.768686 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.768686 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786428 # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786428 # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057928 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057928 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.028076 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16184.700075 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16184.700075 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33331.569147 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33331.569147 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17687.203779 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17687.203779 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19601.368047 # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19601.368047 # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14138.872463 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14138.872463 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20973.452683 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20973.452683 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20543.580491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20543.580491 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184784.205830 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184784.205830 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92386.606984 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92386.606984 # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 13796932 # number of replacements
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-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012830 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018509 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.092013 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.039415 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012830 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018509 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.092013 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.039415 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 130884.818482 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 121080.115607 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 126104.058625 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17797.566658 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17797.566658 # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96235.286287 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96235.286287 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115208.989898 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115208.989898 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115980.499383 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115980.499383 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 104305.836100 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 104305.836100 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 1160350 # number of writebacks
-system.cpu.l2cache.writebacks::total 1160350 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4545 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4325 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3863 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 3863 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 548383 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 80279 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 80279 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 287555 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 287555 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 516512 # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total 516512 # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4545 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4325 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 80279 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 835938 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4325 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 80279 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 38345 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71969 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 549421500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 480421500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1029843000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 73648000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 73648000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47289965000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47289965000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8446072500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8446072500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30475204536 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30475204536 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9640713000 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9640713000 # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 549421500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 480421500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8446072500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77765169536 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 87241085036 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 549421500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 480421500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8446072500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77765169536 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 87241085036 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340544500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5791390500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6131935000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340544500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5791390500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6131935000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015087 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126436 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126436 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.251639 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.251639 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005818 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.041640 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.041640 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.418461 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.418461 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.039415 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.039415 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116104.058625 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19064.975408 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19064.975408 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86235.286287 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86235.286287 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105208.989898 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105208.989898 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105980.436911 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105980.436911 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18665.031984 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18665.031984 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172260.276621 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159914.852002 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86125.014871 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85202.448276 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 48796648 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 24679855 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2089 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 1038155 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 21742291 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33624 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33624 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 9114847 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 13796932 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2555043 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 30556 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 30557 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2179247 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2179247 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 13797449 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6908747 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1261981 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1234328 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41401280 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31154016 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 602385 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 985352 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 74143033 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766059284 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1090777710 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1869336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2834080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2861540410 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1794516 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 77615256 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 26600840 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.020202 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.140692 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 26063442 97.98% 97.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 537398 2.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 26600840 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 46435675500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1669386 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 20700898500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14310442440 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 368718000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 631092000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40260 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40260 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136485 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136485 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353490 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492208 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 41845500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 38606000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 569335764 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115507 # number of replacements
-system.iocache.tags.tagsinuse 10.457942 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115523 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13151557544000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.511326 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.946616 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.219458 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.434164 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.653621 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040082 # Number of tag accesses
-system.iocache.tags.data_accesses 1040082 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115565 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115525 # number of overall misses
-system.iocache.overall_misses::total 115565 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1980781165 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1985867665 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13389793099 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13389793099 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15370574264 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15376011764 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15370574264 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15376011764 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 223539.235414 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 223181.351427 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125532.448614 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125532.448614 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 133050.765924 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 133050.765924 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 49780 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3342 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 14.895272 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106631 # number of writebacks
-system.iocache.writebacks::total 106631 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537731165 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1540967665 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8050946475 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8050946475 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 9588677640 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9592115140 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 9588677640 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9592115140 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173539.235414 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 173181.351427 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75479.510191 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75479.510191 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 3026927 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 1497963 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3722 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 38345 # Transaction distribution
-system.membus.trans_dist::ReadResp 423947 # Transaction distribution
-system.membus.trans_dist::WriteReq 33624 # Transaction distribution
-system.membus.trans_dist::WriteResp 33624 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1266981 # Transaction distribution
-system.membus.trans_dist::CleanEvict 198449 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4422 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
-system.membus.trans_dist::ReadExReq 547827 # Transaction distribution
-system.membus.trans_dist::ReadExResp 547827 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 385602 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 623176 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 27559 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3733842 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3863202 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237209 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237209 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4100411 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 133430112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 133599618 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7217152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7217152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140816770 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 30980 # Total snoops (count)
-system.membus.snoopTraffic 218496 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1632997 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.019173 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.137134 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1601687 98.08% 98.08% # Request fanout histogram
-system.membus.snoop_fanout::1 31310 1.92% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1632997 # Request fanout histogram
-system.membus.reqLayer0.occupancy 106607500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5784000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8217045206 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5023572568 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 73701370 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000040] Console: colour dummy device 80x25\r
-[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000046] pid_max: default: 32768 minimum: 301\r
-[ 0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000252] hw perfevents: no hardware support available\r
-[ 1.060135] CPU1: failed to come online\r
-[ 2.080266] CPU2: failed to come online\r
-[ 3.100397] CPU3: failed to come online\r
-[ 3.100402] Brought up 1 CPUs\r
-[ 3.100404] SMP: Total of 1 processors activated.\r
-[ 3.100503] devtmpfs: initialized\r
-[ 3.101571] atomic64_test: passed\r
-[ 3.101646] regulator-dummy: no parameters\r
-[ 3.102401] NET: Registered protocol family 16\r
-[ 3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.103290] Serial: AMBA PL011 UART driver\r
-[ 3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.104302] console [ttyAMA0] enabled\r
-[ 3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.131002] 3V3: 3300 mV \r
-[ 3.131076] vgaarb: loaded\r
-[ 3.131168] SCSI subsystem initialized\r
-[ 3.131239] libata version 3.00 loaded.\r
-[ 3.131320] usbcore: registered new interface driver usbfs\r
-[ 3.131346] usbcore: registered new interface driver hub\r
-[ 3.131401] usbcore: registered new device driver usb\r
-[ 3.131444] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131477] PTP clock support registered\r
-[ 3.131699] Switched to clocksource arch_sys_counter\r
-[ 3.133732] NET: Registered protocol family 2\r
-[ 3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.133949] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.133976] TCP: reno registered\r
-[ 3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134067] NET: Registered protocol family 1\r
-[ 3.134134] RPC: Registered named UNIX socket transport module.\r
-[ 3.134145] RPC: Registered udp transport module.\r
-[ 3.134154] RPC: Registered tcp transport module.\r
-[ 3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.134177] PCI: CLS 0 bytes, default 64\r
-[ 3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.138130] fuse init (API version 7.23)\r
-[ 3.138291] msgmni has been set to 469\r
-[ 3.142786] io scheduler noop registered\r
-[ 3.142885] io scheduler cfq registered (default)\r
-[ 3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.143688] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.143727] pci_bus 0000:00: scanning bus\r
-[ 3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.143848] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.143860] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.143873] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.143886] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.143899] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.143970] pci_bus 0000:00: fixups for bus\r
-[ 3.143980] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.144020] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.144030] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.144044] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.144054] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.144114] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.144127] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.144141] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.144154] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.144168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.145534] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.145577] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.146149] scsi0 : ata_piix\r
-[ 3.146327] scsi1 : ata_piix\r
-[ 3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.146632] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301744] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301779] ata1.00: configured for UDMA/33\r
-[ 3.301852] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.302142] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.302382] sda: sda1\r
-[ 3.302584] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.422289] usbcore: registered new interface driver usb-storage\r
-[ 3.422380] mousedev: PS/2 mouse device common for all mice\r
-[ 3.422670] usbcore: registered new interface driver usbhid\r
-[ 3.422681] usbhid: USB HID core driver\r
-[ 3.422731] TCP: cubic registered\r
-[ 3.422741] NET: Registered protocol family 17\r
-\0[ 3.423331] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.423377] devtmpfs: mounted\r
-[ 3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.470296] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.606651] random: dd urandom read with 20 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.801935] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.apicbridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-master=system.membus.slave[0]
-slave=system.iobus.master[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=apic_clk_domain branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=true
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.dtb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.dtb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=1
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[3]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.itb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.itb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[4]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
-slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[8]
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[3]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0x8086
-warn: x86 cpuid: unknown family 0x8086
-warn: x86 cpuid: unknown family 0x8086
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Dec 4 2015 15:10:31
-gem5 started Dec 4 2015 15:13:28
-gem5 executing on e104799-lin, pid 29885
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5144274809000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.230834 # Number of seconds simulated
-sim_ticks 5230834315000 # Number of ticks simulated
-final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 207627 # Simulator instruction rate (inst/s)
-host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
-host_mem_usage 751184 # Number of bytes of host memory used
-host_seconds 1964.86 # Real time elapsed on the host
-sim_insts 407959263 # Number of instructions simulated
-sim_ops 806441023 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 181488 # Number of read requests accepted
-system.physmem.writeReqs 145215 # Number of write requests accepted
-system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11156 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11363 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11879 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11399 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11231 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10765 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10426 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10967 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10953 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10767 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11374 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11178 # Per bank write bursts
-system.physmem.perBankRdBursts::12 12058 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12613 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11821 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11247 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9305 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9167 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9550 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8690 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9047 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8333 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8814 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9019 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9026 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9076 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9210 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9034 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9456 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9034 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 5230834265500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 181488 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 145215 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
-system.physmem.totQLat 2046328821 # Total ticks spent queuing
-system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
-system.physmem.readRowHits 147319 # Number of row buffer hits during reads
-system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
-system.physmem.avgGap 16010977.14 # Average gap between requests
-system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
-system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
-system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 94759510 # Number of BP lookups
-system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 0 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 480891878 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
-system.cpu.iq.rate 1.759858 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
-system.cpu.iew.exec_branches 84810471 # Number of branches executed
-system.cpu.iew.exec_stores 9925440 # Number of stores executed
-system.cpu.iew.exec_rate 1.747546 # Inst execution rate
-system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 651539387 # num instructions producing a value
-system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407959263 # Number of instructions committed
-system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22368017 # Number of memory references committed
-system.cpu.commit.loads 13951296 # Number of loads committed
-system.cpu.commit.membars 447981 # Number of memory barriers committed
-system.cpu.commit.branches 82209281 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155854 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 1325977641 # The number of ROB reads
-system.cpu.rob.rob_writes 1738470998 # The number of ROB writes
-system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407959263 # Number of Instructions Simulated
-system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads
-system.cpu.int_regfile_writes 669949193 # number of integer regfile writes
-system.cpu.fp_regfile_reads 124 # number of floating regfile reads
-system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads
-system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes
-system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads
-system.cpu.misc_regfile_writes 400822 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 1703381 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits
-system.cpu.dcache.overall_hits::total 21312315 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses
-system.cpu.dcache.overall_misses::total 2620606 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 20451778744 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 52129012244 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 52129012244 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 52129012244 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 52129012244 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 15046860 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 15046860 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8407012 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8407012 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 479049 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 479049 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency
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-system.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
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-system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
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-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
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-system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor
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-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy
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-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
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-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
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-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
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-system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses
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-system.cpu.icache.overall_hits::total 11313989 # number of overall hits
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-system.cpu.icache.overall_misses::total 1443748 # number of overall misses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency
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-system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
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-system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy
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-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
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-system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
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-system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
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-system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
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-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
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-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
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-system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
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-system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id
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-system.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits
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-system.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits
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-system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits
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-system.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits
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-system.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2949027 # number of overall hits
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-system.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses
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-system.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses
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-system.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses)
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-system.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
-system.cpu.l2cache.writebacks::total 98548 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
-system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47572 # number of replacements
-system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428643 # Number of tag accesses
-system.iocache.tags.data_accesses 428643 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
-system.iocache.overall_misses::total 47627 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
-system.membus.trans_dist::ReadReq 573476 # Transaction distribution
-system.membus.trans_dist::ReadResp 628544 # Transaction distribution
-system.membus.trans_dist::WriteReq 13974 # Transaction distribution
-system.membus.trans_dist::WriteResp 13974 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution
-system.membus.trans_dist::CleanEvict 10528 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 20 # Transaction distribution
-system.membus.trans_dist::ReadExReq 127539 # Transaction distribution
-system.membus.trans_dist::ReadExResp 127538 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution
-system.membus.trans_dist::MessageReq 1666 # Transaction distribution
-system.membus.trans_dist::MessageResp 1666 # Transaction distribution
-system.membus.trans_dist::BadAddressError 611 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1549 # Total snoops (count)
-system.membus.snoop_fanout::samples 976982 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram
-system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 976982 # Request fanout histogram
-system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
- BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
- BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
- BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
-end_pfn_map = 1048576\r
-kernel direct mapping tables up to 100000000 @ 8000-d000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
- DMA 0 -> 4096\r
- DMA32 4096 -> 1048576\r
- Normal 1048576 -> 1048576\r
-early_node_map[2] active PFN ranges\r
- 0: 0 -> 159\r
- 0: 256 -> 32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-I/O APIC #1 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 1\r
-swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000\r
-swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000\r
-Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
-Built 1 zonelists. Total pages: 30610\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.001 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-using mwait in idle threads.\r
-CPU: Fake M5 x86_64 CPU stepping 01\r
-ACPI: Core revision 20070126\r
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
-ACPI: Unable to load the System Description Tables\r
-Using local APIC timer interrupts.\r
-result 7812523\r
-Detected 7.812 MHz APIC timer.\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-ACPI: Interpreter disabled.\r
-Linux Plug and Play Support v0.97 (c) Adam Belay\r
-pnp: PnP ACPI: disabled\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
-PCI-GART: No AMD northbridge found.\r
-NET: Registered protocol family 2\r
-Time: tsc clocksource has been installed.\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-PNP: No PS/2 controller found. Probing ports directly.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-NET: Registered protocol family 17\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 232k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus mem_ctrls pc ruby smbios_table sys_port_proxy voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.ruby.l1_cntrl0.sequencer.slave[4]
-int_slave=system.ruby.l1_cntrl0.sequencer.master[1]
-pio=system.ruby.l1_cntrl0.sequencer.master[0]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.ruby.l1_cntrl1.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu1.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu1.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[3]
-
-[system.cpu1.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu1.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.ruby.l1_cntrl1.sequencer.slave[4]
-int_slave=system.ruby.l1_cntrl1.sequencer.master[1]
-pio=system.ruby.l1_cntrl1.sequencer.master[0]
-
-[system.cpu1.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu1.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[2]
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 system.intel_mp_table.base_entries33
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPProcessor
-bootstrap=false
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=1
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=2
-version=17
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries33]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave[0]
-slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[12]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.master[0]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.ruby.dma_cntrl0.dma_sequencer.slave[0]
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=2
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[0]
-pio=system.iobus.master[8]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 dma_cntrl0 io_controller l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=2
-number_of_virtual_networks=3
-phys_mem=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-eventq_index=0
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_mem_ctrl_latency=1
-transitions_per_cycle=4
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=134217728
-version=0
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.ruby.dma_cntrl0]
-type=DMA_Controller
-children=dma_sequencer mandatoryQueue requestToDir responseFromDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
-eventq_index=0
-mandatoryQueue=system.ruby.dma_cntrl0.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.dma_cntrl0.requestToDir
-request_latency=6
-responseFromDir=system.ruby.dma_cntrl0.responseFromDir
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=4
-version=0
-
-[system.ruby.dma_cntrl0.dma_sequencer]
-type=DMASequencer
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.pc.south_bridge.ide.dma
-
-[system.ruby.dma_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dma_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.ruby.dma_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.ruby.io_controller]
-type=DMA_Controller
-children=dma_sequencer mandatoryQueue requestToDir responseFromDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-dma_sequencer=system.ruby.io_controller.dma_sequencer
-eventq_index=0
-mandatoryQueue=system.ruby.io_controller.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.io_controller.requestToDir
-request_latency=6
-responseFromDir=system.ruby.io_controller.responseFromDir
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-version=1
-
-[system.ruby.io_controller.dma_sequencer]
-type=DMASequencer
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=1
-slave=system.iobus.master[19]
-
-[system.ruby.io_controller.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.io_controller.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[11]
-
-[system.ruby.io_controller.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl0.optionalQueue
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=4
-unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-eventq_index=0
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-sys=system
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
-mem_master_port=system.iobus.slave[2]
-pio_master_port=system.iobus.slave[1]
-pio_slave_port=system.iobus.master[17]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
-
-[system.ruby.l1_cntrl0.unblockFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl1.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl1.optionalQueue
-prefetcher=system.ruby.l1_cntrl1.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl1.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl1.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl1.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl1.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.ruby.l1_cntrl1.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=4
-unblockFromL1Cache=system.ruby.l1_cntrl1.unblockFromL1Cache
-version=1
-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl1.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl1.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.l1_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl1.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl1.prefetcher]
-type=Prefetcher
-cross_page=false
-eventq_index=0
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-sys=system
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl1.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l1_cntrl1.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl1.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l1_cntrl1.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl1.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.l1_cntrl1.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
-mem_master_port=system.iobus.slave[4]
-pio_master_port=system.iobus.slave[3]
-pio_slave_port=system.iobus.master[18]
-slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master
-
-[system.ruby.l1_cntrl1.unblockFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache
-DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-eventq_index=0
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-recycle_latency=10
-responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
-responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
-ruby_system=system.ruby
-system=system
-to_l1_latency=1
-transitions_per_cycle=4
-unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache
-version=0
-
-[system.ruby.l2_cntrl0.DirRequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=4194304
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=4194304
-
-[system.ruby.l2_cntrl0.responseFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.ruby.l2_cntrl0.responseToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.ruby.l2_cntrl0.unblockToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 routers4 routers5 routers6
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-eventq_index=0
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-[system.ruby.network.routers6.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers6.port_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0x8086
-warn: instruction 'wbinvd' unimplemented
-warn: instruction 'wbinvd' unimplemented
-warn: x86 cpuid: unknown family 0x8086
-hack: Assuming logical destinations are 1 << id.
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
+++ /dev/null
-Redirecting stdout to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 15 2016 21:26:21
-gem5 started Mar 15 2016 21:35:42
-gem5 executing on phenom, pid 15979
-command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5220166723500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.220167 # Number of seconds simulated
-sim_ticks 5220166723500 # Number of ticks simulated
-final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 281505 # Simulator instruction rate (inst/s)
-host_op_rate 546613 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9727443238 # Simulator tick rate (ticks/s)
-host_mem_usage 784792 # Number of bytes of host memory used
-host_seconds 536.64 # Real time elapsed on the host
-sim_insts 151067812 # Number of instructions simulated
-sim_ops 293336428 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11621312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 11621312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9422976 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 9422976 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 181583 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 181583 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 147234 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 147234 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 2226234 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 2226234 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805110 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1805110 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 4031344 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 4031344 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 181583 # Number of read requests accepted
-system.mem_ctrls.writeReqs 147234 # Number of write requests accepted
-system.mem_ctrls.readBursts 181583 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 147234 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 11591808 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 29504 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 9419008 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 11621312 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 9422976 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 11329 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 10774 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 10935 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 11505 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 11170 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 10899 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 11836 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 10884 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 12484 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 12159 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 11756 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 12007 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 11147 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 10761 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 10863 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 10613 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 10067 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 9205 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 8897 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 9266 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 9038 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 9160 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 9230 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 8385 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 9312 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 9251 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 9047 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 9790 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 9121 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 9097 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 9389 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 8917 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 5220166614000 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 181583 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 147234 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 181021 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 101 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::15 2012 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::31 8469 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 8257 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 137 # What write queue length does an incoming req see
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-system.mem_ctrls.bytesPerActivate::samples 59923 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 350.629174 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 206.226666 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 350.561474 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 19936 33.27% 33.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 13794 23.02% 56.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 6108 10.19% 66.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3634 6.06% 72.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 2579 4.30% 76.85% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 1995 3.33% 80.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1624 2.71% 82.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1412 2.36% 85.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 8841 14.75% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 59923 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 8207 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 22.065919 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 311.578267 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023 8201 99.93% 99.93% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 8207 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 8207 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.932497 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.599692 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 3.953739 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 6146 74.89% 74.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 20 0.24% 75.13% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 127 1.55% 76.68% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 26 0.32% 77.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 39 0.48% 77.47% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 486 5.92% 83.39% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 193 2.35% 85.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 617 7.52% 93.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 104 1.27% 95.24% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 8 0.10% 95.33% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 15 0.18% 95.52% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 293 3.57% 99.09% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.13% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 1 0.01% 99.15% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 3 0.04% 99.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32 10 0.12% 99.31% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34 2 0.02% 99.39% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35 2 0.02% 99.42% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36 5 0.06% 99.48% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.49% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::38 5 0.06% 99.55% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::39 2 0.02% 99.57% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.61% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41 5 0.06% 99.67% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42 2 0.02% 99.70% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.73% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44 3 0.04% 99.77% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45 5 0.06% 99.83% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::46 2 0.02% 99.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.87% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::49 2 0.02% 99.94% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 8207 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 1926054246 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 5322091746 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 905610000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 10634.02 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 29384.02 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 146815 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 121555 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.06 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 15875598.32 # Average gap between requests
-system.mem_ctrls.pageHitRate 81.74 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 222014520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 121138875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 696781800 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 474647040 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 139500530325 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 3009726629250 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 3491697148290 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 668.887101 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5006844557250 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 174312580000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 39009485750 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 231003360 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 126043500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 715962000 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 479027520 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 139411599210 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3009804639000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3491723681070 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 668.892184 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5006961679500 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 174312580000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 38884946750 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10440333447 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.committedInsts 100619599 # Number of instructions committed
-system.cpu0.committedOps 194912227 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 182208047 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu0.num_func_calls 1789060 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 17876463 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 182208047 # number of integer instructions
-system.cpu0.num_fp_insts 48 # number of float instructions
-system.cpu0.num_int_register_reads 340866599 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 155423898 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 104641558 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 75150612 # number of times the CC registers were written
-system.cpu0.num_mem_refs 18466644 # number of memory refs
-system.cpu0.num_load_insts 11577076 # Number of load instructions
-system.cpu0.num_store_insts 6889568 # Number of store instructions
-system.cpu0.num_idle_cycles 9942379374.520096 # Number of idle cycles
-system.cpu0.num_busy_cycles 497954072.479905 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.047695 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.952305 # Percentage of idle cycles
-system.cpu0.Branches 20277624 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 187137 0.10% 0.10% # Class of executed instruction
-system.cpu0.op_class::IntAlu 176059705 90.33% 90.42% # Class of executed instruction
-system.cpu0.op_class::IntMult 119089 0.06% 90.48% # Class of executed instruction
-system.cpu0.op_class::IntDiv 84733 0.04% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 16 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.53% # Class of executed instruction
-system.cpu0.op_class::MemRead 11572910 5.94% 96.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6889568 3.53% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 194913158 # Class of executed instruction
-system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu1.numCycles 10439192066 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 50448213 # Number of instructions committed
-system.cpu1.committedOps 98424201 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 91824874 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu1.num_func_calls 991908 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 9137643 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 91824874 # number of integer instructions
-system.cpu1.num_fp_insts 48 # number of float instructions
-system.cpu1.num_int_register_reads 171791517 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 78447804 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 52143431 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 36991088 # number of times the CC registers were written
-system.cpu1.num_mem_refs 8627580 # number of memory refs
-system.cpu1.num_load_insts 5530314 # Number of load instructions
-system.cpu1.num_store_insts 3097266 # Number of store instructions
-system.cpu1.num_idle_cycles 10278680276.738028 # Number of idle cycles
-system.cpu1.num_busy_cycles 160511789.261972 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.015376 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.984624 # Percentage of idle cycles
-system.cpu1.Branches 10492962 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 118368 0.12% 0.12% # Class of executed instruction
-system.cpu1.op_class::IntAlu 89576077 91.01% 91.13% # Class of executed instruction
-system.cpu1.op_class::IntMult 66940 0.07% 91.20% # Class of executed instruction
-system.cpu1.op_class::IntDiv 40064 0.04% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 16 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.24% # Class of executed instruction
-system.cpu1.op_class::MemRead 5526131 5.61% 96.85% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3097266 3.15% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 98424862 # Class of executed instruction
-system.iobus.trans_dist::ReadReq 883871 # Transaction distribution
-system.iobus.trans_dist::ReadResp 883871 # Transaction distribution
-system.iobus.trans_dist::WriteReq 36792 # Transaction distribution
-system.iobus.trans_dist::WriteResp 36792 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1835 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1835 # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6166 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1234 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14088 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811278 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 2214 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1753576 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4922 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 876 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 13284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 72 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4620 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 92 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 88002 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1844996 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3506 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2468 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7044 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622550 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 360 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 4401 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2099537 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1752 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6642 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 144 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9237 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 53095 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2159468 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 9083500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 944500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 84500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 51500 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 21127500 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 458718000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 1783484 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 31828500 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 2500 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 20524000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 410414499 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 7700146 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 1751500 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2638190 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1947717500 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 60917000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.ruby.clk_domain.clock 500 # Clock period in ticks
-system.ruby.delayHist::bucket_size 4 # delay histogram for all message
-system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 11184165 # delay histogram for all message
-system.ruby.delayHist::mean 0.431974 # delay histogram for all message
-system.ruby.delayHist::stdev 1.810021 # delay histogram for all message
-system.ruby.delayHist | 10580766 94.60% 94.60% | 2101 0.02% 94.62% | 600708 5.37% 99.99% | 188 0.00% 100.00% | 323 0.00% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 11184165 # delay histogram for all message
-system.ruby.outstanding_req_hist_seqr::bucket_size 1
-system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 197976054
-system.ruby.outstanding_req_hist_seqr::mean 1.000129
-system.ruby.outstanding_req_hist_seqr::gmean 1.000089
-system.ruby.outstanding_req_hist_seqr::stdev 0.011359
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197950506 99.99% 99.99% | 25548 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 197976054
-system.ruby.latency_hist_seqr::bucket_size 128
-system.ruby.latency_hist_seqr::max_bucket 1279
-system.ruby.latency_hist_seqr::samples 197976053
-system.ruby.latency_hist_seqr::mean 1.340875
-system.ruby.latency_hist_seqr::gmean 1.042170
-system.ruby.latency_hist_seqr::stdev 5.085216
-system.ruby.latency_hist_seqr | 197940485 99.98% 99.98% | 26707 0.01% 100.00% | 2933 0.00% 100.00% | 3350 0.00% 100.00% | 1606 0.00% 100.00% | 905 0.00% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 197976053
-system.ruby.hit_latency_hist_seqr::bucket_size 1
-system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 195263006
-system.ruby.hit_latency_hist_seqr::mean 1
-system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195263006 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 195263006
-system.ruby.miss_latency_hist_seqr::bucket_size 128
-system.ruby.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.miss_latency_hist_seqr::samples 2713047
-system.ruby.miss_latency_hist_seqr::mean 25.874270
-system.ruby.miss_latency_hist_seqr::gmean 20.370607
-system.ruby.miss_latency_hist_seqr::stdev 35.731774
-system.ruby.miss_latency_hist_seqr | 2677479 98.69% 98.69% | 26707 0.98% 99.67% | 2933 0.11% 99.78% | 3350 0.12% 99.90% | 1606 0.06% 99.96% | 905 0.03% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 2713047
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 16414226 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 1206044 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17620270 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 114568727 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 549758 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 115118485 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 7924165 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 686474 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8610639 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 56355888 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 270771 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 56626659 # Number of cache demand accesses
-system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits 2479845 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 233202 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2713047 # Number of cache demand accesses
-system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 0.058980
-system.ruby.network.routers0.msg_count.Control::0 1755802
-system.ruby.network.routers0.msg_count.Request_Control::2 45794
-system.ruby.network.routers0.msg_count.Response_Data::1 1784920
-system.ruby.network.routers0.msg_count.Response_Control::1 1171907
-system.ruby.network.routers0.msg_count.Response_Control::2 1168239
-system.ruby.network.routers0.msg_count.Writeback_Data::0 411948
-system.ruby.network.routers0.msg_count.Writeback_Data::1 195
-system.ruby.network.routers0.msg_count.Writeback_Control::0 715361
-system.ruby.network.routers0.msg_bytes.Control::0 14046416
-system.ruby.network.routers0.msg_bytes.Request_Control::2 366352
-system.ruby.network.routers0.msg_bytes.Response_Data::1 128514240
-system.ruby.network.routers0.msg_bytes.Response_Control::1 9375256
-system.ruby.network.routers0.msg_bytes.Response_Control::2 9345912
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 29660256
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 14040
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 5722888
-system.ruby.network.routers1.percent_links_utilized 0.031273
-system.ruby.network.routers1.msg_count.Control::0 957245
-system.ruby.network.routers1.msg_count.Request_Control::2 41954
-system.ruby.network.routers1.msg_count.Response_Data::1 983466
-system.ruby.network.routers1.msg_count.Response_Control::1 655818
-system.ruby.network.routers1.msg_count.Response_Control::2 654857
-system.ruby.network.routers1.msg_count.Writeback_Data::0 160205
-system.ruby.network.routers1.msg_count.Writeback_Data::1 305
-system.ruby.network.routers1.msg_count.Writeback_Control::0 454250
-system.ruby.network.routers1.msg_bytes.Control::0 7657960
-system.ruby.network.routers1.msg_bytes.Request_Control::2 335632
-system.ruby.network.routers1.msg_bytes.Response_Data::1 70809552
-system.ruby.network.routers1.msg_bytes.Response_Control::1 5246544
-system.ruby.network.routers1.msg_bytes.Response_Control::2 5238856
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 11534760
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 21960
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 3634000
-system.ruby.network.routers2.percent_links_utilized 0.094749
-system.ruby.network.routers2.msg_count.Control::0 2894160
-system.ruby.network.routers2.msg_count.Request_Control::2 85903
-system.ruby.network.routers2.msg_count.Response_Data::1 2948232
-system.ruby.network.routers2.msg_count.Response_Control::1 1907805
-system.ruby.network.routers2.msg_count.Response_Control::2 1823096
-system.ruby.network.routers2.msg_count.Writeback_Data::0 572153
-system.ruby.network.routers2.msg_count.Writeback_Data::1 500
-system.ruby.network.routers2.msg_count.Writeback_Control::0 1169611
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-system.ruby.network.routers3.msg_count.Response_Control::1 132538
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-system.ruby.network.routers5.percent_links_utilized 0
-system.ruby.network.routers6.percent_links_utilized 0.032061
-system.ruby.network.routers6.msg_count.Control::0 2894160
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-system.ruby.network.msg_count.Control 8682480
-system.ruby.network.msg_count.Request_Control 261399
-system.ruby.network.msg_count.Response_Data 9003411
-system.ruby.network.msg_count.Response_Control 11271390
-system.ruby.network.msg_count.Writeback_Data 1717959
-system.ruby.network.msg_count.Writeback_Control 3791697
-system.ruby.network.msg_byte.Control 69459840
-system.ruby.network.msg_byte.Request_Control 2091192
-system.ruby.network.msg_byte.Response_Data 648245592
-system.ruby.network.msg_byte.Response_Control 90171120
-system.ruby.network.msg_byte.Writeback_Data 123693048
-system.ruby.network.msg_byte.Writeback_Control 30333576
-system.ruby.network.routers0.throttle0.link_utilization 0.080870
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 45794
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-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 18453
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-system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 45794
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-system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 639112
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-system.ruby.network.routers6.throttle2.msg_count.Control::0 2713047
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-system.ruby.network.routers6.throttle5.link_utilization 0
-system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 6277907 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.731657 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 2.309527 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5704590 90.87% 90.87% | 579 0.01% 90.88% | 572160 9.11% 99.99% | 182 0.00% 99.99% | 317 0.01% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6277907 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 4818510 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.049390 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.622960 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4787836 99.36% 99.36% | 592 0.01% 99.38% | 677 0.01% 99.39% | 845 0.02% 99.41% | 28317 0.59% 99.99% | 231 0.00% 100.00% | 4 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 4818510 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 87748 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.000137 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.016538 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 87742 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 87748 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 128
-system.ruby.LD.latency_hist_seqr::max_bucket 1279
-system.ruby.LD.latency_hist_seqr::samples 15434919
-system.ruby.LD.latency_hist_seqr::mean 2.853771
-system.ruby.LD.latency_hist_seqr::gmean 1.313299
-system.ruby.LD.latency_hist_seqr::stdev 9.010453
-system.ruby.LD.latency_hist_seqr | 15420072 99.90% 99.90% | 12855 0.08% 99.99% | 824 0.01% 99.99% | 752 0.00% 100.00% | 311 0.00% 100.00% | 93 0.00% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 15434919
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 14000797
-system.ruby.LD.hit_latency_hist_seqr::mean 1
-system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 14000797 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 14000797
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.LD.miss_latency_hist_seqr::samples 1434122
-system.ruby.LD.miss_latency_hist_seqr::mean 20.951441
-system.ruby.LD.miss_latency_hist_seqr::gmean 18.789020
-system.ruby.LD.miss_latency_hist_seqr::stdev 22.643422
-system.ruby.LD.miss_latency_hist_seqr | 1419275 98.96% 98.96% | 12855 0.90% 99.86% | 824 0.06% 99.92% | 752 0.05% 99.97% | 311 0.02% 99.99% | 93 0.01% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 1434122
-system.ruby.ST.latency_hist_seqr::bucket_size 128
-system.ruby.ST.latency_hist_seqr::max_bucket 1279
-system.ruby.ST.latency_hist_seqr::samples 9614411
-system.ruby.ST.latency_hist_seqr::mean 3.236789
-system.ruby.ST.latency_hist_seqr::gmean 1.144007
-system.ruby.ST.latency_hist_seqr::stdev 17.965589
-system.ruby.ST.latency_hist_seqr | 9599857 99.85% 99.85% | 8650 0.09% 99.94% | 1610 0.02% 99.96% | 2319 0.02% 99.98% | 1166 0.01% 99.99% | 762 0.01% 100.00% | 3 0.00% 100.00% | 22 0.00% 100.00% | 17 0.00% 100.00% | 5 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 9614411
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
-system.ruby.ST.hit_latency_hist_seqr::samples 9260487
-system.ruby.ST.hit_latency_hist_seqr::mean 1
-system.ruby.ST.hit_latency_hist_seqr::gmean 1
-system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9260487 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 9260487
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.miss_latency_hist_seqr::samples 353924
-system.ruby.ST.miss_latency_hist_seqr::mean 61.762782
-system.ruby.ST.miss_latency_hist_seqr::gmean 38.656662
-system.ruby.ST.miss_latency_hist_seqr::stdev 72.192186
-system.ruby.ST.miss_latency_hist_seqr | 339370 95.89% 95.89% | 8650 2.44% 98.33% | 1610 0.45% 98.79% | 2319 0.66% 99.44% | 1166 0.33% 99.77% | 762 0.22% 99.99% | 3 0.00% 99.99% | 22 0.01% 99.99% | 17 0.00% 100.00% | 5 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 353924
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 128
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279
-system.ruby.IFETCH.latency_hist_seqr::samples 171745144
-system.ruby.IFETCH.latency_hist_seqr::mean 1.087707
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.013816
-system.ruby.IFETCH.latency_hist_seqr::stdev 1.870223
-system.ruby.IFETCH.latency_hist_seqr | 171739420 100.00% 100.00% | 4825 0.00% 100.00% | 474 0.00% 100.00% | 262 0.00% 100.00% | 112 0.00% 100.00% | 43 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 171745144
-system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
-system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 170924615
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170924615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 170924615
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 820529
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.358062
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.674355
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 19.917428
-system.ruby.IFETCH.miss_latency_hist_seqr | 814805 99.30% 99.30% | 4825 0.59% 99.89% | 474 0.06% 99.95% | 262 0.03% 99.98% | 112 0.01% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 820529
-system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128
-system.ruby.RMW_Read.latency_hist_seqr::max_bucket 1279
-system.ruby.RMW_Read.latency_hist_seqr::samples 500947
-system.ruby.RMW_Read.latency_hist_seqr::mean 4.014067
-system.ruby.RMW_Read.latency_hist_seqr::gmean 1.503920
-system.ruby.RMW_Read.latency_hist_seqr::stdev 10.213309
-system.ruby.RMW_Read.latency_hist_seqr | 500762 99.96% 99.96% | 143 0.03% 99.99% | 15 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.latency_hist_seqr::total 500947
-system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1
-system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9
-system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434941
-system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1
-system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1
-system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434941 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist_seqr::total 434941
-system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128
-system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66006
-system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.875011
-system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.132571
-system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.367061
-system.ruby.RMW_Read.miss_latency_hist_seqr | 65821 99.72% 99.72% | 143 0.22% 99.94% | 15 0.02% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist_seqr::total 66006
-system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64
-system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639
-system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340316
-system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.332085
-system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.406714
-system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.468226
-system.ruby.Locked_RMW_Read.latency_hist_seqr | 339968 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 7 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340316
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket 9
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301850
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301850 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301850
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38466
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.632403
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.474141
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 16.027002
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 38118 99.10% 99.10% | 90 0.23% 99.33% | 233 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 7 0.02% 99.96% | 5 0.01% 99.98% | 1 0.00% 99.98% | 2 0.01% 99.98% | 6 0.02% 100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38466
-system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1
-system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9
-system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340316
-system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1
-system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1
-system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340316
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340316
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340316
-system.ruby.Directory_Controller.Fetch 181113 0.00% 0.00%
-system.ruby.Directory_Controller.Data 102911 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 181583 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 147234 0.00% 0.00%
-system.ruby.Directory_Controller.DMA_READ 816 0.00% 0.00%
-system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 13434 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 181113 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE 44323 0.00% 0.00%
-system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack 44323 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 100152 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_READ 346 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE 2413 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 13434 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 181113 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 100152 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRD.Data 346 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack 346 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWR.Data 2413 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2413 0.00% 0.00%
-system.ruby.DMA_Controller.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 816
-system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.WriteRequest::total 46736
-system.ruby.DMA_Controller.Data | 816 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 816
-system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Ack::total 46736
-system.ruby.DMA_Controller.READY.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 816
-system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.WriteRequest::total 46736
-system.ruby.DMA_Controller.BUSY_RD.Data | 816 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 816
-system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736
-system.ruby.L1Cache_Controller.Load | 10174731 65.92% 65.92% | 5260188 34.08% 100.00%
-system.ruby.L1Cache_Controller.Load::total 15434919
-system.ruby.L1Cache_Controller.Ifetch | 115118489 67.03% 67.03% | 56626661 32.97% 100.00%
-system.ruby.L1Cache_Controller.Ifetch::total 171745150
-system.ruby.L1Cache_Controller.Store | 7445539 68.97% 68.97% | 3350451 31.03% 100.00%
-system.ruby.L1Cache_Controller.Store::total 10795990
-system.ruby.L1Cache_Controller.Inv | 18648 52.30% 52.30% | 17011 47.70% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 35659
-system.ruby.L1Cache_Controller.L1_Replacement | 1725795 65.05% 65.05% | 927205 34.95% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 2653000
-system.ruby.L1Cache_Controller.Fwd_GETX | 12362 50.94% 50.94% | 11904 49.06% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 24266
-system.ruby.L1Cache_Controller.Fwd_GETS | 14780 53.13% 53.13% | 13039 46.87% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 27819
-system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.Data | 521 31.46% 31.46% | 1135 68.54% 100.00%
-system.ruby.L1Cache_Controller.Data::total 1656
-system.ruby.L1Cache_Controller.Data_Exclusive | 836671 62.58% 62.58% | 500206 37.42% 100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total 1336877
-system.ruby.L1Cache_Controller.DataS_fromL1 | 13039 46.86% 46.86% | 14784 53.14% 100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total 27823
-system.ruby.L1Cache_Controller.Data_all_Acks | 892759 67.52% 67.52% | 429359 32.48% 100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total 1322118
-system.ruby.L1Cache_Controller.Ack | 12812 52.14% 52.14% | 11761 47.86% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 24573
-system.ruby.L1Cache_Controller.Ack_all | 13333 50.83% 50.83% | 12896 49.17% 100.00%
-system.ruby.L1Cache_Controller.Ack_all::total 26229
-system.ruby.L1Cache_Controller.WB_Ack | 1127309 64.72% 64.72% | 614455 35.28% 100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total 1741764
-system.ruby.L1Cache_Controller.NP.Load | 877314 62.10% 62.10% | 535446 37.90% 100.00%
-system.ruby.L1Cache_Controller.NP.Load::total 1412760
-system.ruby.L1Cache_Controller.NP.Ifetch | 549594 67.01% 67.01% | 270630 32.99% 100.00%
-system.ruby.L1Cache_Controller.NP.Ifetch::total 820224
-system.ruby.L1Cache_Controller.NP.Store | 299910 71.06% 71.06% | 122153 28.94% 100.00%
-system.ruby.L1Cache_Controller.NP.Store::total 422063
-system.ruby.L1Cache_Controller.NP.Inv | 5790 62.89% 62.89% | 3417 37.11% 100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total 9207
-system.ruby.L1Cache_Controller.I.Load | 10201 47.75% 47.75% | 11161 52.25% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 21362
-system.ruby.L1Cache_Controller.I.Ifetch | 164 53.77% 53.77% | 141 46.23% 100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total 305
-system.ruby.L1Cache_Controller.I.Store | 5805 49.38% 49.38% | 5950 50.62% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 11755
-system.ruby.L1Cache_Controller.I.L1_Replacement | 9048 52.68% 52.68% | 8128 47.32% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 17176
-system.ruby.L1Cache_Controller.S.Load | 854922 63.25% 63.25% | 496689 36.75% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 1351611
-system.ruby.L1Cache_Controller.S.Ifetch | 114568727 67.03% 67.03% | 56355888 32.97% 100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total 170924615
-system.ruby.L1Cache_Controller.S.Store | 12814 52.14% 52.14% | 11764 47.86% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 24578
-system.ruby.L1Cache_Controller.S.Inv | 12592 48.75% 48.75% | 13236 51.25% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 25828
-system.ruby.L1Cache_Controller.S.L1_Replacement | 589438 65.93% 65.93% | 304622 34.07% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 894060
-system.ruby.L1Cache_Controller.E.Load | 2373511 63.51% 63.51% | 1363700 36.49% 100.00%
-system.ruby.L1Cache_Controller.E.Load::total 3737211
-system.ruby.L1Cache_Controller.E.Store | 119848 72.96% 72.96% | 44409 27.04% 100.00%
-system.ruby.L1Cache_Controller.E.Store::total 164257
-system.ruby.L1Cache_Controller.E.Inv | 68 57.63% 57.63% | 50 42.37% 100.00%
-system.ruby.L1Cache_Controller.E.Inv::total 118
-system.ruby.L1Cache_Controller.E.L1_Replacement | 715361 61.16% 61.16% | 454250 38.84% 100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total 1169611
-system.ruby.L1Cache_Controller.E.Fwd_GETX | 230 60.05% 60.05% | 153 39.95% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total 383
-system.ruby.L1Cache_Controller.E.Fwd_GETS | 951 42.97% 42.97% | 1262 57.03% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2213
-system.ruby.L1Cache_Controller.M.Load | 6058783 67.98% 67.98% | 2853192 32.02% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 8911975
-system.ruby.L1Cache_Controller.M.Store | 7007162 68.88% 68.88% | 3166175 31.12% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 10173337
-system.ruby.L1Cache_Controller.M.Inv | 195 39.00% 39.00% | 305 61.00% 100.00%
-system.ruby.L1Cache_Controller.M.Inv::total 500
-system.ruby.L1Cache_Controller.M.L1_Replacement | 411948 72.00% 72.00% | 160205 28.00% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 572153
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 12132 50.80% 50.80% | 11750 49.20% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23882
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 13829 54.01% 54.01% | 11777 45.99% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 25606
-system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.IS.Inv | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS.Inv::total 1
-system.ruby.L1Cache_Controller.IS.Data_Exclusive | 836671 62.58% 62.58% | 500206 37.42% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336877
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 13038 46.86% 46.86% | 14784 53.14% 100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27822
-system.ruby.L1Cache_Controller.IS.Data_all_Acks | 587563 66.02% 66.02% | 302388 33.98% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889951
-system.ruby.L1Cache_Controller.IM.Data | 521 31.46% 31.46% | 1135 68.54% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 1656
-system.ruby.L1Cache_Controller.IM.Data_all_Acks | 305196 70.62% 70.62% | 126971 29.38% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 432167
-system.ruby.L1Cache_Controller.SM.Inv | 2 40.00% 40.00% | 3 60.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Inv::total 5
-system.ruby.L1Cache_Controller.SM.Ack | 12812 52.14% 52.14% | 11761 47.86% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 24573
-system.ruby.L1Cache_Controller.SM.Ack_all | 13333 50.83% 50.83% | 12896 49.17% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total 26229
-system.ruby.L1Cache_Controller.IS_I.DataS_fromL1 | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS_I.DataS_fromL1::total 1
-system.ruby.L1Cache_Controller.M_I.Ifetch | 4 66.67% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch::total 6
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1
-system.ruby.L1Cache_Controller.M_I.WB_Ack | 1127309 64.72% 64.72% | 614454 35.28% 100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741763
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1
-system.ruby.L2Cache_Controller.L1_GET_INSTR 820529 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 1434524 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 433826 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE 24578 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 1741764 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 100099 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 13487 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 181113 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 116345 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 26110 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 2213 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack 1845 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 7085 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 27823 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 1795273 0.00% 0.00%
-system.ruby.L2Cache_Controller.MEM_Inv 5518 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15422 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 32337 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 133354 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 805077 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 69426 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 1949 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24573 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 290 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6672 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1304540 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 274254 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 99553 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6682 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 2525 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 27819 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 24266 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1741763 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 256 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 133 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 116345 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 2525 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 447 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 53 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 80 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1551 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 6672 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 294 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 32337 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 15422 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 133354 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 237 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26522 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 165 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768751 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25603 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2212 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 27815 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
- BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
- BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
- BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
-end_pfn_map = 1048576\r
-kernel direct mapping tables up to 100000000 @ 8000-d000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
- DMA 0 -> 4096\r
- DMA32 4096 -> 1048576\r
- Normal 1048576 -> 1048576\r
-early_node_map[2] active PFN ranges\r
- 0: 0 -> 159\r
- 0: 256 -> 32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-Processor #1\r
-I/O APIC #2 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 2\r
-Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
-PERCPU: Allocating 34160 bytes of per cpu data\r
-Built 1 zonelists. Total pages: 30613\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-Marking TSC unstable due to TSCs unsynchronized\r
-time.c: Detected 2000.000 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 121996k/131072k available (3699k kernel code, 8524k reserved, 1767k data, 248k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-using mwait in idle threads.\r
-Freeing SMP alternatives: 34k freed\r
-Using local APIC timer interrupts.\r
-result 7812506\r
-Detected 7.812 MHz APIC timer.\r
-Booting processor 1/2 APIC 0x1\r
-Initializing CPU#1\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-Fake M5 x86_64 CPU stepping 01\r
-Brought up 2 CPUs\r
-migration_cost=11\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
-PCI-GART: No AMD northbridge found.\r
-NET: Registered protocol family 2\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 98304 bytes)\r
-TCP bind hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-NET: Registered protocol family 17\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 248k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-root.system.readfile = os.path.join(tests_root, 'halt.sh')
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=200000000
-time_sync_spin_threshold=200000
-
-[system]
-type=SparcSystem
-children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-hypervisor_addr=1099243257856
-hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
-hypervisor_desc=system.hypervisor_desc
-hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0
-memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-nvram=system.nvram
-nvram_addr=133429198848
-nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
-openboot_addr=1099243716608
-openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-partition_desc=system.partition_desc
-partition_desc_addr=133445976064
-partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr=1099243192320
-reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
-rom=system.rom
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=100
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=2
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=2
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=MmDisk
-children=image
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-image=system.disk0.image
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=134217728000
-pio_latency=200
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=200000
-
-[system.hypervisor_desc]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=133446500352:133446508543:0:0:0:0
-port=system.membus.master[5]
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
-slave=system.bridge.master
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=0
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.nvram]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=133429198848:133429207039:0:0:0:0
-port=system.membus.master[4]
-
-[system.partition_desc]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=133445976064:133445984255:0:0:0:0
-port=system.membus.master[6]
-
-[system.physmem0]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=1048576:68157439:0:0:0:0
-port=system.membus.master[7]
-
-[system.physmem1]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-port=system.membus.master[8]
-
-[system.rom]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=60
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-power_model=Null
-range=1099243192320:1099251580927:0:0:0:0
-port=system.membus.master[3]
-
-[system.t1000]
-type=T1000
-children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.t1000.fake_clk]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=644245094400
-pio_latency=200
-pio_size=4294967296
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[0]
-
-[system.t1000.fake_jbi]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=549755813888
-pio_latency=200
-pio_size=4294967296
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.t1000.fake_l2_1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=725849473024
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=1
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[2]
-
-[system.t1000.fake_l2_2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=725849473088
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=1
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[3]
-
-[system.t1000.fake_l2_3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=725849473152
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=1
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[4]
-
-[system.t1000.fake_l2_4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=725849473216
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=1
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[5]
-
-[system.t1000.fake_l2esr_1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=734439407616
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=0
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[6]
-
-[system.t1000.fake_l2esr_2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=734439407680
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=0
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[7]
-
-[system.t1000.fake_l2esr_3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=734439407744
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=0
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[8]
-
-[system.t1000.fake_l2esr_4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=734439407808
-pio_latency=200
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=0
-ret_data8=255
-system=system
-update_data=true
-warn_access=
-pio=system.iobus.master[9]
-
-[system.t1000.fake_membnks]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=648540061696
-pio_latency=200
-pio_size=16384
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=0
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[1]
-
-[system.t1000.fake_ssi]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=1095216660480
-pio_latency=200
-pio_size=268435456
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.t1000.hterm]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.t1000.htod]
-type=DumbTOD
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=1099255906296
-pio_latency=200
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.membus.master[1]
-
-[system.t1000.hvuart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=1099255955456
-pio_latency=200
-platform=system.t1000
-power_model=Null
-system=system
-terminal=system.t1000.hterm
-pio=system.iobus.master[13]
-
-[system.t1000.iob]
-type=Iob
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_latency=2
-platform=system.t1000
-power_model=Null
-system=system
-pio=system.membus.master[0]
-
-[system.t1000.pterm]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.t1000.puart0]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=2000000000
-p_state_clk_gate_min=2
-pio_addr=133412421632
-pio_latency=200
-platform=system.t1000
-power_model=Null
-system=system
-terminal=system.t1000.pterm
-pio=system.iobus.master[12]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "rom": {
- "range": "1099243192320:1099251580927:0:0:0:0",
- "latency": 60,
- "name": "rom",
- "p_state_clk_gate_min": 2,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "kvm_map": true,
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "latency_var": 0,
- "bandwidth": "0.000000",
- "conf_table_reported": true,
- "cxx_class": "SimpleMemory",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.rom",
- "null": false,
- "type": "SimpleMemory",
- "port": {
- "peer": "system.membus.master[3]",
- "role": "SLAVE"
- },
- "in_addr_map": true
- },
- "bridge": {
- "ranges": [
- "133412421632:133412421639:0:0:0:0",
- "134217728000:554050781183:0:0:0:0",
- "644245094400:652835028991:0:0:0:0",
- "725849473024:1095485095935:0:0:0:0",
- "1099255955456:1099255955463:0:0:0:0"
- ],
- "slave": {
- "peer": "system.membus.master[2]",
- "role": "SLAVE"
- },
- "name": "bridge",
- "p_state_clk_gate_min": 2,
- "p_state_clk_gate_bins": 20,
- "cxx_class": "Bridge",
- "req_size": 16,
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "delay": 100,
- "eventq_index": 0,
- "master": {
- "peer": "system.iobus.slave[0]",
- "role": "MASTER"
- },
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.bridge",
- "resp_size": 16,
- "type": "Bridge"
- },
- "iobus": {
- "forward_latency": 1,
- "slave": {
- "peer": [
- "system.bridge.master"
- ],
- "role": "SLAVE"
- },
- "name": "iobus",
- "p_state_clk_gate_min": 2,
- "p_state_clk_gate_bins": 20,
- "cxx_class": "NoncoherentXBar",
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "width": 16,
- "eventq_index": 0,
- "master": {
- "peer": [
- "system.t1000.fake_clk.pio",
- "system.t1000.fake_membnks.pio",
- "system.t1000.fake_l2_1.pio",
- "system.t1000.fake_l2_2.pio",
- "system.t1000.fake_l2_3.pio",
- "system.t1000.fake_l2_4.pio",
- "system.t1000.fake_l2esr_1.pio",
- "system.t1000.fake_l2esr_2.pio",
- "system.t1000.fake_l2esr_3.pio",
- "system.t1000.fake_l2esr_4.pio",
- "system.t1000.fake_ssi.pio",
- "system.t1000.fake_jbi.pio",
- "system.t1000.puart0.pio",
- "system.t1000.hvuart.pio",
- "system.disk0.pio"
- ],
- "role": "MASTER"
- },
- "response_latency": 2,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.iobus",
- "type": "NoncoherentXBar",
- "use_default_range": false,
- "frontend_latency": 2
- },
- "t1000": {
- "htod": {
- "name": "htod",
- "p_state_clk_gate_min": 2,
- "pio": {
- "peer": "system.membus.master[1]",
- "role": "SLAVE"
- },
- "p_state_clk_gate_bins": 20,
- "cxx_class": "DumbTOD",
- "pio_latency": 200,
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "system": "system",
- "eventq_index": 0,
- "time": "Thu Jan 1 00:00:00 2009",
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.t1000.htod",
- "pio_addr": 1099255906296,
- "type": "DumbTOD"
- },
- "puart0": {
- "name": "puart0",
- "p_state_clk_gate_min": 2,
- "pio": {
- "peer": "system.iobus.master[12]",
- "role": "SLAVE"
- },
- "p_state_clk_gate_bins": 20,
- "cxx_class": "Uart8250",
- "pio_latency": 200,
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "system": "system",
- "terminal": "system.t1000.pterm",
- "platform": "system.t1000",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.t1000.puart0",
- "pio_addr": 133412421632,
- "type": "Uart8250"
- },
- "fake_membnks": {
- "pio": {
- "peer": "system.iobus.master[1]",
- "role": "SLAVE"
- },
- "ret_data64": 0,
- "fake_mem": false,
- "clk_domain": "system.clk_domain",
- "cxx_class": "IsaFake",
- "pio_addr": 648540061696,
- "update_data": false,
- "warn_access": "",
- "pio_latency": 200,
- "system": "system",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "type": "IsaFake",
- "p_state_clk_gate_min": 2,
- "power_model": null,
- "ret_data32": 4294967295,
- "path": "system.t1000.fake_membnks",
- "ret_data16": 65535,
- "ret_data8": 255,
- "name": "fake_membnks",
- "ret_bad_addr": false,
- "pio_size": 16384,
- "p_state_clk_gate_bins": 20
- },
- "cxx_class": "T1000",
- "fake_jbi": {
- "pio": {
- "peer": "system.iobus.master[11]",
- "role": "SLAVE"
- },
- "ret_data64": 18446744073709551615,
- "fake_mem": false,
- "clk_domain": "system.clk_domain",
- "cxx_class": "IsaFake",
- "pio_addr": 549755813888,
- "update_data": false,
- "warn_access": "",
- "pio_latency": 200,
- "system": "system",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "type": "IsaFake",
- "p_state_clk_gate_min": 2,
- "power_model": null,
- "ret_data32": 4294967295,
- "path": "system.t1000.fake_jbi",
- "ret_data16": 65535,
- "ret_data8": 255,
- "name": "fake_jbi",
- "ret_bad_addr": false,
- "pio_size": 4294967296,
- "p_state_clk_gate_bins": 20
- },
- "intrctrl": "system.intrctrl",
- "fake_l2esr_2": {
- "pio": {
- "peer": "system.iobus.master[7]",
- "role": "SLAVE"
- },
- "ret_data64": 0,
- "fake_mem": false,
- "clk_domain": "system.clk_domain",
- "cxx_class": "IsaFake",
- "pio_addr": 734439407680,
- "update_data": true,
- "warn_access": "",
- "pio_latency": 200,
- "system": "system",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "type": "IsaFake",
- "p_state_clk_gate_min": 2,
- "power_model": null,
- "ret_data32": 4294967295,
- "path": "system.t1000.fake_l2esr_2",
- "ret_data16": 65535,
- "ret_data8": 255,
- "name": "fake_l2esr_2",
- "ret_bad_addr": false,
- "pio_size": 8,
- "p_state_clk_gate_bins": 20
- },
- "system": "system",
- "eventq_index": 0,
- "hterm": {
- "name": "hterm",
- "output": true,
- "number": 0,
- "intr_control": "system.intrctrl",
- "eventq_index": 0,
- "cxx_class": "Terminal",
- "path": "system.t1000.hterm",
- "type": "Terminal",
- "port": 3456
- },
- "type": "T1000",
- "fake_l2_4": {
- "pio": {
- "peer": "system.iobus.master[5]",
- "role": "SLAVE"
- },
- "ret_data64": 1,
- "fake_mem": false,
- "clk_domain": "system.clk_domain",
- "cxx_class": "IsaFake",
- "pio_addr": 725849473216,
- "update_data": true,
- "warn_access": "",
- "pio_latency": 200,
- "system": "system",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "type": "IsaFake",
- "p_state_clk_gate_min": 2,
- "power_model": null,
- "ret_data32": 4294967295,
- "path": "system.t1000.fake_l2_4",
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- }
- },
- "intrctrl": {
- "name": "intrctrl",
- "sys": "system",
- "eventq_index": 0,
- "cxx_class": "IntrControl",
- "path": "system.intrctrl",
- "type": "IntrControl"
- },
- "disk0": {
- "name": "disk0",
- "p_state_clk_gate_min": 2,
- "pio": {
- "peer": "system.iobus.master[14]",
- "role": "SLAVE"
- },
- "p_state_clk_gate_bins": 20,
- "image": {
- "read_only": false,
- "name": "image",
- "cxx_class": "CowDiskImage",
- "eventq_index": 0,
- "child": {
- "read_only": true,
- "name": "child",
- "eventq_index": 0,
- "cxx_class": "RawDiskImage",
- "path": "system.disk0.image.child",
- "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
- "type": "RawDiskImage"
- },
- "path": "system.disk0.image",
- "image_file": "",
- "type": "CowDiskImage",
- "table_size": 65536
- },
- "cxx_class": "MmDisk",
- "pio_latency": 200,
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "system": "system",
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 2000000000,
- "path": "system.disk0",
- "pio_addr": 134217728000,
- "type": "MmDisk"
- },
- "multi_thread": false,
- "reset_addr": 1099243192320,
- "p_state_clk_gate_bins": 20,
- "hypervisor_desc_addr": 133446500352,
- "num_work_ids": 16,
- "work_item_id": -1,
- "exit_on_work_items": false
- },
- "time_sync_period": 200000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 200000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": true
-}
\ No newline at end of file
+++ /dev/null
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: rounding error > tolerance
- 0.145519 rounded to 0
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Don't know what interrupt to clear for console.
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 4 2017 02:52:44
-gem5 started Apr 4 2017 02:52:54
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 16631
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
-
-Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing
- 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
-
- 0: system.t1000.htod: Real-time clock set to 1230768000
-info: Entering event queue @ 0. Starting simulation...
-info: Ignoring write to SPARC ERROR regsiter
-info: Ignoring write to SPARC ERROR regsiter
-Exiting @ tick 4467555024 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.233778 # Number of seconds simulated
-sim_ticks 4467555024 # Number of ticks simulated
-final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 2912008 # Simulator instruction rate (inst/s)
-host_op_rate 2913153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5838373 # Simulator tick rate (ticks/s)
-host_mem_usage 551728 # Number of bytes of host memory used
-host_seconds 765.21 # Real time elapsed on the host
-sim_insts 2228284650 # Number of instructions simulated
-sim_ops 2229160714 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 2 # Clock period in ticks
-system.hypervisor_desc.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
-system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
-system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
-system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
-system.nvram.bytes_read::total 284 # Number of bytes read from this memory
-system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
-system.nvram.bytes_written::total 92 # Number of bytes written to this memory
-system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
-system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
-system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
-system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
-system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
-system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory
-system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
-system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
-system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
-system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory
-system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
-system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
-system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory
-system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
-system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory
-system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory
-system.physmem0.num_other::total 14 # Number of other requests responded to by this memory
-system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
-system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
-system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
-system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
-system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
-system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
-system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
-system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
-system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
-system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
-system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
-system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
-system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
-system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
-system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
-system.rom.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
-system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
-system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 2 # Clock period in ticks
-system.cpu.pwrStateResidencyTicks::ON 4467555024 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 2233777513 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.committedInsts 2228284650 # Number of instructions committed
-system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
-system.cpu.num_func_calls 44037246 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1839325658 # number of integer instructions
-system.cpu.num_fp_insts 14608322 # number of float instructions
-system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
-system.cpu.num_mem_refs 547951940 # number of memory refs
-system.cpu.num_load_insts 349807670 # Number of load instructions
-system.cpu.num_store_insts 198144270 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 441057355 # Number of branches fetched
-system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
-system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
-system.cpu.op_class::MemRead 352214742 15.77% 90.86% # Class of executed instruction
-system.cpu.op_class::MemWrite 198071026 8.87% 99.72% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 4059787 0.18% 99.90% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 2128756 0.10% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 2233583679 # Class of executed instruction
-system.disk0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.iobus.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution
-system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7569 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7569 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_1.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_3.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_4.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_1.pio 16 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio 16 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution
-system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution
-system.membus.trans_dist::WriteReq 189322556 # Transaction distribution
-system.membus.trans_dist::WriteResp 189322556 # Transaction distribution
-system.membus.trans_dist::SwapReq 5403081 # Transaction distribution
-system.membus.trans_dist::SwapResp 5403081 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2767993261 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 2767993261 # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_clk.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_jbi.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2_1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2_2.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2_3.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2_4.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2esr_1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2esr_2.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2esr_3.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_l2esr_4.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_membnks.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.fake_ssi.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.htod.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.hvuart.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.iob.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-system.t1000.puart0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics ----------
+++ /dev/null
-\11cpu \r
-\r
-Sun Fire T2000, No Keyboard\r
-Copyright 2006 Sun Microsystems, Inc. All rights reserved.\r
-OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.\r
-[saidi obp #30]\r
-Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.\r
-\r
-\r
-\r
-Boot device: /virtual-devices/disk@0 File and args: -vV\r
-Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. \r
-FCode UFS Reader 1.12 00/07/17 15:48:16. \r
-Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot\r
-Loading: /platform/sun4v/ufsboot\r
-device path '/virtual-devices@100/disk@0:a'\r
-The boot filesystem is logging.\r
-The ufs log is empty and will not be used.\r
-standalone = `kernel/sparcv9/unix', args = `-v'\r
-|\bElf64 client\r
-Size: /\b-\b\\b|\b/\b-\b\\b|\b0x76e40+/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b0x1c872+|\b/\b-\b\\b0x3123a Bytes\r
-modpath: /platform/sun4v/kernel /kernel /usr/kernel\r
-|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\bmodule /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000\r
-module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0\r
-module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0\r
-module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0\r
-module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300\r
-\\b\rSunOS Release 5.10 Version Generic_118822-23 64-bit\r
-Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.\r
-Use is subject to license terms.\r
-|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\bEthernet address = 0:80:3:de:ad:3\r
-\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\b-\b\\b|\b/\bmem = 262144K (0x10000000)\r
-avail mem = 237879296\r
-root nexus = Sun Fire T2000\r
-pseudo0 at root\r
-pseudo0 is /pseudo\r
-scsi_vhci0 at root\r
-scsi_vhci0 is /scsi_vhci\r
-virtual-device: hsimd0\r
-hsimd0 is /virtual-devices@100/disk@0\r
-root on /virtual-devices@100/disk@0:a fstype ufs\r
-pseudo-device: dld0\r
-dld0 is /pseudo/dld@0\r
-cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)\r
-iscsi0 at root\r
-iscsi0 is /iscsi\r
-Hostname: unknown\r
-Loading M5 readfile script...\r
+++ /dev/null
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-root.system.readfile = os.path.join(tests_root, 'halt.sh')
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
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-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
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-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits3]
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-opLat=9
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-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
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-
-[system.cpu.executeFuncUnits.funcUnits4]
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-cantForwardFromFUIndices=
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
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-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
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-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
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-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
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-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
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-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
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-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
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-extraAssumedLat=2
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-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
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-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
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-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
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-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
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-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
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-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
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-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
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-id_aa64mmfr0_el1=15728642
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-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
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-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
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-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
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-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
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-
-[system.cpu.itb]
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-[system.cpu.itb.walker]
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-is_stage2=false
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
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-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
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-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
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-response_latency=20
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-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
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-p_state_clk_gate_min=1000
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-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
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-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
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-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:02
-gem5 executing on e108600-lin, pid 17345
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 62552970500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.062555 # Number of seconds simulated
-sim_ticks 62555455500 # Number of ticks simulated
-final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 428742 # Simulator instruction rate (inst/s)
-host_op_rate 430877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 296018745 # Simulator tick rate (ticks/s)
-host_mem_usage 404460 # Number of bytes of host memory used
-host_seconds 211.32 # Real time elapsed on the host
-sim_insts 90602850 # Number of instructions simulated
-sim_ops 91054081 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
-system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15575 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 993 # Per bank write bursts
-system.physmem.perBankRdBursts::1 891 # Per bank write bursts
-system.physmem.perBankRdBursts::2 949 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 962 # Per bank write bursts
-system.physmem.perBankRdBursts::10 938 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 904 # Per bank write bursts
-system.physmem.perBankRdBursts::13 867 # Per bank write bursts
-system.physmem.perBankRdBursts::14 876 # Per bank write bursts
-system.physmem.perBankRdBursts::15 906 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 62555354500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 15575 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
-system.physmem.totQLat 211097500 # Total ticks spent queuing
-system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.12 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14028 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4016395.15 # Average gap between requests
-system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ)
-system.physmem_0.averagePower 252.613756 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states
-system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ)
-system.physmem_1.averagePower 254.503090 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 20806620 # Number of BP lookups
-system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 125110911 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 90602850 # Number of instructions committed
-system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.380872 # CPI: cycles per instruction
-system.cpu.ipc 0.724180 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
-system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 91054081 # Class of committed instruction
-system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 946104 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits
-system.cpu.dcache.overall_hits::total 26266839 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses
-system.cpu.dcache.overall_misses::total 980819 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
-system.cpu.dcache.writebacks::total 943285 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1031 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 15575 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 15575 # Request fanout histogram
-system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
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-eventq_index=0
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-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
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-degree=8
-eventq_index=0
-latency=1
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-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
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-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu.l2cache.tags]
-type=RandomRepl
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
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-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
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-
-[system.cpu.tracer]
-type=ExeTracer
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-
-[system.cpu.workload]
-type=Process
-cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
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-clk_domain=system.clk_domain
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-ranks_per_channel=2
-read_buffer_size=32
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-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
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-tXAW=30000
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-tXPDLL=0
-tXS=270000
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-write_buffer_size=64
-write_high_thresh_perc=85
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-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
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-***
-82
-()
-23
-***
-87
-***
-117
-()
-22
-***
-76
-***
-119
-()
-21
-***
-84
-()
-20
-***
-78
-()
-19
-***
-73
-()
-18
-***
-81
-()
-17
-***
-65
-()
-16
-***
-63
-***
-101
-()
-15
-***
-71
-()
-14
-***
-75
-()
-13
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-322
-()
-12
-***
-77
-()
-11
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-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
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-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
-***
-185
-***
-200
-()
-2
-***
-205
-()
-1
-***
-39
-***
-95
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 18:10:17
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 58521086000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.058521
-sim_ticks 58521086000
-final_tick 58521086000
-sim_freq 1000000000000
-host_inst_rate 103970
-host_op_rate 104488
-host_tick_rate 67164623
-host_mem_usage 503044
-host_seconds 871.31
-sim_insts 90589799
-sim_ops 91041030
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.physmem.bytes_read::cpu.inst 44736
-system.physmem.bytes_read::cpu.data 220224
-system.physmem.bytes_read::cpu.l2cache.prefetcher 921920
-system.physmem.bytes_read::total 1186880
-system.physmem.bytes_inst_read::cpu.inst 44736
-system.physmem.bytes_inst_read::total 44736
-system.physmem.bytes_written::writebacks 4736
-system.physmem.bytes_written::total 4736
-system.physmem.num_reads::cpu.inst 699
-system.physmem.num_reads::cpu.data 3441
-system.physmem.num_reads::cpu.l2cache.prefetcher 14405
-system.physmem.num_reads::total 18545
-system.physmem.num_writes::writebacks 74
-system.physmem.num_writes::total 74
-system.physmem.bw_read::cpu.inst 764442
-system.physmem.bw_read::cpu.data 3763156
-system.physmem.bw_read::cpu.l2cache.prefetcher 15753638
-system.physmem.bw_read::total 20281237
-system.physmem.bw_inst_read::cpu.inst 764442
-system.physmem.bw_inst_read::total 764442
-system.physmem.bw_write::writebacks 80928
-system.physmem.bw_write::total 80928
-system.physmem.bw_total::writebacks 80928
-system.physmem.bw_total::cpu.inst 764442
-system.physmem.bw_total::cpu.data 3763156
-system.physmem.bw_total::cpu.l2cache.prefetcher 15753638
-system.physmem.bw_total::total 20362165
-system.physmem.readReqs 18546
-system.physmem.writeReqs 74
-system.physmem.readBursts 18546
-system.physmem.writeBursts 74
-system.physmem.bytesReadDRAM 1183360
-system.physmem.bytesReadWrQ 3584
-system.physmem.bytesWritten 3328
-system.physmem.bytesReadSys 1186944
-system.physmem.bytesWrittenSys 4736
-system.physmem.servicedByWrQ 56
-system.physmem.mergedWrBursts 4
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 3297
-system.physmem.perBankRdBursts::1 920
-system.physmem.perBankRdBursts::2 949
-system.physmem.perBankRdBursts::3 1031
-system.physmem.perBankRdBursts::4 1067
-system.physmem.perBankRdBursts::5 1119
-system.physmem.perBankRdBursts::6 1093
-system.physmem.perBankRdBursts::7 1097
-system.physmem.perBankRdBursts::8 1024
-system.physmem.perBankRdBursts::9 961
-system.physmem.perBankRdBursts::10 934
-system.physmem.perBankRdBursts::11 899
-system.physmem.perBankRdBursts::12 902
-system.physmem.perBankRdBursts::13 895
-system.physmem.perBankRdBursts::14 1399
-system.physmem.perBankRdBursts::15 903
-system.physmem.perBankWrBursts::0 1
-system.physmem.perBankWrBursts::1 0
-system.physmem.perBankWrBursts::2 2
-system.physmem.perBankWrBursts::3 0
-system.physmem.perBankWrBursts::4 1
-system.physmem.perBankWrBursts::5 14
-system.physmem.perBankWrBursts::6 9
-system.physmem.perBankWrBursts::7 3
-system.physmem.perBankWrBursts::8 1
-system.physmem.perBankWrBursts::9 0
-system.physmem.perBankWrBursts::10 2
-system.physmem.perBankWrBursts::11 0
-system.physmem.perBankWrBursts::12 1
-system.physmem.perBankWrBursts::13 12
-system.physmem.perBankWrBursts::14 5
-system.physmem.perBankWrBursts::15 1
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 0
-system.physmem.totGap 58521077500
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 0
-system.physmem.readPktSize::3 0
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 18546
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 0
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 74
-system.physmem.rdQLenPdf::0 12593
-system.physmem.rdQLenPdf::1 3390
-system.physmem.rdQLenPdf::2 500
-system.physmem.rdQLenPdf::3 409
-system.physmem.rdQLenPdf::4 319
-system.physmem.rdQLenPdf::5 301
-system.physmem.rdQLenPdf::6 297
-system.physmem.rdQLenPdf::7 299
-system.physmem.rdQLenPdf::8 279
-system.physmem.rdQLenPdf::9 103
-system.physmem.rdQLenPdf::10 0
-system.physmem.rdQLenPdf::11 0
-system.physmem.rdQLenPdf::12 0
-system.physmem.rdQLenPdf::13 0
-system.physmem.rdQLenPdf::14 0
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 3
-system.physmem.wrQLenPdf::16 3
-system.physmem.wrQLenPdf::17 4
-system.physmem.wrQLenPdf::18 3
-system.physmem.wrQLenPdf::19 3
-system.physmem.wrQLenPdf::20 3
-system.physmem.wrQLenPdf::21 3
-system.physmem.wrQLenPdf::22 3
-system.physmem.wrQLenPdf::23 3
-system.physmem.wrQLenPdf::24 3
-system.physmem.wrQLenPdf::25 3
-system.physmem.wrQLenPdf::26 3
-system.physmem.wrQLenPdf::27 3
-system.physmem.wrQLenPdf::28 3
-system.physmem.wrQLenPdf::29 3
-system.physmem.wrQLenPdf::30 3
-system.physmem.wrQLenPdf::31 3
-system.physmem.wrQLenPdf::32 3
-system.physmem.wrQLenPdf::33 0
-system.physmem.wrQLenPdf::34 0
-system.physmem.wrQLenPdf::35 0
-system.physmem.wrQLenPdf::36 0
-system.physmem.wrQLenPdf::37 0
-system.physmem.wrQLenPdf::38 0
-system.physmem.wrQLenPdf::39 0
-system.physmem.wrQLenPdf::40 0
-system.physmem.wrQLenPdf::41 0
-system.physmem.wrQLenPdf::42 0
-system.physmem.wrQLenPdf::43 0
-system.physmem.wrQLenPdf::44 0
-system.physmem.wrQLenPdf::45 0
-system.physmem.wrQLenPdf::46 0
-system.physmem.wrQLenPdf::47 0
-system.physmem.wrQLenPdf::48 0
-system.physmem.wrQLenPdf::49 0
-system.physmem.wrQLenPdf::50 0
-system.physmem.wrQLenPdf::51 0
-system.physmem.wrQLenPdf::52 0
-system.physmem.wrQLenPdf::53 0
-system.physmem.wrQLenPdf::54 0
-system.physmem.wrQLenPdf::55 0
-system.physmem.wrQLenPdf::56 0
-system.physmem.wrQLenPdf::57 0
-system.physmem.wrQLenPdf::58 0
-system.physmem.wrQLenPdf::59 0
-system.physmem.wrQLenPdf::60 0
-system.physmem.wrQLenPdf::61 0
-system.physmem.wrQLenPdf::62 0
-system.physmem.wrQLenPdf::63 0
-system.physmem.bytesPerActivate::samples 3004
-system.physmem.bytesPerActivate::mean 394.652463
-system.physmem.bytesPerActivate::gmean 214.589229
-system.physmem.bytesPerActivate::stdev 405.543781
-system.physmem.bytesPerActivate::0-127 893 29.73% 29.73%
-system.physmem.bytesPerActivate::128-255 965 32.12% 61.85%
-system.physmem.bytesPerActivate::256-383 89 2.96% 64.81%
-system.physmem.bytesPerActivate::384-511 63 2.10% 66.91%
-system.physmem.bytesPerActivate::512-639 67 2.23% 69.14%
-system.physmem.bytesPerActivate::640-767 66 2.20% 71.34%
-system.physmem.bytesPerActivate::768-895 53 1.76% 73.10%
-system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67%
-system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00%
-system.physmem.bytesPerActivate::total 3004
-system.physmem.rdPerTurnAround::samples 3
-system.physmem.rdPerTurnAround::mean 6161.333333
-system.physmem.rdPerTurnAround::gmean 2123.401593
-system.physmem.rdPerTurnAround::stdev 8586.829993
-system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33%
-system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67%
-system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00%
-system.physmem.rdPerTurnAround::total 3
-system.physmem.wrPerTurnAround::samples 3
-system.physmem.wrPerTurnAround::mean 17.333333
-system.physmem.wrPerTurnAround::gmean 17.306995
-system.physmem.wrPerTurnAround::stdev 1.154701
-system.physmem.wrPerTurnAround::16 1 33.33% 33.33%
-system.physmem.wrPerTurnAround::18 2 66.67% 100.00%
-system.physmem.wrPerTurnAround::total 3
-system.physmem.totQLat 837911216
-system.physmem.totMemAccLat 1184598716
-system.physmem.totBusLat 92450000
-system.physmem.avgQLat 45316.99
-system.physmem.avgBusLat 5000.00
-system.physmem.avgMemAccLat 64066.99
-system.physmem.avgRdBW 20.22
-system.physmem.avgWrBW 0.06
-system.physmem.avgRdBWSys 20.28
-system.physmem.avgWrBWSys 0.08
-system.physmem.peakBW 12800.00
-system.physmem.busUtil 0.16
-system.physmem.busUtilRead 0.16
-system.physmem.busUtilWrite 0.00
-system.physmem.avgRdQLen 1.04
-system.physmem.avgWrQLen 13.38
-system.physmem.readRowHits 15512
-system.physmem.writeRowHits 18
-system.physmem.readRowHitRate 83.89
-system.physmem.writeRowHitRate 25.71
-system.physmem.avgGap 3142915.01
-system.physmem.pageHitRate 83.67
-system.physmem_0.actEnergy 16243500
-system.physmem_0.preEnergy 8614650
-system.physmem_0.readEnergy 75484080
-system.physmem_0.writeEnergy 156600
-system.physmem_0.refreshEnergy 1895549760.000000
-system.physmem_0.actBackEnergy 464945010
-system.physmem_0.preBackEnergy 99199680
-system.physmem_0.actPowerDownEnergy 4173482430
-system.physmem_0.prePowerDownEnergy 3272736480
-system.physmem_0.selfRefreshEnergy 9883191315
-system.physmem_0.totalEnergy 19894073865
-system.physmem_0.averagePower 339.947098
-system.physmem_0.totalIdleTime 57233116090
-system.physmem_0.memoryStateTime::IDLE 194944250
-system.physmem_0.memoryStateTime::REF 806364000
-system.physmem_0.memoryStateTime::SREF 39558059500
-system.physmem_0.memoryStateTime::PRE_PDN 8522710566
-system.physmem_0.memoryStateTime::ACT 286661660
-system.physmem_0.memoryStateTime::ACT_PDN 9152346024
-system.physmem_1.actEnergy 5255040
-system.physmem_1.preEnergy 2785530
-system.physmem_1.readEnergy 56527380
-system.physmem_1.writeEnergy 114840
-system.physmem_1.refreshEnergy 247699920.000000
-system.physmem_1.actBackEnergy 125328180
-system.physmem_1.preBackEnergy 13397280
-system.physmem_1.actPowerDownEnergy 772336890
-system.physmem_1.prePowerDownEnergy 242624160
-system.physmem_1.selfRefreshEnergy 13451278005
-system.physmem_1.totalEnergy 14917407225
-system.physmem_1.averagePower 254.906533
-system.physmem_1.totalIdleTime 58211272096
-system.physmem_1.memoryStateTime::IDLE 21634250
-system.physmem_1.memoryStateTime::REF 105218000
-system.physmem_1.memoryStateTime::SREF 55885668250
-system.physmem_1.memoryStateTime::PRE_PDN 631842954
-system.physmem_1.memoryStateTime::ACT 182961654
-system.physmem_1.memoryStateTime::ACT_PDN 1693760892
-system.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.cpu.branchPred.lookups 28121660
-system.cpu.branchPred.condPredicted 23134709
-system.cpu.branchPred.condIncorrect 844714
-system.cpu.branchPred.BTBLookups 11731332
-system.cpu.branchPred.BTBHits 11630363
-system.cpu.branchPred.BTBCorrect 0
-system.cpu.branchPred.BTBHitPct 99.139322
-system.cpu.branchPred.usedRAS 80725
-system.cpu.branchPred.RASInCorrect 95
-system.cpu.branchPred.indirectLookups 28301
-system.cpu.branchPred.indirectHits 25845
-system.cpu.branchPred.indirectMisses 2456
-system.cpu.branchPredindirectMispredicted 243
-system.cpu_clk_domain.clock 500
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.hits 0
-system.cpu.dstage2_mmu.stage2_tlb.misses 0
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.cpu.dtb.walker.walks 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dtb.walker.walkRequestOrigin::total 0
-system.cpu.dtb.inst_hits 0
-system.cpu.dtb.inst_misses 0
-system.cpu.dtb.read_hits 0
-system.cpu.dtb.read_misses 0
-system.cpu.dtb.write_hits 0
-system.cpu.dtb.write_misses 0
-system.cpu.dtb.flush_tlb 0
-system.cpu.dtb.flush_tlb_mva 0
-system.cpu.dtb.flush_tlb_mva_asid 0
-system.cpu.dtb.flush_tlb_asid 0
-system.cpu.dtb.flush_entries 0
-system.cpu.dtb.align_faults 0
-system.cpu.dtb.prefetch_faults 0
-system.cpu.dtb.domain_faults 0
-system.cpu.dtb.perms_faults 0
-system.cpu.dtb.read_accesses 0
-system.cpu.dtb.write_accesses 0
-system.cpu.dtb.inst_accesses 0
-system.cpu.dtb.hits 0
-system.cpu.dtb.misses 0
-system.cpu.dtb.accesses 0
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
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-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341
-system.cpu.l2cache.ReadExReq_mshr_misses::total 341
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 700
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3442
-system.cpu.l2cache.demand_mshr_misses::total 4142
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 700
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3442
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332
-system.cpu.l2cache.overall_mshr_misses::total 320474
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500
-system.cpu.l2cache.demand_mshr_miss_latency::total 692500000
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
-system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441
-system.cpu.toL2Bus.snoop_filter.tot_requests 10943138
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928
-system.cpu.toL2Bus.snoop_filter.tot_snoops 301927
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.cpu.toL2Bus.trans_dist::ReadResp 5245799
-system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271
-system.cpu.toL2Bus.trans_dist::WritebackClean 10884
-system.cpu.toL2Bus.trans_dist::CleanEvict 25
-system.cpu.toL2Bus.trans_dist::HardPFReq 318221
-system.cpu.toL2Bus.trans_dist::HardPFResp 6
-system.cpu.toL2Bus.trans_dist::UpgradeReq 5
-system.cpu.toL2Bus.trans_dist::UpgradeResp 5
-system.cpu.toL2Bus.trans_dist::ReadExReq 226252
-system.cpu.toL2Bus.trans_dist::ReadExResp 226252
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 908
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936
-system.cpu.toL2Bus.pkt_count::total 16415200
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048
-system.cpu.toL2Bus.pkt_size::total 700360832
-system.cpu.toL2Bus.snoops 318326
-system.cpu.toL2Bus.snoopTraffic 5120
-system.cpu.toL2Bus.snoop_fanout::samples 5790377
-system.cpu.toL2Bus.snoop_fanout::mean 0.052651
-system.cpu.toL2Bus.snoop_fanout::stdev 0.223337
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73%
-system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00%
-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 2
-system.cpu.toL2Bus.snoop_fanout::total 5790377
-system.cpu.toL2Bus.reqLayer0.occupancy 10942650026
-system.cpu.toL2Bus.reqLayer0.utilization 18.7
-system.cpu.toL2Bus.snoopLayer0.occupancy 9032
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer0.occupancy 1362995
-system.cpu.toL2Bus.respLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer1.occupancy 8206721993
-system.cpu.toL2Bus.respLayer1.utilization 14.0
-system.membus.snoop_filter.tot_requests 18651
-system.membus.snoop_filter.hit_single_requests 3037
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000
-system.membus.trans_dist::ReadResp 18205
-system.membus.trans_dist::WritebackDirty 74
-system.membus.trans_dist::CleanEvict 25
-system.membus.trans_dist::UpgradeReq 6
-system.membus.trans_dist::ReadExReq 340
-system.membus.trans_dist::ReadExResp 340
-system.membus.trans_dist::ReadSharedReq 18206
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196
-system.membus.pkt_count::total 37196
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616
-system.membus.pkt_size::total 1191616
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 18552
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 18552 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 18552
-system.membus.reqLayer0.occupancy 29380556
-system.membus.reqLayer0.utilization 0.1
-system.membus.respLayer1.occupancy 97369032
-system.membus.respLayer1.utilization 0.2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=mcf mcf.in
-cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:268435455:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-()
-500
-()
-499
-()
-498
-()
-496
-()
-495
-()
-494
-()
-493
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
-443
-()
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-()
-440
-()
-439
-()
-438
-()
-436
-()
-435
-()
-433
-()
-432
-()
-431
-()
-428
-()
-427
-()
-425
-()
-424
-()
-423
-()
-420
-()
-419
-()
-416
-()
-414
-()
-413
-()
-412
-()
-407
-()
-406
-()
-405
-()
-404
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+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 18:41:19
-gem5 started Apr 3 2017 18:43:33
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 361613361500 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
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-final_tick 361613361500
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-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
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-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=true
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=1
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2 opList3 opList4
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList4]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1 opList2 opList3
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-()
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+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 19:05:53
-gem5 started Apr 3 2017 19:06:21
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87177
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 65721494500 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.065721
-sim_ticks 65721494500
-final_tick 65721494500
-sim_freq 1000000000000
-host_inst_rate 83517
-host_op_rate 147060
-host_tick_rate 34742064
-host_mem_usage 427260
-host_seconds 1891.70
-sim_insts 157988547
-sim_ops 278192464
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500
-system.physmem.bytes_read::cpu.inst 68800
-system.physmem.bytes_read::cpu.data 1892544
-system.physmem.bytes_read::total 1961344
-system.physmem.bytes_inst_read::cpu.inst 68800
-system.physmem.bytes_inst_read::total 68800
-system.physmem.bytes_written::writebacks 19136
-system.physmem.bytes_written::total 19136
-system.physmem.num_reads::cpu.inst 1075
-system.physmem.num_reads::cpu.data 29571
-system.physmem.num_reads::total 30646
-system.physmem.num_writes::writebacks 299
-system.physmem.num_writes::total 299
-system.physmem.bw_read::cpu.inst 1046842
-system.physmem.bw_read::cpu.data 28796424
-system.physmem.bw_read::total 29843265
-system.physmem.bw_inst_read::cpu.inst 1046842
-system.physmem.bw_inst_read::total 1046842
-system.physmem.bw_write::writebacks 291168
-system.physmem.bw_write::total 291168
-system.physmem.bw_total::writebacks 291168
-system.physmem.bw_total::cpu.inst 1046842
-system.physmem.bw_total::cpu.data 28796424
-system.physmem.bw_total::total 30134433
-system.physmem.readReqs 30646
-system.physmem.writeReqs 299
-system.physmem.readBursts 30646
-system.physmem.writeBursts 299
-system.physmem.bytesReadDRAM 1952832
-system.physmem.bytesReadWrQ 8512
-system.physmem.bytesWritten 17216
-system.physmem.bytesReadSys 1961344
-system.physmem.bytesWrittenSys 19136
-system.physmem.servicedByWrQ 133
-system.physmem.mergedWrBursts 0
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 1937
-system.physmem.perBankRdBursts::1 2081
-system.physmem.perBankRdBursts::2 2039
-system.physmem.perBankRdBursts::3 1941
-system.physmem.perBankRdBursts::4 2068
-system.physmem.perBankRdBursts::5 1911
-system.physmem.perBankRdBursts::6 1977
-system.physmem.perBankRdBursts::7 1878
-system.physmem.perBankRdBursts::8 1945
-system.physmem.perBankRdBursts::9 1939
-system.physmem.perBankRdBursts::10 1805
-system.physmem.perBankRdBursts::11 1794
-system.physmem.perBankRdBursts::12 1792
-system.physmem.perBankRdBursts::13 1800
-system.physmem.perBankRdBursts::14 1827
-system.physmem.perBankRdBursts::15 1779
-system.physmem.perBankWrBursts::0 8
-system.physmem.perBankWrBursts::1 125
-system.physmem.perBankWrBursts::2 25
-system.physmem.perBankWrBursts::3 26
-system.physmem.perBankWrBursts::4 54
-system.physmem.perBankWrBursts::5 8
-system.physmem.perBankWrBursts::6 14
-system.physmem.perBankWrBursts::7 0
-system.physmem.perBankWrBursts::8 0
-system.physmem.perBankWrBursts::9 6
-system.physmem.perBankWrBursts::10 3
-system.physmem.perBankWrBursts::11 0
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-system.physmem.perBankWrBursts::13 0
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-system.physmem.perBankWrBursts::15 0
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 0
-system.physmem.totGap 65721290500
-system.physmem.readPktSize::0 0
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-system.physmem.readPktSize::3 0
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-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 30646
-system.physmem.writePktSize::0 0
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-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 299
-system.physmem.rdQLenPdf::0 29942
-system.physmem.rdQLenPdf::1 423
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-system.physmem.rdQLenPdf::4 5
-system.physmem.rdQLenPdf::5 1
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-system.physmem.rdQLenPdf::13 0
-system.physmem.rdQLenPdf::14 0
-system.physmem.rdQLenPdf::15 0
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-system.physmem.rdQLenPdf::17 0
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-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
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-system.physmem.rdQLenPdf::24 0
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-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233
-system.cpu.l2cache.demand_miss_rate::total 0.014743
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233
-system.cpu.l2cache.overall_miss_rate::total 0.014743
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178
-system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178
-system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830
-system.cpu.l2cache.blocked_cycles::no_mshrs 0
-system.cpu.l2cache.blocked_cycles::no_targets 0
-system.cpu.l2cache.blocked::no_mshrs 0
-system.cpu.l2cache.blocked::no_targets 0
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan
-system.cpu.l2cache.writebacks::writebacks 299
-system.cpu.l2cache.writebacks::total 299
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28996
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29571
-system.cpu.l2cache.demand_mshr_misses::total 30646
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29571
-system.cpu.l2cache.overall_mshr_misses::total 30646
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000
-system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000
-system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830
-system.cpu.toL2Bus.snoop_filter.tot_requests 4152301
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23
-system.cpu.toL2Bus.snoop_filter.tot_snoops 330
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500
-system.cpu.toL2Bus.trans_dist::ReadResp 1996764
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201
-system.cpu.toL2Bus.trans_dist::WritebackClean 86
-system.cpu.toL2Bus.trans_dist::CleanEvict 6988
-system.cpu.toL2Bus.trans_dist::ReadExReq 81942
-system.cpu.toL2Bus.trans_dist::ReadExResp 81942
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719
-system.cpu.toL2Bus.pkt_count::total 6231007
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448
-system.cpu.toL2Bus.pkt_size::total 265324416
-system.cpu.toL2Bus.snoops 680
-system.cpu.toL2Bus.snoopTraffic 19136
-system.cpu.toL2Bus.snoop_fanout::samples 2079386
-system.cpu.toL2Bus.snoop_fanout::mean 0.000170
-system.cpu.toL2Bus.snoop_fanout::stdev 0.013047
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98%
-system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00%
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 1
-system.cpu.toL2Bus.snoop_fanout::total 2079386
-system.cpu.toL2Bus.reqLayer0.occupancy 4143138500
-system.cpu.toL2Bus.reqLayer0.utilization 6.3
-system.cpu.toL2Bus.respLayer0.occupancy 1652498
-system.cpu.toL2Bus.respLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer1.occupancy 3116407500
-system.cpu.toL2Bus.respLayer1.utilization 4.7
-system.membus.snoop_filter.tot_requests 30996
-system.membus.snoop_filter.hit_single_requests 350
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500
-system.membus.trans_dist::ReadResp 1650
-system.membus.trans_dist::WritebackDirty 299
-system.membus.trans_dist::CleanEvict 51
-system.membus.trans_dist::ReadExReq 28996
-system.membus.trans_dist::ReadExResp 28996
-system.membus.trans_dist::ReadSharedReq 1650
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642
-system.membus.pkt_count::total 61642
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480
-system.membus.pkt_size::total 1980480
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 30646
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 30646 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 30646
-system.membus.reqLayer0.occupancy 43591500
-system.membus.reqLayer0.utilization 0.1
-system.membus.respLayer1.occupancy 161486250
-system.membus.respLayer1.utilization 0.2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:268435455:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
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-95
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 19:05:53
-gem5 started Apr 3 2017 19:08:56
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 90898
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 366229314500 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.366229
-sim_ticks 366229314500
-final_tick 366229314500
-sim_freq 1000000000000
-host_inst_rate 440271
-host_op_rate 775247
-host_tick_rate 1020581695
-host_mem_usage 422392
-host_seconds 358.84
-sim_insts 157988548
-sim_ops 278192465
-system.voltage_domain.voltage 1
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-system.cpu.op_class::MemRead 90779371 32.63% 88.70%
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-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500
-system.membus.trans_dist::ReadResp 1022
-system.membus.trans_dist::WritebackDirty 104
-system.membus.trans_dist::CleanEvict 14
-system.membus.trans_dist::ReadExReq 29024
-system.membus.trans_dist::ReadExResp 29024
-system.membus.trans_dist::ReadSharedReq 1022
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210
-system.membus.pkt_count::total 60210
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600
-system.membus.pkt_size::total 1929600
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 30046
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 30046 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 30046
-system.membus.reqLayer0.occupancy 30614500
-system.membus.reqLayer0.utilization 0.0
-system.membus.respLayer1.occupancy 150230000
-system.membus.respLayer1.utilization 0.0
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import mcf
-
-workload = mcf(isa, opsys, 'smred')
-root.system.cpu[0].workload = workload.makeProcess()
-root.system.physmem.range=AddrRange('256MB')
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:49:48
-gem5 executing on e108600-lin, pid 17449
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/minor-timing
-
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-info: Increasing stack size by one page.
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 132538562500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.132570 # Number of seconds simulated
-sim_ticks 132570000500 # Number of ticks simulated
-final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 373440 # Simulator instruction rate (inst/s)
-host_op_rate 393666 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 287300012 # Simulator tick rate (ticks/s)
-host_mem_usage 274936 # Number of bytes of host memory used
-host_seconds 461.43 # Real time elapsed on the host
-sim_insts 172317810 # Number of instructions simulated
-sim_ops 181650743 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
-system.physmem.bytes_read::total 247552 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3868 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 247552 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 305 # Per bank write bursts
-system.physmem.perBankRdBursts::1 217 # Per bank write bursts
-system.physmem.perBankRdBursts::2 135 # Per bank write bursts
-system.physmem.perBankRdBursts::3 313 # Per bank write bursts
-system.physmem.perBankRdBursts::4 306 # Per bank write bursts
-system.physmem.perBankRdBursts::5 305 # Per bank write bursts
-system.physmem.perBankRdBursts::6 273 # Per bank write bursts
-system.physmem.perBankRdBursts::7 222 # Per bank write bursts
-system.physmem.perBankRdBursts::8 248 # Per bank write bursts
-system.physmem.perBankRdBursts::9 218 # Per bank write bursts
-system.physmem.perBankRdBursts::10 296 # Per bank write bursts
-system.physmem.perBankRdBursts::11 200 # Per bank write bursts
-system.physmem.perBankRdBursts::12 183 # Per bank write bursts
-system.physmem.perBankRdBursts::13 218 # Per bank write bursts
-system.physmem.perBankRdBursts::14 224 # Per bank write bursts
-system.physmem.perBankRdBursts::15 205 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 132569899500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 3868 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation
-system.physmem.totQLat 82551750 # Total ticks spent queuing
-system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.01 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 2935 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34273500.39 # Average gap between requests
-system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ)
-system.physmem_0.averagePower 244.026270 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states
-system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ)
-system.physmem_1.averagePower 243.774090 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 49693872 # Number of BP lookups
-system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 400 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 265140001 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 172317810 # Number of instructions committed
-system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.538669 # CPI: cycles per instruction
-system.cpu.ipc 0.649913 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
-system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
-system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 181650743 # Class of committed instruction
-system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 42 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy
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-system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits
-system.cpu.dcache.overall_hits::total 40709647 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses
-system.cpu.dcache.overall_misses::total 2405 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses
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-system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses
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-system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 2861 # number of replacements
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
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-system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2587 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
-system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2161 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3869 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 2777 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 3868 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3868 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 18:24:01
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59389
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
-
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 85986203000 because exiting with last active thread context
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.085986
-sim_ticks 85986203000
-final_tick 85986203000
-sim_freq 1000000000000
-host_inst_rate 102101
-host_op_rate 107631
-host_tick_rate 50952414
-host_mem_usage 284176
-host_seconds 1687.58
-sim_insts 172303022
-sim_ops 181635954
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000
-system.physmem.bytes_read::cpu.inst 651776
-system.physmem.bytes_read::cpu.data 193408
-system.physmem.bytes_read::cpu.l2cache.prefetcher 71680
-system.physmem.bytes_read::total 916864
-system.physmem.bytes_inst_read::cpu.inst 651776
-system.physmem.bytes_inst_read::total 651776
-system.physmem.num_reads::cpu.inst 10184
-system.physmem.num_reads::cpu.data 3022
-system.physmem.num_reads::cpu.l2cache.prefetcher 1120
-system.physmem.num_reads::total 14326
-system.physmem.bw_read::cpu.inst 7580007
-system.physmem.bw_read::cpu.data 2249291
-system.physmem.bw_read::cpu.l2cache.prefetcher 833622
-system.physmem.bw_read::total 10662920
-system.physmem.bw_inst_read::cpu.inst 7580007
-system.physmem.bw_inst_read::total 7580007
-system.physmem.bw_total::cpu.inst 7580007
-system.physmem.bw_total::cpu.data 2249291
-system.physmem.bw_total::cpu.l2cache.prefetcher 833622
-system.physmem.bw_total::total 10662920
-system.physmem.readReqs 14327
-system.physmem.writeReqs 0
-system.physmem.readBursts 14327
-system.physmem.writeBursts 0
-system.physmem.bytesReadDRAM 916928
-system.physmem.bytesReadWrQ 0
-system.physmem.bytesWritten 0
-system.physmem.bytesReadSys 916928
-system.physmem.bytesWrittenSys 0
-system.physmem.servicedByWrQ 0
-system.physmem.mergedWrBursts 0
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 1379
-system.physmem.perBankRdBursts::1 501
-system.physmem.perBankRdBursts::2 5100
-system.physmem.perBankRdBursts::3 815
-system.physmem.perBankRdBursts::4 2265
-system.physmem.perBankRdBursts::5 427
-system.physmem.perBankRdBursts::6 394
-system.physmem.perBankRdBursts::7 623
-system.physmem.perBankRdBursts::8 270
-system.physmem.perBankRdBursts::9 230
-system.physmem.perBankRdBursts::10 354
-system.physmem.perBankRdBursts::11 345
-system.physmem.perBankRdBursts::12 321
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-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199
-system.cpu.toL2Bus.pkt_count::total 378544
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816
-system.cpu.toL2Bus.pkt_size::total 16129152
-system.cpu.toL2Bus.snoops 2338
-system.cpu.toL2Bus.snoopTraffic 64
-system.cpu.toL2Bus.snoop_fanout::samples 128862
-system.cpu.toL2Bus.snoop_fanout::mean 0.088172
-system.cpu.toL2Bus.snoop_fanout::stdev 0.283573
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18%
-system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00%
-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 2
-system.cpu.toL2Bus.snoop_fanout::total 128862
-system.cpu.toL2Bus.reqLayer0.occupancy 251508000
-system.cpu.toL2Bus.reqLayer0.utilization 0.3
-system.cpu.toL2Bus.respLayer0.occupancy 80437981
-system.cpu.toL2Bus.respLayer0.utilization 0.1
-system.cpu.toL2Bus.respLayer1.occupancy 109359491
-system.cpu.toL2Bus.respLayer1.utilization 0.1
-system.membus.snoop_filter.tot_requests 14328
-system.membus.snoop_filter.hit_single_requests 10478
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000
-system.membus.trans_dist::ReadResp 14090
-system.membus.trans_dist::UpgradeReq 1
-system.membus.trans_dist::ReadExReq 235
-system.membus.trans_dist::ReadExResp 235
-system.membus.trans_dist::ReadSharedReq 14092
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653
-system.membus.pkt_count::total 28653
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800
-system.membus.pkt_size::total 916800
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 14328
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 14328 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 14328
-system.membus.reqLayer0.occupancy 18011178
-system.membus.reqLayer0.utilization 0.0
-system.membus.respLayer1.occupancy 77254535
-system.membus.respLayer1.utilization 0.1
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=true
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=1
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2 opList3 opList4
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList4]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1 opList2 opList3
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=twolf smred
-cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 31 2017 16:17:52
-gem5 started Mar 31 2017 16:18:04
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50433
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing
-
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 102720088500 because exiting with last active thread context
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.102720
-sim_ticks 102720088500
-final_tick 102720088500
-sim_freq 1000000000000
-host_inst_rate 108111
-host_op_rate 181205
-host_tick_rate 84085065
-host_mem_usage 318048
-host_seconds 1221.62
-sim_insts 132071192
-sim_ops 221363384
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.physmem.bytes_read::cpu.inst 235072
-system.physmem.bytes_read::cpu.data 130880
-system.physmem.bytes_read::total 365952
-system.physmem.bytes_inst_read::cpu.inst 235072
-system.physmem.bytes_inst_read::total 235072
-system.physmem.num_reads::cpu.inst 3673
-system.physmem.num_reads::cpu.data 2045
-system.physmem.num_reads::total 5718
-system.physmem.bw_read::cpu.inst 2288472
-system.physmem.bw_read::cpu.data 1274142
-system.physmem.bw_read::total 3562614
-system.physmem.bw_inst_read::cpu.inst 2288472
-system.physmem.bw_inst_read::total 2288472
-system.physmem.bw_total::cpu.inst 2288472
-system.physmem.bw_total::cpu.data 1274142
-system.physmem.bw_total::total 3562614
-system.physmem.readReqs 5718
-system.physmem.writeReqs 0
-system.physmem.readBursts 5718
-system.physmem.writeBursts 0
-system.physmem.bytesReadDRAM 365952
-system.physmem.bytesReadWrQ 0
-system.physmem.bytesWritten 0
-system.physmem.bytesReadSys 365952
-system.physmem.bytesWrittenSys 0
-system.physmem.servicedByWrQ 0
-system.physmem.mergedWrBursts 0
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 308
-system.physmem.perBankRdBursts::1 393
-system.physmem.perBankRdBursts::2 481
-system.physmem.perBankRdBursts::3 362
-system.physmem.perBankRdBursts::4 367
-system.physmem.perBankRdBursts::5 342
-system.physmem.perBankRdBursts::6 448
-system.physmem.perBankRdBursts::7 369
-system.physmem.perBankRdBursts::8 368
-system.physmem.perBankRdBursts::9 301
-system.physmem.perBankRdBursts::10 254
-system.physmem.perBankRdBursts::11 270
-system.physmem.perBankRdBursts::12 266
-system.physmem.perBankRdBursts::13 486
-system.physmem.perBankRdBursts::14 412
-system.physmem.perBankRdBursts::15 291
-system.physmem.perBankWrBursts::0 0
-system.physmem.perBankWrBursts::1 0
-system.physmem.perBankWrBursts::2 0
-system.physmem.perBankWrBursts::3 0
-system.physmem.perBankWrBursts::4 0
-system.physmem.perBankWrBursts::5 0
-system.physmem.perBankWrBursts::6 0
-system.physmem.perBankWrBursts::7 0
-system.physmem.perBankWrBursts::8 0
-system.physmem.perBankWrBursts::9 0
-system.physmem.perBankWrBursts::10 0
-system.physmem.perBankWrBursts::11 0
-system.physmem.perBankWrBursts::12 0
-system.physmem.perBankWrBursts::13 0
-system.physmem.perBankWrBursts::14 0
-system.physmem.perBankWrBursts::15 0
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 0
-system.physmem.totGap 102719826000
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 0
-system.physmem.readPktSize::3 0
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 5718
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 0
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 0
-system.physmem.rdQLenPdf::0 4465
-system.physmem.rdQLenPdf::1 986
-system.physmem.rdQLenPdf::2 224
-system.physmem.rdQLenPdf::3 32
-system.physmem.rdQLenPdf::4 9
-system.physmem.rdQLenPdf::5 2
-system.physmem.rdQLenPdf::6 0
-system.physmem.rdQLenPdf::7 0
-system.physmem.rdQLenPdf::8 0
-system.physmem.rdQLenPdf::9 0
-system.physmem.rdQLenPdf::10 0
-system.physmem.rdQLenPdf::11 0
-system.physmem.rdQLenPdf::12 0
-system.physmem.rdQLenPdf::13 0
-system.physmem.rdQLenPdf::14 0
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 0
-system.physmem.wrQLenPdf::1 0
-system.physmem.wrQLenPdf::2 0
-system.physmem.wrQLenPdf::3 0
-system.physmem.wrQLenPdf::4 0
-system.physmem.wrQLenPdf::5 0
-system.physmem.wrQLenPdf::6 0
-system.physmem.wrQLenPdf::7 0
-system.physmem.wrQLenPdf::8 0
-system.physmem.wrQLenPdf::9 0
-system.physmem.wrQLenPdf::10 0
-system.physmem.wrQLenPdf::11 0
-system.physmem.wrQLenPdf::12 0
-system.physmem.wrQLenPdf::13 0
-system.physmem.wrQLenPdf::14 0
-system.physmem.wrQLenPdf::15 0
-system.physmem.wrQLenPdf::16 0
-system.physmem.wrQLenPdf::17 0
-system.physmem.wrQLenPdf::18 0
-system.physmem.wrQLenPdf::19 0
-system.physmem.wrQLenPdf::20 0
-system.physmem.wrQLenPdf::21 0
-system.physmem.wrQLenPdf::22 0
-system.physmem.wrQLenPdf::23 0
-system.physmem.wrQLenPdf::24 0
-system.physmem.wrQLenPdf::25 0
-system.physmem.wrQLenPdf::26 0
-system.physmem.wrQLenPdf::27 0
-system.physmem.wrQLenPdf::28 0
-system.physmem.wrQLenPdf::29 0
-system.physmem.wrQLenPdf::30 0
-system.physmem.wrQLenPdf::31 0
-system.physmem.wrQLenPdf::32 0
-system.physmem.wrQLenPdf::33 0
-system.physmem.wrQLenPdf::34 0
-system.physmem.wrQLenPdf::35 0
-system.physmem.wrQLenPdf::36 0
-system.physmem.wrQLenPdf::37 0
-system.physmem.wrQLenPdf::38 0
-system.physmem.wrQLenPdf::39 0
-system.physmem.wrQLenPdf::40 0
-system.physmem.wrQLenPdf::41 0
-system.physmem.wrQLenPdf::42 0
-system.physmem.wrQLenPdf::43 0
-system.physmem.wrQLenPdf::44 0
-system.physmem.wrQLenPdf::45 0
-system.physmem.wrQLenPdf::46 0
-system.physmem.wrQLenPdf::47 0
-system.physmem.wrQLenPdf::48 0
-system.physmem.wrQLenPdf::49 0
-system.physmem.wrQLenPdf::50 0
-system.physmem.wrQLenPdf::51 0
-system.physmem.wrQLenPdf::52 0
-system.physmem.wrQLenPdf::53 0
-system.physmem.wrQLenPdf::54 0
-system.physmem.wrQLenPdf::55 0
-system.physmem.wrQLenPdf::56 0
-system.physmem.wrQLenPdf::57 0
-system.physmem.wrQLenPdf::58 0
-system.physmem.wrQLenPdf::59 0
-system.physmem.wrQLenPdf::60 0
-system.physmem.wrQLenPdf::61 0
-system.physmem.wrQLenPdf::62 0
-system.physmem.wrQLenPdf::63 0
-system.physmem.bytesPerActivate::samples 1260
-system.physmem.bytesPerActivate::mean 288.914286
-system.physmem.bytesPerActivate::gmean 165.287070
-system.physmem.bytesPerActivate::stdev 321.712301
-system.physmem.bytesPerActivate::0-127 547 43.41% 43.41%
-system.physmem.bytesPerActivate::128-255 272 21.59% 65.00%
-system.physmem.bytesPerActivate::256-383 106 8.41% 73.41%
-system.physmem.bytesPerActivate::384-511 51 4.05% 77.46%
-system.physmem.bytesPerActivate::512-639 47 3.73% 81.19%
-system.physmem.bytesPerActivate::640-767 65 5.16% 86.35%
-system.physmem.bytesPerActivate::768-895 23 1.83% 88.17%
-system.physmem.bytesPerActivate::896-1023 25 1.98% 90.16%
-system.physmem.bytesPerActivate::1024-1151 124 9.84% 100.00%
-system.physmem.bytesPerActivate::total 1260
-system.physmem.totQLat 196407250
-system.physmem.totMemAccLat 303619750
-system.physmem.totBusLat 28590000
-system.physmem.avgQLat 34348.94
-system.physmem.avgBusLat 5000.00
-system.physmem.avgMemAccLat 53098.94
-system.physmem.avgRdBW 3.56
-system.physmem.avgWrBW 0.00
-system.physmem.avgRdBWSys 3.56
-system.physmem.avgWrBWSys 0.00
-system.physmem.peakBW 12800.00
-system.physmem.busUtil 0.03
-system.physmem.busUtilRead 0.03
-system.physmem.busUtilWrite 0.00
-system.physmem.avgRdQLen 1.05
-system.physmem.avgWrQLen 0.00
-system.physmem.readRowHits 4449
-system.physmem.writeRowHits 0
-system.physmem.readRowHitRate 77.81
-system.physmem.writeRowHitRate nan
-system.physmem.avgGap 17964292.76
-system.physmem.pageHitRate 77.81
-system.physmem_0.actEnergy 5397840
-system.physmem_0.preEnergy 2846250
-system.physmem_0.readEnergy 21919800
-system.physmem_0.writeEnergy 0
-system.physmem_0.refreshEnergy 308549280.000000
-system.physmem_0.actBackEnergy 94558440
-system.physmem_0.preBackEnergy 17132160
-system.physmem_0.actPowerDownEnergy 742713990
-system.physmem_0.prePowerDownEnergy 449076000
-system.physmem_0.selfRefreshEnergy 23986517265
-system.physmem_0.totalEnergy 25628757345
-system.physmem_0.averagePower 249.500927
-system.physmem_0.totalIdleTime 102467665750
-system.physmem_0.memoryStateTime::IDLE 33083500
-system.physmem_0.memoryStateTime::REF 131252000
-system.physmem_0.memoryStateTime::SREF 99669779750
-system.physmem_0.memoryStateTime::PRE_PDN 1169466500
-system.physmem_0.memoryStateTime::ACT 87760750
-system.physmem_0.memoryStateTime::ACT_PDN 1628746000
-system.physmem_1.actEnergy 3662820
-system.physmem_1.preEnergy 1935450
-system.physmem_1.readEnergy 18906720
-system.physmem_1.writeEnergy 0
-system.physmem_1.refreshEnergy 232333920.000000
-system.physmem_1.actBackEnergy 74817060
-system.physmem_1.preBackEnergy 12559200
-system.physmem_1.actPowerDownEnergy 593057070
-system.physmem_1.prePowerDownEnergy 320340000
-system.physmem_1.selfRefreshEnergy 24140187000
-system.physmem_1.totalEnergy 25397799240
-system.physmem_1.averagePower 247.252505
-system.physmem_1.totalIdleTime 102523033750
-system.physmem_1.memoryStateTime::IDLE 23868000
-system.physmem_1.memoryStateTime::REF 98790000
-system.physmem_1.memoryStateTime::SREF 100388528750
-system.physmem_1.memoryStateTime::PRE_PDN 834205000
-system.physmem_1.memoryStateTime::ACT 74170500
-system.physmem_1.memoryStateTime::ACT_PDN 1300526250
-system.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.cpu.branchPred.lookups 40475084
-system.cpu.branchPred.condPredicted 40475084
-system.cpu.branchPred.condIncorrect 6616129
-system.cpu.branchPred.BTBLookups 34806523
-system.cpu.branchPred.BTBHits 0
-system.cpu.branchPred.BTBCorrect 0
-system.cpu.branchPred.BTBHitPct 0.000000
-system.cpu.branchPred.usedRAS 3130762
-system.cpu.branchPred.RASInCorrect 590891
-system.cpu.branchPred.indirectLookups 34806523
-system.cpu.branchPred.indirectHits 9997741
-system.cpu.branchPred.indirectMisses 24808782
-system.cpu.branchPredindirectMispredicted 4890378
-system.cpu_clk_domain.clock 500
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.cpu.apic_clk_domain.clock 8000
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.cpu.workload.numSyscalls 400
-system.cpu.pwrStateResidencyTicks::ON 102720088500
-system.cpu.numCycles 205440178
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.fetch.icacheStallCycles 45893457
-system.cpu.fetch.Insts 415890076
-system.cpu.fetch.Branches 40475084
-system.cpu.fetch.predictedBranches 13128503
-system.cpu.fetch.Cycles 151898082
-system.cpu.fetch.SquashCycles 14677482
-system.cpu.fetch.TlbCycles 200
-system.cpu.fetch.MiscStallCycles 5835
-system.cpu.fetch.PendingTrapStallCycles 64355
-system.cpu.fetch.PendingQuiesceStallCycles 603
-system.cpu.fetch.IcacheWaitRetryStallCycles 216
-system.cpu.fetch.CacheLines 40893606
-system.cpu.fetch.IcacheSquashes 1496125
-system.cpu.fetch.ItlbSquashes 12
-system.cpu.fetch.rateDist::samples 205201489
-system.cpu.fetch.rateDist::mean 3.402316
-system.cpu.fetch.rateDist::stdev 3.658034
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
-system.cpu.fetch.rateDist::0 98918093 48.21% 48.21%
-system.cpu.fetch.rateDist::1 5142251 2.51% 50.71%
-system.cpu.fetch.rateDist::2 5340115 2.60% 53.31%
-system.cpu.fetch.rateDist::3 5342270 2.60% 55.92%
-system.cpu.fetch.rateDist::4 5947887 2.90% 58.82%
-system.cpu.fetch.rateDist::5 5817548 2.84% 61.65%
-system.cpu.fetch.rateDist::6 5684311 2.77% 64.42%
-system.cpu.fetch.rateDist::7 4746260 2.31% 66.73%
-system.cpu.fetch.rateDist::8 68262754 33.27% 100.00%
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
-system.cpu.fetch.rateDist::min_value 0
-system.cpu.fetch.rateDist::max_value 8
-system.cpu.fetch.rateDist::total 205201489
-system.cpu.fetch.branchRate 0.197016
-system.cpu.fetch.rate 2.024385
-system.cpu.decode.IdleCycles 31935868
-system.cpu.decode.BlockedCycles 86571071
-system.cpu.decode.RunCycles 61623221
-system.cpu.decode.UnblockCycles 17732588
-system.cpu.decode.SquashCycles 7338741
-system.cpu.decode.DecodedInsts 585423984
-system.cpu.rename.SquashCycles 7338741
-system.cpu.rename.IdleCycles 41662198
-system.cpu.rename.BlockCycles 46227032
-system.cpu.rename.serializeStallCycles 28975
-system.cpu.rename.RunCycles 68218755
-system.cpu.rename.UnblockCycles 41725788
-system.cpu.rename.RenamedInsts 547333443
-system.cpu.rename.ROBFullEvents 1805
-system.cpu.rename.IQFullEvents 36710058
-system.cpu.rename.LQFullEvents 4936211
-system.cpu.rename.SQFullEvents 172839
-system.cpu.rename.RenamedOperands 624155655
-system.cpu.rename.RenameLookups 1473918429
-system.cpu.rename.int_rename_lookups 966803164
-system.cpu.rename.fp_rename_lookups 14714209
-system.cpu.rename.CommittedMaps 259429450
-system.cpu.rename.UndoneMaps 364726205
-system.cpu.rename.serializingInsts 2257
-system.cpu.rename.tempSerializingInsts 2274
-system.cpu.rename.skidInsts 89803547
-system.cpu.memDep0.insertedLoads 127813041
-system.cpu.memDep0.insertedStores 45569331
-system.cpu.memDep0.conflictingLoads 76700066
-system.cpu.memDep0.conflictingStores 25076087
-system.cpu.iq.iqInstsAdded 486700641
-system.cpu.iq.iqNonSpecInstsAdded 63617
-system.cpu.iq.iqInstsIssued 336591190
-system.cpu.iq.iqSquashedInstsIssued 1075815
-system.cpu.iq.iqSquashedInstsExamined 265400873
-system.cpu.iq.iqSquashedOperandsExamined 520101528
-system.cpu.iq.iqSquashedNonSpecRemoved 62372
-system.cpu.iq.issued_per_cycle::samples 205201489
-system.cpu.iq.issued_per_cycle::mean 1.640296
-system.cpu.iq.issued_per_cycle::stdev 1.801230
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
-system.cpu.iq.issued_per_cycle::0 72558251 35.36% 35.36%
-system.cpu.iq.issued_per_cycle::1 46563358 22.69% 58.05%
-system.cpu.iq.issued_per_cycle::2 32833586 16.00% 74.05%
-system.cpu.iq.issued_per_cycle::3 20829408 10.15% 84.20%
-system.cpu.iq.issued_per_cycle::4 14957393 7.29% 91.49%
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-system.cpu.l2cache.tags.warmup_cycle 0
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-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.174500
-system.cpu.l2cache.tags.tag_accesses 145758
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-system.cpu.toL2Bus.snoop_filter.tot_requests 18037
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 6582
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0
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-system.cpu.toL2Bus.trans_dist::ReadResp 9531
-system.cpu.toL2Bus.trans_dist::WritebackDirty 22
-system.cpu.toL2Bus.trans_dist::WritebackClean 6438
-system.cpu.toL2Bus.trans_dist::CleanEvict 40
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-system.cpu.toL2Bus.trans_dist::ReadSharedReq 607
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5286
-system.cpu.toL2Bus.pkt_count::total 29082
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216
-system.cpu.toL2Bus.pkt_size::total 1088960
-system.cpu.toL2Bus.snoops 491
-system.cpu.toL2Bus.snoopTraffic 31424
-system.cpu.toL2Bus.snoop_fanout::samples 11537
-system.cpu.toL2Bus.snoop_fanout::mean 0.091878
-system.cpu.toL2Bus.snoop_fanout::stdev 0.288867
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 10477 90.81% 90.81%
-system.cpu.toL2Bus.snoop_fanout::1 1060 9.19% 100.00%
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 1
-system.cpu.toL2Bus.snoop_fanout::total 11537
-system.cpu.toL2Bus.reqLayer0.occupancy 15478500
-system.cpu.toL2Bus.reqLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer0.occupancy 13386000
-system.cpu.toL2Bus.respLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer1.occupancy 3428499
-system.cpu.toL2Bus.respLayer1.utilization 0.0
-system.membus.snoop_filter.tot_requests 5718
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 102720088500
-system.membus.trans_dist::ReadResp 4211
-system.membus.trans_dist::ReadExReq 1507
-system.membus.trans_dist::ReadExResp 1507
-system.membus.trans_dist::ReadSharedReq 4211
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11436
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11436
-system.membus.pkt_count::total 11436
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 365952
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 365952
-system.membus.pkt_size::total 365952
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 5718
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 5718 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 5718
-system.membus.reqLayer0.occupancy 6956000
-system.membus.reqLayer0.utilization 0.0
-system.membus.respLayer1.occupancy 30307000
-system.membus.respLayer1.utilization 0.0
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from __future__ import print_function
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import twolf
-import os
-
-workload = twolf(isa, opsys, 'smred')
-root.system.cpu[0].workload = workload.makeProcess()
-cwd = root.system.cpu[0].workload[0].cwd
-
-#Remove two files who's presence or absence affects execution
-sav_file = os.path.join(cwd, workload.input_set + '.sav')
-sv2_file = os.path.join(cwd, workload.input_set + '.sv2')
-try:
- os.unlink(sav_file)
-except:
- print("Couldn't unlink ", sav_file)
-try:
- os.unlink(sv2_file)
-except:
- print("Couldn't unlink ", sv2_file)
projects / gem5.git / commitdiff